[mirror_ubuntu-artful-kernel.git] / include / asm-s390 / system.h

/*
 *  include/asm-s390/system.h
 *
 *  S390 version
 *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
 *
 *  Derived from "include/asm-i386/system.h"
 */

#ifndef __ASM_SYSTEM_H
#define __ASM_SYSTEM_H

#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/processor.h>

#ifdef __KERNEL__

struct task_struct;

extern struct task_struct *__switch_to(void *, void *);

#ifdef __s390x__
#define __FLAG_SHIFT 56
#else /* ! __s390x__ */
#define __FLAG_SHIFT 24
#endif /* ! __s390x__ */

static inline void save_fp_regs(s390_fp_regs *fpregs)
{
	asm volatile (
		"   std   0,8(%1)\n"
		"   std   2,24(%1)\n"
		"   std   4,40(%1)\n"
		"   std   6,56(%1)"
		: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
	if (!MACHINE_HAS_IEEE)
		return;
	asm volatile(
		"   stfpc 0(%1)\n"
		"   std   1,16(%1)\n"
		"   std   3,32(%1)\n"
		"   std   5,48(%1)\n"
		"   std   7,64(%1)\n"
		"   std   8,72(%1)\n"
		"   std   9,80(%1)\n"
		"   std   10,88(%1)\n"
		"   std   11,96(%1)\n"
		"   std   12,104(%1)\n"
		"   std   13,112(%1)\n"
		"   std   14,120(%1)\n"
		"   std   15,128(%1)\n"
		: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
}

static inline void restore_fp_regs(s390_fp_regs *fpregs)
{
	asm volatile (
		"   ld    0,8(%0)\n"
		"   ld    2,24(%0)\n"
		"   ld    4,40(%0)\n"
		"   ld    6,56(%0)"
		: : "a" (fpregs), "m" (*fpregs) );
	if (!MACHINE_HAS_IEEE)
		return;
	asm volatile(
		"   lfpc  0(%0)\n"
		"   ld    1,16(%0)\n"
		"   ld    3,32(%0)\n"
		"   ld    5,48(%0)\n"
		"   ld    7,64(%0)\n"
		"   ld    8,72(%0)\n"
		"   ld    9,80(%0)\n"
		"   ld    10,88(%0)\n"
		"   ld    11,96(%0)\n"
		"   ld    12,104(%0)\n"
		"   ld    13,112(%0)\n"
		"   ld    14,120(%0)\n"
		"   ld    15,128(%0)\n"
		: : "a" (fpregs), "m" (*fpregs) );
}

static inline void save_access_regs(unsigned int *acrs)
{
	asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
}

static inline void restore_access_regs(unsigned int *acrs)
{
	asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
}

#define switch_to(prev,next,last) do {					     \
	if (prev == next)						     \
		break;							     \
	save_fp_regs(&prev->thread.fp_regs);				     \
	restore_fp_regs(&next->thread.fp_regs);				     \
	save_access_regs(&prev->thread.acrs[0]);			     \
	restore_access_regs(&next->thread.acrs[0]);			     \
	prev = __switch_to(prev,next);					     \
} while (0)

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible.
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

#ifdef CONFIG_VIRT_CPU_ACCOUNTING
extern void account_user_vtime(struct task_struct *);
extern void account_system_vtime(struct task_struct *);
#endif

#define finish_arch_switch(prev) do {					     \
	set_fs(current->thread.mm_segment);				     \
	account_system_vtime(prev);					     \
} while (0)

#define nop() __asm__ __volatile__ ("nop")

#define xchg(ptr,x) \
  ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))

static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
{
	unsigned long addr, old;
	int shift;

        switch (size) {
	case 1:
		addr = (unsigned long) ptr;
		shift = (3 ^ (addr & 3)) << 3;
		addr ^= addr & 3;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  lr  0,%0\n"
			"    nr  0,%3\n"
			"    or  0,%2\n"
			"    cs  %0,0,0(%4)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(int *) addr)
			: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
			  "m" (*(int *) addr) : "memory", "cc", "0" );
		x = old >> shift;
		break;
	case 2:
		addr = (unsigned long) ptr;
		shift = (2 ^ (addr & 2)) << 3;
		addr ^= addr & 2;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  lr  0,%0\n"
			"    nr  0,%3\n"
			"    or  0,%2\n"
			"    cs  %0,0,0(%4)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(int *) addr)
			: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
			  "m" (*(int *) addr) : "memory", "cc", "0" );
		x = old >> shift;
		break;
	case 4:
		asm volatile (
			"    l   %0,0(%3)\n"
			"0:  cs  %0,%2,0(%3)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(int *) ptr)
			: "d" (x), "a" (ptr), "m" (*(int *) ptr)
			: "memory", "cc" );
		x = old;
		break;
#ifdef __s390x__
	case 8:
		asm volatile (
			"    lg  %0,0(%3)\n"
			"0:  csg %0,%2,0(%3)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(long *) ptr)
			: "d" (x), "a" (ptr), "m" (*(long *) ptr)
			: "memory", "cc" );
		x = old;
		break;
#endif /* __s390x__ */
        }
        return x;
}

/*
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */

#define __HAVE_ARCH_CMPXCHG 1

#define cmpxchg(ptr,o,n)\
	((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
					(unsigned long)(n),sizeof(*(ptr))))

static inline unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
	unsigned long addr, prev, tmp;
	int shift;

        switch (size) {
	case 1:
		addr = (unsigned long) ptr;
		shift = (3 ^ (addr & 3)) << 3;
		addr ^= addr & 3;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  nr  %0,%5\n"
                        "    lr  %1,%0\n"
			"    or  %0,%2\n"
			"    or  %1,%3\n"
			"    cs  %0,%1,0(%4)\n"
			"    jnl 1f\n"
			"    xr  %1,%0\n"
			"    nr  %1,%5\n"
			"    jnz 0b\n"
			"1:"
			: "=&d" (prev), "=&d" (tmp)
			: "d" (old << shift), "d" (new << shift), "a" (ptr),
			  "d" (~(255 << shift))
			: "memory", "cc" );
		return prev >> shift;
	case 2:
		addr = (unsigned long) ptr;
		shift = (2 ^ (addr & 2)) << 3;
		addr ^= addr & 2;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  nr  %0,%5\n"
                        "    lr  %1,%0\n"
			"    or  %0,%2\n"
			"    or  %1,%3\n"
			"    cs  %0,%1,0(%4)\n"
			"    jnl 1f\n"
			"    xr  %1,%0\n"
			"    nr  %1,%5\n"
			"    jnz 0b\n"
			"1:"
			: "=&d" (prev), "=&d" (tmp)
			: "d" (old << shift), "d" (new << shift), "a" (ptr),
			  "d" (~(65535 << shift))
			: "memory", "cc" );
		return prev >> shift;
	case 4:
		asm volatile (
			"    cs  %0,%2,0(%3)\n"
			: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
			: "memory", "cc" );
		return prev;
#ifdef __s390x__
	case 8:
		asm volatile (
			"    csg %0,%2,0(%3)\n"
			: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
			: "memory", "cc" );
		return prev;
#endif /* __s390x__ */
        }
        return old;
}

/*
 * Force strict CPU ordering.
 * And yes, this is required on UP too when we're talking
 * to devices.
 *
 * This is very similar to the ppc eieio/sync instruction in that is
 * does a checkpoint syncronisation & makes sure that 
 * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 */

#define eieio()  __asm__ __volatile__ ( "bcr 15,0" : : : "memory" ) 
# define SYNC_OTHER_CORES(x)   eieio() 
#define mb()    eieio()
#define rmb()   eieio()
#define wmb()   eieio()
#define read_barrier_depends() do { } while(0)
#define smp_mb()       mb()
#define smp_rmb()      rmb()
#define smp_wmb()      wmb()
#define smp_read_barrier_depends()    read_barrier_depends()
#define smp_mb__before_clear_bit()     smp_mb()
#define smp_mb__after_clear_bit()      smp_mb()


#define set_mb(var, value)      do { var = value; mb(); } while (0)
#define set_wmb(var, value)     do { var = value; wmb(); } while (0)

/* interrupt control.. */
#define local_irq_enable() ({ \
        unsigned long  __dummy; \
        __asm__ __volatile__ ( \
                "stosm 0(%1),0x03" \
		: "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
        })

#define local_irq_disable() ({ \
        unsigned long __flags; \
        __asm__ __volatile__ ( \
                "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
        __flags; \
        })

#define local_save_flags(x) \
        __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )

#define local_irq_restore(x) \
        __asm__ __volatile__("ssm   0(%0)" : : "a" (&x), "m" (x) : "memory")

#define irqs_disabled()			\
({					\
	unsigned long flags;		\
	local_save_flags(flags);	\
        !((flags >> __FLAG_SHIFT) & 3);	\
})

#ifdef __s390x__

#define __ctl_load(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
                "   lctlg 0,0,0(%0)\n" \
		"0: ex    %1,0(1)" \
		: : "a" (&array), "a" (((low)<<4)+(high)), \
		    "m" (*(addrtype *)(array)) : "1" ); \
	})

#define __ctl_store(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
		"   stctg 0,0,0(%1)\n" \
		"0: ex    %2,0(1)" \
		: "=m" (*(addrtype *)(array)) \
		: "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
	})

#define __ctl_set_bit(cr, bit) ({ \
        __u8 __dummy[24]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctg 0,0,0(%1)\n" \
                "    lctlg 0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    lg    0,0(%1)\n" \
                "    ogr   0,%3\n"       /* set the bit */ \
                "    stg   0,0(%1)\n" \
                "1:  ex    %2,6(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (1L<<(bit)) \
                : "cc", "0", "1" ); \
        })

#define __ctl_clear_bit(cr, bit) ({ \
        __u8 __dummy[16]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctg 0,0,0(%1)\n" \
                "    lctlg 0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    lg    0,0(%1)\n" \
                "    ngr   0,%3\n"       /* set the bit */ \
                "    stg   0,0(%1)\n" \
                "1:  ex    %2,6(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (~(1L<<(bit))) \
                : "cc", "0", "1" ); \
        })

#else /* __s390x__ */

#define __ctl_load(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
                "   lctl 0,0,0(%0)\n" \
		"0: ex    %1,0(1)" \
		: : "a" (&array), "a" (((low)<<4)+(high)), \
		    "m" (*(addrtype *)(array)) : "1" ); \
	})

#define __ctl_store(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
		"   stctl 0,0,0(%1)\n" \
		"0: ex    %2,0(1)" \
		: "=m" (*(addrtype *)(array)) \
		: "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
	})

#define __ctl_set_bit(cr, bit) ({ \
        __u8 __dummy[16]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctl 0,0,0(%1)\n" \
                "    lctl  0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    l     0,0(%1)\n" \
                "    or    0,%3\n"       /* set the bit */ \
                "    st    0,0(%1)\n" \
                "1:  ex    %2,4(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (1<<(bit)) \
                : "cc", "0", "1" ); \
        })

#define __ctl_clear_bit(cr, bit) ({ \
        __u8 __dummy[16]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctl 0,0,0(%1)\n" \
                "    lctl  0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    l     0,0(%1)\n" \
                "    nr    0,%3\n"       /* set the bit */ \
                "    st    0,0(%1)\n" \
                "1:  ex    %2,4(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (~(1<<(bit))) \
                : "cc", "0", "1" ); \
        })
#endif /* __s390x__ */

/* For spinlocks etc */
#define local_irq_save(x)	((x) = local_irq_disable())

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	local_save_flags(mask);
	__load_psw_mask(mask);
}

#define local_mcck_enable()  __set_psw_mask(PSW_KERNEL_BITS)
#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)

#ifdef CONFIG_SMP

extern void smp_ctl_set_bit(int cr, int bit);
extern void smp_ctl_clear_bit(int cr, int bit);
#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)

#else

#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)

#endif /* CONFIG_SMP */

extern void (*_machine_restart)(char *command);
extern void (*_machine_halt)(void);
extern void (*_machine_power_off)(void);

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-s390/system.h
	3	*
	4	* S390 version
	5	* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
	6	* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
	7	*
	8	* Derived from "include/asm-i386/system.h"
	9	*/
	10
	11	#ifndef __ASM_SYSTEM_H
	12	#define __ASM_SYSTEM_H
	13
	14	#include <linux/config.h>
	15	#include <linux/kernel.h>
	16	#include <asm/types.h>
	17	#include <asm/ptrace.h>
	18	#include <asm/setup.h>
77fa2245	19	#include <asm/processor.h>
1da177e4 LT	20
	21	#ifdef __KERNEL__
	22
	23	struct task_struct;
	24
	25	extern struct task_struct __switch_to(void , void *);
	26
	27	#ifdef __s390x__
	28	#define __FLAG_SHIFT 56
	29	#else /* ! __s390x__ */
	30	#define __FLAG_SHIFT 24
	31	#endif /* ! __s390x__ */
	32
	33	static inline void save_fp_regs(s390_fp_regs *fpregs)
	34	{
	35	asm volatile (
	36	" std 0,8(%1)\n"
	37	" std 2,24(%1)\n"
	38	" std 4,40(%1)\n"
	39	" std 6,56(%1)"
	40	: "=m" (fpregs) : "a" (fpregs), "m" (fpregs) : "memory" );
	41	if (!MACHINE_HAS_IEEE)
	42	return;
	43	asm volatile(
	44	" stfpc 0(%1)\n"
	45	" std 1,16(%1)\n"
	46	" std 3,32(%1)\n"
	47	" std 5,48(%1)\n"
	48	" std 7,64(%1)\n"
	49	" std 8,72(%1)\n"
	50	" std 9,80(%1)\n"
	51	" std 10,88(%1)\n"
	52	" std 11,96(%1)\n"
	53	" std 12,104(%1)\n"
	54	" std 13,112(%1)\n"
	55	" std 14,120(%1)\n"
	56	" std 15,128(%1)\n"
	57	: "=m" (fpregs) : "a" (fpregs), "m" (fpregs) : "memory" );
	58	}
	59
	60	static inline void restore_fp_regs(s390_fp_regs *fpregs)
	61	{
	62	asm volatile (
	63	" ld 0,8(%0)\n"
	64	" ld 2,24(%0)\n"
	65	" ld 4,40(%0)\n"
	66	" ld 6,56(%0)"
	67	: : "a" (fpregs), "m" (*fpregs) );
	68	if (!MACHINE_HAS_IEEE)
	69	return;
	70	asm volatile(
	71	" lfpc 0(%0)\n"
	72	" ld 1,16(%0)\n"
	73	" ld 3,32(%0)\n"
	74	" ld 5,48(%0)\n"
	75	" ld 7,64(%0)\n"
	76	" ld 8,72(%0)\n"
	77	" ld 9,80(%0)\n"
	78	" ld 10,88(%0)\n"
	79	" ld 11,96(%0)\n"
	80	" ld 12,104(%0)\n"
	81	" ld 13,112(%0)\n"
	82	" ld 14,120(%0)\n"
	83	" ld 15,128(%0)\n"
84	: : "a" (fpregs), "m" (*fpregs) );
85	}
86
87	static inline void save_access_regs(unsigned int *acrs)
88	{
89	asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
90	}
91
92	static inline void restore_access_regs(unsigned int *acrs)
93	{
94	asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
95	}
96
97	#define switch_to(prev,next,last) do { \
98	if (prev == next) \
99	break; \
100	save_fp_regs(&prev->thread.fp_regs); \
101	restore_fp_regs(&next->thread.fp_regs); \
102	save_access_regs(&prev->thread.acrs[0]); \
103	restore_access_regs(&next->thread.acrs[0]); \
104	prev = __switch_to(prev,next); \
105	} while (0)
106
4dc7a0bb IM	107	/*
	108	* On SMP systems, when the scheduler does migration-cost autodetection,
	109	* it needs a way to flush as much of the CPU's caches as possible.
	110	*
	111	* TODO: fill this in!
	112	*/
	113	static inline void sched_cacheflush(void)
	114	{
	115	}
	116
1da177e4 LT	117	#ifdef CONFIG_VIRT_CPU_ACCOUNTING
	118	extern void account_user_vtime(struct task_struct *);
	119	extern void account_system_vtime(struct task_struct *);
4866cde0	120	#endif
1da177e4	121
5ee24d95	122	#define finish_arch_switch(prev) do { \
1da177e4	123	set_fs(current->thread.mm_segment); \
4866cde0	124	account_system_vtime(prev); \
1da177e4 LT	125	} while (0)
1da177e4 LT	126
1da177e4 LT	127	#define nop() __asm__ __volatile__ ("nop")
	128
	129	#define xchg(ptr,x) \
	130	((__typeof__((ptr)))__xchg((unsigned long)(x),(void )(ptr),sizeof(*(ptr))))
	131
	132	static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
	133	{
	134	unsigned long addr, old;
	135	int shift;
	136
	137	switch (size) {
	138	case 1:
	139	addr = (unsigned long) ptr;
	140	shift = (3 ^ (addr & 3)) << 3;
	141	addr ^= addr & 3;
	142	asm volatile(
	143	" l %0,0(%4)\n"
	144	"0: lr 0,%0\n"
	145	" nr 0,%3\n"
	146	" or 0,%2\n"
	147	" cs %0,0,0(%4)\n"
	148	" jl 0b\n"
	149	: "=&d" (old), "=m" ((int ) addr)
	150	: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
	151	"m" ((int ) addr) : "memory", "cc", "0" );
	152	x = old >> shift;
	153	break;
	154	case 2:
	155	addr = (unsigned long) ptr;
	156	shift = (2 ^ (addr & 2)) << 3;
	157	addr ^= addr & 2;
	158	asm volatile(
	159	" l %0,0(%4)\n"
	160	"0: lr 0,%0\n"
	161	" nr 0,%3\n"
	162	" or 0,%2\n"
	163	" cs %0,0,0(%4)\n"
	164	" jl 0b\n"
	165	: "=&d" (old), "=m" ((int ) addr)
	166	: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
	167	"m" ((int ) addr) : "memory", "cc", "0" );
	168	x = old >> shift;
	169	break;
	170	case 4:
	171	asm volatile (
	172	" l %0,0(%3)\n"
	173	"0: cs %0,%2,0(%3)\n"
	174	" jl 0b\n"
	175	: "=&d" (old), "=m" ((int ) ptr)
	176	: "d" (x), "a" (ptr), "m" ((int ) ptr)
	177	: "memory", "cc" );
	178	x = old;
	179	break;
	180	#ifdef __s390x__
	181	case 8:
	182	asm volatile (
	183	" lg %0,0(%3)\n"
	184	"0: csg %0,%2,0(%3)\n"
	185	" jl 0b\n"
	186	: "=&d" (old), "=m" ((long ) ptr)
	187	: "d" (x), "a" (ptr), "m" ((long ) ptr)
	188	: "memory", "cc" );
	189	x = old;
	190	break;
191	#endif /* __s390x__ */
192	}
193	return x;
194	}
195
196	/*
197	* Atomic compare and exchange. Compare OLD with MEM, if identical,
198	* store NEW in MEM. Return the initial value in MEM. Success is
199	* indicated by comparing RETURN with OLD.
200	*/
201
202	#define __HAVE_ARCH_CMPXCHG 1
203
204	#define cmpxchg(ptr,o,n)\
205	((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
206	(unsigned long)(n),sizeof(*(ptr))))
207
208	static inline unsigned long
209	__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
210	{
211	unsigned long addr, prev, tmp;
212	int shift;
213
214	switch (size) {
215	case 1:
216	addr = (unsigned long) ptr;
217	shift = (3 ^ (addr & 3)) << 3;
218	addr ^= addr & 3;
219	asm volatile(
220	" l %0,0(%4)\n"
221	"0: nr %0,%5\n"
222	" lr %1,%0\n"
223	" or %0,%2\n"
224	" or %1,%3\n"
225	" cs %0,%1,0(%4)\n"
226	" jnl 1f\n"
227	" xr %1,%0\n"
228	" nr %1,%5\n"
229	" jnz 0b\n"
230	"1:"
231	: "=&d" (prev), "=&d" (tmp)
232	: "d" (old << shift), "d" (new << shift), "a" (ptr),
233	"d" (~(255 << shift))
234	: "memory", "cc" );
235	return prev >> shift;
236	case 2:
237	addr = (unsigned long) ptr;
238	shift = (2 ^ (addr & 2)) << 3;
239	addr ^= addr & 2;
240	asm volatile(
241	" l %0,0(%4)\n"
242	"0: nr %0,%5\n"
243	" lr %1,%0\n"
244	" or %0,%2\n"
245	" or %1,%3\n"
246	" cs %0,%1,0(%4)\n"
247	" jnl 1f\n"
248	" xr %1,%0\n"
249	" nr %1,%5\n"
250	" jnz 0b\n"
251	"1:"
252	: "=&d" (prev), "=&d" (tmp)
253	: "d" (old << shift), "d" (new << shift), "a" (ptr),
254	"d" (~(65535 << shift))
255	: "memory", "cc" );
256	return prev >> shift;
257	case 4:
258	asm volatile (
259	" cs %0,%2,0(%3)\n"
260	: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
261	: "memory", "cc" );
262	return prev;
263	#ifdef __s390x__
264	case 8:
265	asm volatile (
266	" csg %0,%2,0(%3)\n"
267	: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
268	: "memory", "cc" );
269	return prev;
270	#endif /* __s390x__ */
271	}
272	return old;
273	}
274
275	/*
276	* Force strict CPU ordering.
277	* And yes, this is required on UP too when we're talking
278	* to devices.
279	*
280	* This is very similar to the ppc eieio/sync instruction in that is
281	* does a checkpoint syncronisation & makes sure that
282	* all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
283	*/
284
285	#define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
286	# define SYNC_OTHER_CORES(x) eieio()
287	#define mb() eieio()
288	#define rmb() eieio()
289	#define wmb() eieio()
290	#define read_barrier_depends() do { } while(0)
291	#define smp_mb() mb()
292	#define smp_rmb() rmb()
293	#define smp_wmb() wmb()
294	#define smp_read_barrier_depends() read_barrier_depends()
295	#define smp_mb__before_clear_bit() smp_mb()
296	#define smp_mb__after_clear_bit() smp_mb()
297
298
299	#define set_mb(var, value) do { var = value; mb(); } while (0)
300	#define set_wmb(var, value) do { var = value; wmb(); } while (0)
301
302	/* interrupt control.. */
303	#define local_irq_enable() ({ \
304	unsigned long __dummy; \
305	__asm__ __volatile__ ( \
306	"stosm 0(%1),0x03" \
307	: "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
308	})
309
310	#define local_irq_disable() ({ \
311	unsigned long __flags; \
312	__asm__ __volatile__ ( \
313	"stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
314	__flags; \
315	})
316
317	#define local_save_flags(x) \
318	__asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
319
320	#define local_irq_restore(x) \
321	__asm__ __volatile__("ssm 0(%0)" : : "a" (&x), "m" (x) : "memory")
322
323	#define irqs_disabled() \
324	({ \
325	unsigned long flags; \
326	local_save_flags(flags); \
327	!((flags >> __FLAG_SHIFT) & 3); \
328	})
329
330	#ifdef __s390x__
331
1da177e4 LT	332	#define __ctl_load(array, low, high) ({ \
	333	typedef struct { char _[sizeof(array)]; } addrtype; \
	334	__asm__ __volatile__ ( \
	335	" bras 1,0f\n" \
	336	" lctlg 0,0,0(%0)\n" \
	337	"0: ex %1,0(1)" \
	338	: : "a" (&array), "a" (((low)<<4)+(high)), \
	339	"m" ((addrtype )(array)) : "1" ); \
	340	})
	341
	342	#define __ctl_store(array, low, high) ({ \
	343	typedef struct { char _[sizeof(array)]; } addrtype; \
	344	__asm__ __volatile__ ( \
	345	" bras 1,0f\n" \
	346	" stctg 0,0,0(%1)\n" \
	347	"0: ex %2,0(1)" \
	348	: "=m" ((addrtype )(array)) \
	349	: "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
	350	})
	351
	352	#define __ctl_set_bit(cr, bit) ({ \
	353	__u8 __dummy[24]; \
	354	__asm__ __volatile__ ( \
	355	" bras 1,0f\n" /* skip indirect insns */ \
	356	" stctg 0,0,0(%1)\n" \
	357	" lctlg 0,0,0(%1)\n" \
	358	"0: ex %2,0(1)\n" /* execute stctl */ \
	359	" lg 0,0(%1)\n" \
	360	" ogr 0,%3\n" /* set the bit */ \
	361	" stg 0,0(%1)\n" \
	362	"1: ex %2,6(1)" /* execute lctl */ \
	363	: "=m" (__dummy) \
	364	: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
	365	"a" (cr*17), "a" (1L<<(bit)) \
	366	: "cc", "0", "1" ); \
	367	})
	368
	369	#define __ctl_clear_bit(cr, bit) ({ \
	370	__u8 __dummy[16]; \
	371	__asm__ __volatile__ ( \
	372	" bras 1,0f\n" /* skip indirect insns */ \
	373	" stctg 0,0,0(%1)\n" \
	374	" lctlg 0,0,0(%1)\n" \
	375	"0: ex %2,0(1)\n" /* execute stctl */ \
	376	" lg 0,0(%1)\n" \
	377	" ngr 0,%3\n" /* set the bit */ \
	378	" stg 0,0(%1)\n" \
	379	"1: ex %2,6(1)" /* execute lctl */ \
	380	: "=m" (__dummy) \
	381	: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
	382	"a" (cr*17), "a" (~(1L<<(bit))) \
	383	: "cc", "0", "1" ); \
	384	})
	385
	386	#else /* __s390x__ */
	387
1da177e4 LT	388	#define __ctl_load(array, low, high) ({ \
	389	typedef struct { char _[sizeof(array)]; } addrtype; \
	390	__asm__ __volatile__ ( \
	391	" bras 1,0f\n" \
	392	" lctl 0,0,0(%0)\n" \
	393	"0: ex %1,0(1)" \
	394	: : "a" (&array), "a" (((low)<<4)+(high)), \
	395	"m" ((addrtype )(array)) : "1" ); \
	396	})
	397
	398	#define __ctl_store(array, low, high) ({ \
	399	typedef struct { char _[sizeof(array)]; } addrtype; \
	400	__asm__ __volatile__ ( \
	401	" bras 1,0f\n" \
	402	" stctl 0,0,0(%1)\n" \
	403	"0: ex %2,0(1)" \
	404	: "=m" ((addrtype )(array)) \
	405	: "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
	406	})
	407
	408	#define __ctl_set_bit(cr, bit) ({ \
	409	__u8 __dummy[16]; \
	410	__asm__ __volatile__ ( \
	411	" bras 1,0f\n" /* skip indirect insns */ \
	412	" stctl 0,0,0(%1)\n" \
	413	" lctl 0,0,0(%1)\n" \
	414	"0: ex %2,0(1)\n" /* execute stctl */ \
	415	" l 0,0(%1)\n" \
	416	" or 0,%3\n" /* set the bit */ \
	417	" st 0,0(%1)\n" \
	418	"1: ex %2,4(1)" /* execute lctl */ \
	419	: "=m" (__dummy) \
	420	: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
	421	"a" (cr*17), "a" (1<<(bit)) \
	422	: "cc", "0", "1" ); \
	423	})
	424
	425	#define __ctl_clear_bit(cr, bit) ({ \
	426	__u8 __dummy[16]; \
	427	__asm__ __volatile__ ( \
	428	" bras 1,0f\n" /* skip indirect insns */ \
	429	" stctl 0,0,0(%1)\n" \
	430	" lctl 0,0,0(%1)\n" \
	431	"0: ex %2,0(1)\n" /* execute stctl */ \
	432	" l 0,0(%1)\n" \
	433	" nr 0,%3\n" /* set the bit */ \
	434	" st 0,0(%1)\n" \
	435	"1: ex %2,4(1)" /* execute lctl */ \
	436	: "=m" (__dummy) \
	437	: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
	438	"a" (cr*17), "a" (~(1<<(bit))) \
	439	: "cc", "0", "1" ); \
	440	})
	441	#endif /* __s390x__ */
	442
	443	/* For spinlocks etc */
	444	#define local_irq_save(x) ((x) = local_irq_disable())
	445
77fa2245 HC	446	/*
	447	* Use to set psw mask except for the first byte which
	448	* won't be changed by this function.
	449	*/
	450	static inline void
	451	__set_psw_mask(unsigned long mask)
	452	{
	453	local_save_flags(mask);
	454	__load_psw_mask(mask);
	455	}
	456
	457	#define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
	458	#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
	459
1da177e4 LT	460	#ifdef CONFIG_SMP
	461
	462	extern void smp_ctl_set_bit(int cr, int bit);
	463	extern void smp_ctl_clear_bit(int cr, int bit);
	464	#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
	465	#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
	466
	467	#else
	468
	469	#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
	470	#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
	471
	472	#endif /* CONFIG_SMP */
	473
	474	extern void (_machine_restart)(char command);
	475	extern void (*_machine_halt)(void);
	476	extern void (*_machine_power_off)(void);
	477
	478	#define arch_align_stack(x) (x)
	479
	480	#endif /* __KERNEL__ */
	481
	482	#endif
	483