[mirror_ubuntu-artful-kernel.git] / include / asm-sh / hw_irq.h

#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H

#include <linux/init.h>
#include <asm/atomic.h>

extern atomic_t irq_err_count;

struct ipr_data {
	unsigned char irq;
	unsigned char ipr_idx;		/* Index for the IPR registered */
	unsigned char shift;		/* Number of bits to shift the data */
	unsigned char priority;		/* The priority */
};

struct ipr_desc {
	unsigned long *ipr_offsets;
	unsigned int nr_offsets;
	struct ipr_data *ipr_data;
	unsigned int nr_irqs;
	struct irq_chip chip;
};

void register_ipr_controller(struct ipr_desc *);

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_prio {
	intc_enum enum_id;
	unsigned char priority;
};

#define INTC_PRIO(enum_id, prio) { enum_id, prio }

struct intc_group {
	intc_enum enum_id;
	intc_enum *enum_ids;
};

#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
};

struct intc_prio_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

struct intc_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_prio *priorities;
	unsigned int nr_priorities;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	struct irq_chip chip;
};

#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	priorities, mask_regs, prio_regs, sense_regs)			\
struct intc_desc symbol = {						\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
	_INTC_ARRAY(priorities),					\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
	_INTC_ARRAY(sense_regs),					\
	.chip.name = chipname,						\
}

void __init register_intc_controller(struct intc_desc *desc);

void __init plat_irq_setup(void);

enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
void __init plat_irq_setup_pins(int mode);

#endif /* __ASM_SH_HW_IRQ_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_HW_IRQ_H
	2	#define __ASM_SH_HW_IRQ_H
	3
02ab3f70	4	#include <linux/init.h>
35f3c518 PM	5	#include <asm/atomic.h>
	6
	7	extern atomic_t irq_err_count;
	8
68abdbbb MD	9	struct ipr_data {
	10	unsigned char irq;
	11	unsigned char ipr_idx; /* Index for the IPR registered */
	12	unsigned char shift; /* Number of bits to shift the data */
	13	unsigned char priority; /* The priority */
	14	};
	15
	16	struct ipr_desc {
	17	unsigned long *ipr_offsets;
	18	unsigned int nr_offsets;
	19	struct ipr_data *ipr_data;
	20	unsigned int nr_irqs;
	21	struct irq_chip chip;
	22	};
	23
	24	void register_ipr_controller(struct ipr_desc *);
68abdbbb	25
02ab3f70 MD	26	typedef unsigned char intc_enum;
	27
	28	struct intc_vect {
	29	intc_enum enum_id;
	30	unsigned short vect;
	31	};
	32
	33	#define INTC_VECT(enum_id, vect) { enum_id, vect }
51da6426	34	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
02ab3f70 MD	35
	36	struct intc_prio {
	37	intc_enum enum_id;
	38	unsigned char priority;
	39	};
	40
	41	#define INTC_PRIO(enum_id, prio) { enum_id, prio }
	42
	43	struct intc_group {
	44	intc_enum enum_id;
	45	intc_enum *enum_ids;
	46	};
	47
	48	#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
	49
	50	struct intc_mask_reg {
	51	unsigned long set_reg, clr_reg, reg_width;
	52	intc_enum enum_ids[32];
	53	};
	54
	55	struct intc_prio_reg {
	56	unsigned long reg, reg_width, field_width;
	57	intc_enum enum_ids[16];
	58	};
	59
	60	struct intc_sense_reg {
	61	unsigned long reg, reg_width, field_width;
	62	intc_enum enum_ids[16];
	63	};
	64
	65	struct intc_desc {
	66	struct intc_vect *vectors;
	67	unsigned int nr_vectors;
	68	struct intc_group *groups;
	69	unsigned int nr_groups;
	70	struct intc_prio *priorities;
	71	unsigned int nr_priorities;
	72	struct intc_mask_reg *mask_regs;
	73	unsigned int nr_mask_regs;
	74	struct intc_prio_reg *prio_regs;
	75	unsigned int nr_prio_regs;
	76	struct intc_sense_reg *sense_regs;
	77	unsigned int nr_sense_regs;
	78	struct irq_chip chip;
	79	};
	80
	81	#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
	82	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
	83	priorities, mask_regs, prio_regs, sense_regs) \
1b06428e	84	struct intc_desc symbol = { \
02ab3f70 MD	85	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	86	_INTC_ARRAY(priorities), \
	87	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	88	_INTC_ARRAY(sense_regs), \
	89	.chip.name = chipname, \
	90	}
	91
	92	void __init register_intc_controller(struct intc_desc *desc);
	93
90015c89 MD	94	void __init plat_irq_setup(void);
90015c89 MD	95
a0e23267 MD	96	enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
a0e23267 MD	97	IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
39c7aa9e MD	98	void __init plat_irq_setup_pins(int mode);
39c7aa9e MD	99
1da177e4	100	#endif /* __ASM_SH_HW_IRQ_H */