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1da177e4 1/*
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2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
4 *
1da177e4 5 * Copyright (C) 1999 Niibe Yutaka
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6 * Copyright (C) 2002 - 2005 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
1da177e4 11 */
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12#ifndef __ASM_SH_PGTABLE_H
13#define __ASM_SH_PGTABLE_H
1da177e4 14
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15#include <asm-generic/pgtable-nopmd.h>
16#include <asm/page.h>
17
1da177e4 18#ifndef __ASSEMBLY__
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19#include <asm/addrspace.h>
20#include <asm/fixmap.h>
1da177e4 21
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22/*
23 * ZERO_PAGE is a global shared page that is always zero: used
24 * for zero-mapped memory areas etc..
25 */
26ff6c11 26extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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27#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
28
29#endif /* !__ASSEMBLY__ */
30
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31/*
32 * traditional two-level paging structure
33 */
34/* PTE bits */
35#ifdef CONFIG_X2TLB
36# define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
37#else
38# define PTE_MAGNITUDE 2 /* 32-bit PTEs */
39#endif
40#define PTE_SHIFT PAGE_SHIFT
41#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
42
43/* PGD bits */
44#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
45#define PGDIR_BITS (32 - PGDIR_SHIFT)
9b3a53ab 46#define PGDIR_SIZE (1 << PGDIR_SHIFT)
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47#define PGDIR_MASK (~(PGDIR_SIZE-1))
48
21440cf0 49/* Entries per level */
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50#define PTRS_PER_PTE (PAGE_SIZE / 4)
51#define PTRS_PER_PGD (PAGE_SIZE / 4)
21440cf0 52
1da177e4 53#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
d455a369 54#define FIRST_USER_ADDRESS 0
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55
56#define PTE_PHYS_MASK 0x1ffff000
57
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58/*
59 * First 1MB map is used by fixed purpose.
510c72ad 60 * Currently only 4-entry (16kB) is used (see arch/sh/mm/cache.c)
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61 */
62#define VMALLOC_START (P3SEG+0x00100000)
63#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
64
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65/*
66 * Linux PTEL encoding.
67 *
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68 * Hardware and software bit definitions for the PTEL value (see below for
69 * notes on SH-X2 MMUs and 64-bit PTEs):
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70 *
71 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
72 *
73 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
74 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
75 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
76 *
77 * In order to keep this relatively clean, do not use these for defining
78 * SH-3 specific flags until all of the other unused bits have been
79 * exhausted.
80 *
81 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
82 *
83 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
84 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
85 *
86 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
87 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
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88 *
89 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
90 *
91 * SH-X2 MMUs and extended PTEs
92 *
93 * SH-X2 supports an extended mode TLB with split data arrays due to the
94 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
95 * SZ bit placeholders still exist in data array 1, but are implemented as
96 * reserved bits, with the real logic existing in data array 2.
97 *
98 * The downside to this is that we can no longer fit everything in to a 32-bit
99 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
100 * side, this gives us quite a few spare bits to play with for future usage.
ef48e8e3 101 */
21440cf0 102/* Legacy and compat mode bits */
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103#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
104#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
105#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
106#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
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107#ifndef CONFIG_X2TLB
108# define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
109# define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
110# define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
111# define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
112#endif
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113#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
114#define _PAGE_PROTNONE 0x200 /* software: if not present */
115#define _PAGE_ACCESSED 0x400 /* software: page referenced */
116#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
1da177e4 117
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118/* Extended mode bits */
119#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
120#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
121#define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
122#define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
123
124#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
125#define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
126#define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
127
128#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
129#define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
130#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
131
132/* Wrapper for extended mode pgprot twiddling */
133#ifdef CONFIG_X2TLB
134# define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
135#else
136# define _PAGE_EXT(x) (0)
137#endif
138
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139/* software: moves to PTEA.TC (Timing Control) */
140#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
141#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
142
143/* software: moves to PTEA.SA[2:0] (Space Attributes) */
144#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
145#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
146#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
147#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
148#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
149#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
150#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
151
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152/* Mask which drops unused bits from the PTEL value */
153#ifdef CONFIG_CPU_SH3
154#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
155 _PAGE_FILE | _PAGE_SZ1 | \
156 _PAGE_HW_SHARED)
1da177e4 157#else
ef48e8e3 158#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
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159#endif
160
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161#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
162
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163/* Hardware flags, page size encoding */
164#if defined(CONFIG_X2TLB)
165# if defined(CONFIG_PAGE_SIZE_4KB)
166# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
167# elif defined(CONFIG_PAGE_SIZE_8KB)
168# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
169# elif defined(CONFIG_PAGE_SIZE_64KB)
170# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
171# endif
172#else
173# if defined(CONFIG_PAGE_SIZE_4KB)
174# define _PAGE_FLAGS_HARD _PAGE_SZ0
175# elif defined(CONFIG_PAGE_SIZE_64KB)
176# define _PAGE_FLAGS_HARD _PAGE_SZ1
177# endif
178#endif
1da177e4 179
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180#if defined(CONFIG_X2TLB)
181# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
182# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
183# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
184# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
185# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
186# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
187# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
188# define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
189# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
190# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
191# endif
192#else
193# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
194# define _PAGE_SZHUGE (_PAGE_SZ1)
195# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
196# define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
197# endif
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198#endif
199
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200/*
201 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
202 * to make pte_mkhuge() happy.
203 */
204#ifndef _PAGE_SZHUGE
205# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
206#endif
207
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208#define _PAGE_CHG_MASK \
209 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
1da177e4 210
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211#ifndef __ASSEMBLY__
212
21440cf0 213#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
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214#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
215 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
216
217#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
218 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
219 _PAGE_EXT(_PAGE_EXT_USER_READ | \
99a596f9 220 _PAGE_EXT_USER_WRITE))
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221
222#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
223 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
224 _PAGE_EXT(_PAGE_EXT_USER_EXEC | \
99a596f9 225 _PAGE_EXT_USER_READ))
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226
227#define PAGE_COPY PAGE_EXECREAD
228
229#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
230 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
231 _PAGE_EXT(_PAGE_EXT_USER_READ))
232
233#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
234 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
235 _PAGE_EXT(_PAGE_EXT_USER_WRITE))
236
237#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
238 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
239 _PAGE_EXT(_PAGE_EXT_USER_WRITE | \
99a596f9 240 _PAGE_EXT_USER_READ | \
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241 _PAGE_EXT_USER_EXEC))
242
243#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
244 _PAGE_DIRTY | _PAGE_ACCESSED | \
245 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
246 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
99a596f9 247 _PAGE_EXT_KERN_WRITE | \
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248 _PAGE_EXT_KERN_EXEC))
249
250#define PAGE_KERNEL_NOCACHE \
251 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
252 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
253 _PAGE_FLAGS_HARD | \
254 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
99a596f9 255 _PAGE_EXT_KERN_WRITE | \
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256 _PAGE_EXT_KERN_EXEC))
257
258#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
259 _PAGE_DIRTY | _PAGE_ACCESSED | \
260 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
261 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
99a596f9 262 _PAGE_EXT_KERN_EXEC))
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263
264#define PAGE_KERNEL_PCC(slot, type) \
265 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
266 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
267 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
99a596f9 268 _PAGE_EXT_KERN_WRITE | \
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269 _PAGE_EXT_KERN_EXEC) \
270 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
271 (type))
272
273#elif defined(CONFIG_MMU) /* SH-X TLB */
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274#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
275 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
276
277#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
278 _PAGE_CACHABLE | _PAGE_ACCESSED | \
279 _PAGE_FLAGS_HARD)
280
281#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
282 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
283
284#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
285 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
286
287#define PAGE_EXECREAD PAGE_READONLY
288#define PAGE_RWX PAGE_SHARED
289#define PAGE_WRITEONLY PAGE_SHARED
290
291#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
292 _PAGE_DIRTY | _PAGE_ACCESSED | \
293 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
294
1da177e4 295#define PAGE_KERNEL_NOCACHE \
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296 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
297 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
298 _PAGE_FLAGS_HARD)
299
300#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
301 _PAGE_DIRTY | _PAGE_ACCESSED | \
302 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
303
1da177e4 304#define PAGE_KERNEL_PCC(slot, type) \
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305 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
306 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
307 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
308 (type))
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309#else /* no mmu */
310#define PAGE_NONE __pgprot(0)
311#define PAGE_SHARED __pgprot(0)
312#define PAGE_COPY __pgprot(0)
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313#define PAGE_EXECREAD __pgprot(0)
314#define PAGE_RWX __pgprot(0)
1da177e4 315#define PAGE_READONLY __pgprot(0)
21440cf0 316#define PAGE_WRITEONLY __pgprot(0)
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317#define PAGE_KERNEL __pgprot(0)
318#define PAGE_KERNEL_NOCACHE __pgprot(0)
319#define PAGE_KERNEL_RO __pgprot(0)
320#define PAGE_KERNEL_PCC __pgprot(0)
321#endif
322
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323#endif /* __ASSEMBLY__ */
324
1da177e4 325/*
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326 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
327 * protection for execute, and considers it the same as a read. Also, write
328 * permission implies read permission. This is the closest we can get..
329 *
330 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
331 * not only supporting separate execute, read, and write bits, but having
332 * completely separate permission bits for user and kernel space.
1da177e4 333 */
21440cf0 334 /*xwr*/
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335#define __P000 PAGE_NONE
336#define __P001 PAGE_READONLY
337#define __P010 PAGE_COPY
338#define __P011 PAGE_COPY
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339#define __P100 PAGE_EXECREAD
340#define __P101 PAGE_EXECREAD
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341#define __P110 PAGE_COPY
342#define __P111 PAGE_COPY
343
344#define __S000 PAGE_NONE
345#define __S001 PAGE_READONLY
21440cf0 346#define __S010 PAGE_WRITEONLY
1da177e4 347#define __S011 PAGE_SHARED
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348#define __S100 PAGE_EXECREAD
349#define __S101 PAGE_EXECREAD
350#define __S110 PAGE_RWX
351#define __S111 PAGE_RWX
1da177e4 352
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353#ifndef __ASSEMBLY__
354
355/*
356 * Certain architectures need to do special things when PTEs
357 * within a page table are directly modified. Thus, the following
358 * hook is made available.
359 */
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360#ifdef CONFIG_X2TLB
361static inline void set_pte(pte_t *ptep, pte_t pte)
362{
363 ptep->pte_high = pte.pte_high;
364 smp_wmb();
365 ptep->pte_low = pte.pte_low;
366}
367#else
26ff6c11 368#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
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369#endif
370
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371#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
372
373/*
374 * (pmds are folded into pgds so this doesn't get actually called,
375 * but the define is needed for a generic inline function.)
376 */
377#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
378
21440cf0 379#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
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380#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
381#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
382
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383#define pte_none(x) (!pte_val(x))
384#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
21440cf0 385#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
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386
387#define pmd_none(x) (!pmd_val(x))
99a596f9 388#define pmd_present(x) (pmd_val(x))
1da177e4 389#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
99a596f9 390#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
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391
392#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
26ff6c11 393#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
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394
395/*
396 * The following only work if pte_present() is true.
397 * Undefined behaviour if not..
398 */
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399#define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT))
400#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
401#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
402#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
403
404#ifdef CONFIG_X2TLB
405#define pte_read(pte) ((pte).pte_high & _PAGE_EXT_USER_READ)
406#define pte_exec(pte) ((pte).pte_high & _PAGE_EXT_USER_EXEC)
407#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
408#else
409#define pte_read(pte) (pte_val(pte) & _PAGE_USER)
410#define pte_exec(pte) (pte_val(pte) & _PAGE_USER)
411#define pte_write(pte) (pte_val(pte) & _PAGE_RW)
d229401f 412#endif
1da177e4 413
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414#define PTE_BIT_FUNC(h,fn,op) \
415static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
416
417#ifdef CONFIG_X2TLB
418/*
419 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
420 * individually toggled (and user permissions are entirely decoupled from
421 * kernel permissions), we attempt to couple them a bit more sanely here.
422 */
423PTE_BIT_FUNC(high, rdprotect, &= ~_PAGE_EXT_USER_READ);
424PTE_BIT_FUNC(high, mkread, |= _PAGE_EXT_USER_READ | _PAGE_EXT_KERN_READ);
425PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
426PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
427PTE_BIT_FUNC(high, exprotect, &= ~_PAGE_EXT_USER_EXEC);
428PTE_BIT_FUNC(high, mkexec, |= _PAGE_EXT_USER_EXEC | _PAGE_EXT_KERN_EXEC);
429PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
430#else
431PTE_BIT_FUNC(low, rdprotect, &= ~_PAGE_USER);
432PTE_BIT_FUNC(low, mkread, |= _PAGE_USER);
433PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
434PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
435PTE_BIT_FUNC(low, exprotect, &= ~_PAGE_USER);
436PTE_BIT_FUNC(low, mkexec, |= _PAGE_USER);
437PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
438#endif
439
440PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
441PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
442PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
443PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
444
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445/*
446 * Macro and implementation to make a page protection as uncachable.
447 */
448#define pgprot_noncached pgprot_noncached
449
450static inline pgprot_t pgprot_noncached(pgprot_t _prot)
451{
452 unsigned long prot = pgprot_val(_prot);
453
454 prot &= ~_PAGE_CACHABLE;
455 return __pgprot(prot);
456}
457
458#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
459
460/*
461 * Conversion functions: convert a page and protection to a page entry,
462 * and a page entry and page directory to the page they refer to.
463 *
464 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
465 */
466#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
467
468static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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469{
470 set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
471 pgprot_val(newprot)));
472 return pte;
473}
1da177e4 474
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475#define pmd_page_vaddr(pmd) pmd_val(pmd)
476#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
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477
478/* to find an entry in a page-table-directory. */
479#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
480#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
481
482/* to find an entry in a kernel page-table-directory */
483#define pgd_offset_k(address) pgd_offset(&init_mm, address)
484
485/* Find an entry in the third-level page table.. */
486#define pte_index(address) \
487 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
488#define pte_offset_kernel(dir, address) \
46a82b2d 489 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
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490#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
491#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
492#define pte_unmap(pte) do { } while (0)
493#define pte_unmap_nested(pte) do { } while (0)
494
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495#ifdef CONFIG_X2TLB
496#define pte_ERROR(e) \
497 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
498 &(e), (e).pte_high, (e).pte_low)
499#else
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500#define pte_ERROR(e) \
501 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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502#endif
503
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504#define pgd_ERROR(e) \
505 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
506
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507struct vm_area_struct;
508extern void update_mmu_cache(struct vm_area_struct * vma,
509 unsigned long address, pte_t pte);
510
1da177e4 511/*
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512 * Encode and de-code a swap entry
513 *
514 * Constraints:
515 * _PAGE_FILE at bit 0
516 * _PAGE_PRESENT at bit 8
517 * _PAGE_PROTNONE at bit 9
518 *
519 * For the normal case, we encode the swap type into bits 0:7 and the
520 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
521 * preserved bits in the low 32-bits and use the upper 32 as the swap
522 * offset (along with a 5-bit type), following the same approach as x86
523 * PAE. This keeps the logic quite simple, and allows for a full 32
524 * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
525 * in the pte_low case.
526 *
527 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
528 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
529 * much cleaner..
530 *
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531 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
532 * and _PAGE_PROTNONE bits
533 */
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534#ifdef CONFIG_X2TLB
535#define __swp_type(x) ((x).val & 0x1f)
536#define __swp_offset(x) ((x).val >> 5)
537#define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
538#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
539#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
540
541/*
542 * Encode and decode a nonlinear file mapping entry
543 */
544#define pte_to_pgoff(pte) ((pte).pte_high)
545#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
546
547#define PTE_FILE_MAX_BITS 32
548#else
549#define __swp_type(x) ((x).val & 0xff)
550#define __swp_offset(x) ((x).val >> 10)
b6250e37 551#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
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552
553#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
554#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
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555
556/*
557 * Encode and decode a nonlinear file mapping entry
558 */
559#define PTE_FILE_MAX_BITS 29
560#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
561#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
b9b382da 562#endif
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563
564typedef pte_t *pte_addr_t;
565
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566#define kern_addr_valid(addr) (1)
567
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568#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
569 remap_pfn_range(vma, vaddr, pfn, size, prot)
570
571#define MK_IOSPACE_PFN(space, pfn) (pfn)
572#define GET_IOSPACE(pfn) 0
573#define GET_PFN(pfn) (pfn)
574
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575struct mm_struct;
576
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577/*
578 * No page table caches to initialise
579 */
580#define pgtable_cache_init() do { } while (0)
581
582#ifndef CONFIG_MMU
583extern unsigned int kobjsize(const void *objp);
584#endif /* !CONFIG_MMU */
585
586#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
587#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
588extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
589#endif
590
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591extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
592extern void paging_init(void);
593
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594#include <asm-generic/pgtable.h>
595
26ff6c11 596#endif /* !__ASSEMBLY__ */
1da177e4 597#endif /* __ASM_SH_PAGE_H */