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1da177e4 LT |
1 | #ifndef __SPARC64_SYSTEM_H |
2 | #define __SPARC64_SYSTEM_H | |
3 | ||
1da177e4 LT |
4 | #include <asm/ptrace.h> |
5 | #include <asm/processor.h> | |
6 | #include <asm/visasm.h> | |
7 | ||
8 | #ifndef __ASSEMBLY__ | |
10e26723 DM |
9 | |
10 | #include <linux/irqflags.h> | |
80af4eeb | 11 | #include <asm-generic/cmpxchg-local.h> |
10e26723 | 12 | |
1da177e4 LT |
13 | /* |
14 | * Sparc (general) CPU types | |
15 | */ | |
16 | enum sparc_cpu { | |
17 | sun4 = 0x00, | |
18 | sun4c = 0x01, | |
19 | sun4m = 0x02, | |
20 | sun4d = 0x03, | |
21 | sun4e = 0x04, | |
22 | sun4u = 0x05, /* V8 ploos ploos */ | |
23 | sun_unknown = 0x06, | |
24 | ap1000 = 0x07, /* almost a sun4m */ | |
25 | }; | |
26 | ||
27 | #define sparc_cpu_model sun4u | |
28 | ||
29 | /* This cannot ever be a sun4c nor sun4 :) That's just history. */ | |
30 | #define ARCH_SUN4C_SUN4 0 | |
31 | #define ARCH_SUN4 0 | |
32 | ||
7729d74e DM |
33 | extern char reboot_command[]; |
34 | ||
4d803fcd DM |
35 | /* These are here in an effort to more fully work around Spitfire Errata |
36 | * #51. Essentially, if a memory barrier occurs soon after a mispredicted | |
37 | * branch, the chip can stop executing instructions until a trap occurs. | |
38 | * Therefore, if interrupts are disabled, the chip can hang forever. | |
39 | * | |
40 | * It used to be believed that the memory barrier had to be right in the | |
41 | * delay slot, but a case has been traced recently wherein the memory barrier | |
42 | * was one instruction after the branch delay slot and the chip still hung. | |
43 | * The offending sequence was the following in sym_wakeup_done() of the | |
44 | * sym53c8xx_2 driver: | |
45 | * | |
46 | * call sym_ccb_from_dsa, 0 | |
47 | * movge %icc, 0, %l0 | |
48 | * brz,pn %o0, .LL1303 | |
49 | * mov %o0, %l2 | |
50 | * membar #LoadLoad | |
51 | * | |
52 | * The branch has to be mispredicted for the bug to occur. Therefore, we put | |
53 | * the memory barrier explicitly into a "branch always, predicted taken" | |
54 | * delay slot to avoid the problem case. | |
55 | */ | |
56 | #define membar_safe(type) \ | |
57 | do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ | |
58 | " membar " type "\n" \ | |
59 | "1:\n" \ | |
60 | : : : "memory"); \ | |
61 | } while (0) | |
62 | ||
63 | #define mb() \ | |
64 | membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad") | |
65 | #define rmb() \ | |
66 | membar_safe("#LoadLoad") | |
67 | #define wmb() \ | |
68 | membar_safe("#StoreStore") | |
69 | #define membar_storeload() \ | |
70 | membar_safe("#StoreLoad") | |
71 | #define membar_storeload_storestore() \ | |
72 | membar_safe("#StoreLoad | #StoreStore") | |
73 | #define membar_storeload_loadload() \ | |
74 | membar_safe("#StoreLoad | #LoadLoad") | |
75 | #define membar_storestore_loadstore() \ | |
76 | membar_safe("#StoreStore | #LoadStore") | |
4f07118f | 77 | |
1da177e4 LT |
78 | #endif |
79 | ||
1da177e4 LT |
80 | #define nop() __asm__ __volatile__ ("nop") |
81 | ||
1da177e4 LT |
82 | #define read_barrier_depends() do { } while(0) |
83 | #define set_mb(__var, __value) \ | |
4f07118f | 84 | do { __var = __value; membar_storeload_storestore(); } while(0) |
1da177e4 LT |
85 | |
86 | #ifdef CONFIG_SMP | |
87 | #define smp_mb() mb() | |
88 | #define smp_rmb() rmb() | |
89 | #define smp_wmb() wmb() | |
90 | #define smp_read_barrier_depends() read_barrier_depends() | |
91 | #else | |
92 | #define smp_mb() __asm__ __volatile__("":::"memory") | |
93 | #define smp_rmb() __asm__ __volatile__("":::"memory") | |
94 | #define smp_wmb() __asm__ __volatile__("":::"memory") | |
95 | #define smp_read_barrier_depends() do { } while(0) | |
96 | #endif | |
97 | ||
98 | #define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory") | |
99 | ||
100 | #define flushw_all() __asm__ __volatile__("flushw") | |
101 | ||
102 | /* Performance counter register access. */ | |
103 | #define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p)) | |
104 | #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p)) | |
105 | #define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p)) | |
106 | ||
107 | /* Blackbird errata workaround. See commentary in | |
108 | * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt() | |
109 | * for more information. | |
110 | */ | |
111 | #define reset_pic() \ | |
112 | __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \ | |
113 | ".align 64\n" \ | |
114 | "99:wr %g0, 0x0, %pic\n\t" \ | |
115 | "rd %pic, %g0") | |
116 | ||
117 | #ifndef __ASSEMBLY__ | |
118 | ||
119 | extern void sun_do_break(void); | |
1da177e4 LT |
120 | extern int stop_a_enabled; |
121 | ||
6ca94a13 | 122 | extern void fault_in_user_windows(void); |
1da177e4 LT |
123 | extern void synchronize_user_stack(void); |
124 | ||
125 | extern void __flushw_user(void); | |
126 | #define flushw_user() __flushw_user() | |
127 | ||
128 | #define flush_user_windows flushw_user | |
129 | #define flush_register_windows flushw_all | |
130 | ||
4866cde0 NP |
131 | /* Don't hold the runqueue lock over context switch */ |
132 | #define __ARCH_WANT_UNLOCKED_CTXSW | |
133 | #define prepare_arch_switch(next) \ | |
134 | do { \ | |
1da177e4 LT |
135 | flushw_all(); \ |
136 | } while (0) | |
137 | ||
1da177e4 LT |
138 | /* See what happens when you design the chip correctly? |
139 | * | |
140 | * We tell gcc we clobber all non-fixed-usage registers except | |
141 | * for l0/l1. It will use one for 'next' and the other to hold | |
142 | * the output value of 'last'. 'next' is not referenced again | |
143 | * past the invocation of switch_to in the scheduler, so we need | |
144 | * not preserve it's value. Hairy, but it lets us remove 2 loads | |
145 | * and 2 stores in this critical code path. -DaveM | |
146 | */ | |
1da177e4 LT |
147 | #define switch_to(prev, next, last) \ |
148 | do { if (test_thread_flag(TIF_PERFCTR)) { \ | |
149 | unsigned long __tmp; \ | |
150 | read_pcr(__tmp); \ | |
151 | current_thread_info()->pcr_reg = __tmp; \ | |
152 | read_pic(__tmp); \ | |
153 | current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\ | |
154 | current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \ | |
155 | } \ | |
156 | flush_tlb_pending(); \ | |
157 | save_and_clear_fpu(); \ | |
158 | /* If you are tempted to conditionalize the following */ \ | |
159 | /* so that ASI is only written if it changes, think again. */ \ | |
160 | __asm__ __volatile__("wr %%g0, %0, %%asi" \ | |
f3169641 | 161 | : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\ |
56fb4df6 DM |
162 | trap_block[current_thread_info()->cpu].thread = \ |
163 | task_thread_info(next); \ | |
1da177e4 LT |
164 | __asm__ __volatile__( \ |
165 | "mov %%g4, %%g7\n\t" \ | |
1da177e4 LT |
166 | "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \ |
167 | "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ | |
168 | "rdpr %%wstate, %%o5\n\t" \ | |
195f7fd0 | 169 | "stx %%o6, [%%g6 + %6]\n\t" \ |
1da177e4 | 170 | "stb %%o5, [%%g6 + %5]\n\t" \ |
195f7fd0 DM |
171 | "rdpr %%cwp, %%o5\n\t" \ |
172 | "stb %%o5, [%%g6 + %8]\n\t" \ | |
173 | "mov %4, %%g6\n\t" \ | |
174 | "ldub [%4 + %8], %%g1\n\t" \ | |
1da177e4 | 175 | "wrpr %%g1, %%cwp\n\t" \ |
195f7fd0 DM |
176 | "ldx [%%g6 + %6], %%o6\n\t" \ |
177 | "ldub [%%g6 + %5], %%o5\n\t" \ | |
178 | "ldub [%%g6 + %7], %%o7\n\t" \ | |
1da177e4 LT |
179 | "wrpr %%o5, 0x0, %%wstate\n\t" \ |
180 | "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ | |
181 | "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ | |
195f7fd0 | 182 | "ldx [%%g6 + %9], %%g4\n\t" \ |
db7d9a4e | 183 | "brz,pt %%o7, 1f\n\t" \ |
1da177e4 | 184 | " mov %%g7, %0\n\t" \ |
52eb053b DM |
185 | "sethi %%hi(ret_from_syscall), %%g1\n\t" \ |
186 | "jmpl %%g1 + %%lo(ret_from_syscall), %%g0\n\t" \ | |
187 | " nop\n\t" \ | |
1da177e4 | 188 | "1:\n\t" \ |
195f7fd0 DM |
189 | : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \ |
190 | "=r" (__local_per_cpu_offset) \ | |
f3169641 | 191 | : "0" (task_thread_info(next)), \ |
db7d9a4e DM |
192 | "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \ |
193 | "i" (TI_CWP), "i" (TI_TASK) \ | |
1da177e4 LT |
194 | : "cc", \ |
195 | "g1", "g2", "g3", "g7", \ | |
195f7fd0 | 196 | "l1", "l2", "l3", "l4", "l5", "l6", "l7", \ |
1da177e4 | 197 | "i0", "i1", "i2", "i3", "i4", "i5", \ |
195f7fd0 | 198 | "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \ |
1da177e4 LT |
199 | /* If you fuck with this, update ret_from_syscall code too. */ \ |
200 | if (test_thread_flag(TIF_PERFCTR)) { \ | |
201 | write_pcr(current_thread_info()->pcr_reg); \ | |
202 | reset_pic(); \ | |
203 | } \ | |
204 | } while(0) | |
205 | ||
206 | static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) | |
207 | { | |
208 | unsigned long tmp1, tmp2; | |
209 | ||
210 | __asm__ __volatile__( | |
211 | " membar #StoreLoad | #LoadLoad\n" | |
212 | " mov %0, %1\n" | |
213 | "1: lduw [%4], %2\n" | |
214 | " cas [%4], %2, %0\n" | |
215 | " cmp %2, %0\n" | |
216 | " bne,a,pn %%icc, 1b\n" | |
217 | " mov %1, %0\n" | |
218 | " membar #StoreLoad | #StoreStore\n" | |
219 | : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) | |
220 | : "0" (val), "r" (m) | |
221 | : "cc", "memory"); | |
222 | return val; | |
223 | } | |
224 | ||
225 | static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) | |
226 | { | |
227 | unsigned long tmp1, tmp2; | |
228 | ||
229 | __asm__ __volatile__( | |
230 | " membar #StoreLoad | #LoadLoad\n" | |
231 | " mov %0, %1\n" | |
232 | "1: ldx [%4], %2\n" | |
233 | " casx [%4], %2, %0\n" | |
234 | " cmp %2, %0\n" | |
235 | " bne,a,pn %%xcc, 1b\n" | |
236 | " mov %1, %0\n" | |
237 | " membar #StoreLoad | #StoreStore\n" | |
238 | : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) | |
239 | : "0" (val), "r" (m) | |
240 | : "cc", "memory"); | |
241 | return val; | |
242 | } | |
243 | ||
244 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
1da177e4 LT |
245 | |
246 | extern void __xchg_called_with_bad_pointer(void); | |
247 | ||
d979f179 | 248 | static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, |
1da177e4 LT |
249 | int size) |
250 | { | |
251 | switch (size) { | |
252 | case 4: | |
253 | return xchg32(ptr, x); | |
254 | case 8: | |
255 | return xchg64(ptr, x); | |
256 | }; | |
257 | __xchg_called_with_bad_pointer(); | |
258 | return x; | |
259 | } | |
260 | ||
261 | extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn)); | |
262 | ||
263 | /* | |
264 | * Atomic compare and exchange. Compare OLD with MEM, if identical, | |
265 | * store NEW in MEM. Return the initial value in MEM. Success is | |
266 | * indicated by comparing RETURN with OLD. | |
267 | */ | |
268 | ||
269 | #define __HAVE_ARCH_CMPXCHG 1 | |
270 | ||
d979f179 | 271 | static inline unsigned long |
1da177e4 LT |
272 | __cmpxchg_u32(volatile int *m, int old, int new) |
273 | { | |
274 | __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n" | |
275 | "cas [%2], %3, %0\n\t" | |
276 | "membar #StoreLoad | #StoreStore" | |
277 | : "=&r" (new) | |
278 | : "0" (new), "r" (m), "r" (old) | |
279 | : "memory"); | |
280 | ||
281 | return new; | |
282 | } | |
283 | ||
d979f179 | 284 | static inline unsigned long |
1da177e4 LT |
285 | __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new) |
286 | { | |
287 | __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n" | |
288 | "casx [%2], %3, %0\n\t" | |
289 | "membar #StoreLoad | #StoreStore" | |
290 | : "=&r" (new) | |
291 | : "0" (new), "r" (m), "r" (old) | |
292 | : "memory"); | |
293 | ||
294 | return new; | |
295 | } | |
296 | ||
297 | /* This function doesn't exist, so you'll get a linker error | |
298 | if something tries to do an invalid cmpxchg(). */ | |
299 | extern void __cmpxchg_called_with_bad_pointer(void); | |
300 | ||
d979f179 | 301 | static inline unsigned long |
1da177e4 LT |
302 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) |
303 | { | |
304 | switch (size) { | |
305 | case 4: | |
306 | return __cmpxchg_u32(ptr, old, new); | |
307 | case 8: | |
308 | return __cmpxchg_u64(ptr, old, new); | |
309 | } | |
310 | __cmpxchg_called_with_bad_pointer(); | |
311 | return old; | |
312 | } | |
313 | ||
314 | #define cmpxchg(ptr,o,n) \ | |
315 | ({ \ | |
316 | __typeof__(*(ptr)) _o_ = (o); \ | |
317 | __typeof__(*(ptr)) _n_ = (n); \ | |
318 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
319 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
320 | }) | |
321 | ||
80af4eeb MD |
322 | /* |
323 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | |
324 | * them available. | |
325 | */ | |
326 | ||
327 | static inline unsigned long __cmpxchg_local(volatile void *ptr, | |
328 | unsigned long old, | |
329 | unsigned long new, int size) | |
330 | { | |
331 | switch (size) { | |
332 | case 4: | |
333 | case 8: return __cmpxchg(ptr, old, new, size); | |
334 | default: | |
335 | return __cmpxchg_local_generic(ptr, old, new, size); | |
336 | } | |
337 | ||
338 | return old; | |
339 | } | |
340 | ||
341 | #define cmpxchg_local(ptr, o, n) \ | |
342 | ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ | |
343 | (unsigned long)(n), sizeof(*(ptr)))) | |
344 | #define cmpxchg64_local(ptr, o, n) \ | |
345 | ({ \ | |
346 | BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ | |
347 | cmpxchg_local((ptr), (o), (n)); \ | |
348 | }) | |
349 | ||
1da177e4 LT |
350 | #endif /* !(__ASSEMBLY__) */ |
351 | ||
352 | #define arch_align_stack(x) (x) | |
353 | ||
354 | #endif /* !(__SPARC64_SYSTEM_H) */ |