]>
Commit | Line | Data |
---|---|---|
67c5fc5c TG |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
3 | ||
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
6 | #include <asm/fixmap.h> | |
7 | #include <asm/apicdef.h> | |
8 | #include <asm/processor.h> | |
9 | #include <asm/system.h> | |
10 | ||
11 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
12 | ||
13 | #define Dprintk(x...) | |
14 | ||
15 | /* | |
16 | * Debugging macros | |
17 | */ | |
18 | #define APIC_QUIET 0 | |
19 | #define APIC_VERBOSE 1 | |
20 | #define APIC_DEBUG 2 | |
21 | ||
22 | /* | |
23 | * Define the default level of output to be very little | |
24 | * This can be turned up by using apic=verbose for more | |
25 | * information and apic=debug for _lots_ of information. | |
26 | * apic_verbosity is defined in apic.c | |
27 | */ | |
28 | #define apic_printk(v, s, a...) do { \ | |
29 | if ((v) <= apic_verbosity) \ | |
30 | printk(s, ##a); \ | |
31 | } while (0) | |
32 | ||
33 | ||
34 | extern void generic_apic_probe(void); | |
35 | ||
36 | #ifdef CONFIG_X86_LOCAL_APIC | |
37 | ||
38 | extern int apic_verbosity; | |
39 | extern int timer_over_8254; | |
40 | extern int local_apic_timer_c2_ok; | |
67c5fc5c | 41 | |
67c5fc5c | 42 | extern int ioapic_force; |
ae9d983b | 43 | extern int disable_apic; |
67c5fc5c TG |
44 | |
45 | /* | |
46 | * Basic functions accessing APICs. | |
47 | */ | |
48 | #ifdef CONFIG_PARAVIRT | |
49 | #include <asm/paravirt.h> | |
96a388de | 50 | #else |
67c5fc5c TG |
51 | #define apic_write native_apic_write |
52 | #define apic_write_atomic native_apic_write_atomic | |
53 | #define apic_read native_apic_read | |
54 | #define setup_boot_clock setup_boot_APIC_clock | |
55 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 56 | #endif |
67c5fc5c | 57 | |
aa7d8e25 RT |
58 | extern int is_vsmp_box(void); |
59 | ||
341d8854 | 60 | static inline void native_apic_write(unsigned long reg, u32 v) |
67c5fc5c TG |
61 | { |
62 | *((volatile u32 *)(APIC_BASE + reg)) = v; | |
63 | } | |
64 | ||
341d8854 | 65 | static inline void native_apic_write_atomic(unsigned long reg, u32 v) |
67c5fc5c | 66 | { |
3c311feb | 67 | (void)xchg((u32 *)(APIC_BASE + reg), v); |
67c5fc5c TG |
68 | } |
69 | ||
341d8854 | 70 | static inline u32 native_apic_read(unsigned long reg) |
67c5fc5c TG |
71 | { |
72 | return *((volatile u32 *)(APIC_BASE + reg)); | |
73 | } | |
74 | ||
75 | extern void apic_wait_icr_idle(void); | |
76 | extern u32 safe_apic_wait_icr_idle(void); | |
77 | extern int get_physical_broadcast(void); | |
78 | ||
79 | #ifdef CONFIG_X86_GOOD_APIC | |
80 | # define FORCE_READ_AROUND_WRITE 0 | |
81 | # define apic_read_around(x) | |
82 | # define apic_write_around(x, y) apic_write((x), (y)) | |
83 | #else | |
84 | # define FORCE_READ_AROUND_WRITE 1 | |
85 | # define apic_read_around(x) apic_read(x) | |
86 | # define apic_write_around(x, y) apic_write_atomic((x), (y)) | |
87 | #endif | |
88 | ||
89 | static inline void ack_APIC_irq(void) | |
90 | { | |
91 | /* | |
92 | * ack_APIC_irq() actually gets compiled as a single instruction: | |
93 | * - a single rmw on Pentium/82489DX | |
94 | * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC) | |
95 | * ... yummie. | |
96 | */ | |
97 | ||
98 | /* Docs say use 0 for future compatibility */ | |
99 | apic_write_around(APIC_EOI, 0); | |
100 | } | |
101 | ||
102 | extern int lapic_get_maxlvt(void); | |
103 | extern void clear_local_APIC(void); | |
104 | extern void connect_bsp_APIC(void); | |
105 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
106 | extern void disable_local_APIC(void); | |
107 | extern void lapic_shutdown(void); | |
108 | extern int verify_local_APIC(void); | |
109 | extern void cache_APIC_registers(void); | |
110 | extern void sync_Arb_IDs(void); | |
111 | extern void init_bsp_APIC(void); | |
112 | extern void setup_local_APIC(void); | |
739f33b3 | 113 | extern void end_local_APIC_setup(void); |
67c5fc5c | 114 | extern void init_apic_mappings(void); |
67c5fc5c TG |
115 | extern void setup_boot_APIC_clock(void); |
116 | extern void setup_secondary_APIC_clock(void); | |
117 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 118 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
119 | |
120 | /* | |
121 | * On 32bit this is mach-xxx local | |
122 | */ | |
123 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 124 | extern void early_init_lapic_mapping(void); |
67c5fc5c TG |
125 | #endif |
126 | ||
7b83dae7 RR |
127 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
128 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c TG |
129 | |
130 | extern int apic_is_clustered_box(void); | |
131 | ||
132 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
133 | static inline void lapic_shutdown(void) { } | |
134 | #define local_apic_timer_c2_ok 1 | |
135 | ||
136 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
137 | ||
138 | #endif /* __ASM_APIC_H */ |