[mirror_ubuntu-bionic-kernel.git] / include / asm-x86 / dma.h

/*
 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
 * Written by Hennus Bergman, 1992.
 * High DMA channel support & info by Hannu Savolainen
 * and John Boyd, Nov. 1992.
 */

#ifndef _ASM_X86_DMA_H
#define _ASM_X86_DMA_H

#include <linux/spinlock.h>	/* And spinlocks */
#include <asm/io.h>		/* need byte IO */
#include <linux/delay.h>


#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb	outb_p
#else
#define dma_outb	outb
#endif

#define dma_inb		inb

/*
 * NOTES about DMA transfers:
 *
 *  controller 1: channels 0-3, byte operations, ports 00-1F
 *  controller 2: channels 4-7, word operations, ports C0-DF
 *
 *  - ALL registers are 8 bits only, regardless of transfer size
 *  - channel 4 is not used - cascades 1 into 2.
 *  - channels 0-3 are byte - addresses/counts are for physical bytes
 *  - channels 5-7 are word - addresses/counts are for physical words
 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
 *  - transfer count loaded to registers is 1 less than actual count
 *  - controller 2 offsets are all even (2x offsets for controller 1)
 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
 *  - page registers for 0-3 use bit 0, represent 64K pages
 *
 * DMA transfers are limited to the lower 16MB of _physical_ memory.
 * Note that addresses loaded into registers must be _physical_ addresses,
 * not logical addresses (which may differ if paging is active).
 *
 *  Address mapping for channels 0-3:
 *
 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
 *    |  ...  |   |  ... |   |  ... |
 *    |  ...  |   |  ... |   |  ... |
 *    |  ...  |   |  ... |   |  ... |
 *   P7  ...  P0  A7 ... A0  A7 ... A0
 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
 *
 *  Address mapping for channels 5-7:
 *
 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
 *    |  ...  |   \   \   ... \  \  \  ... \  \
 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
 *    |  ...  |     \   \   ... \  \  \  ... \
 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
 *
 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
 * the hardware level, so odd-byte transfers aren't possible).
 *
 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
 *
 */

#define MAX_DMA_CHANNELS	8

#ifdef CONFIG_X86_32

/* The maximum address that we can perform a DMA transfer to on this platform */
#define MAX_DMA_ADDRESS      (PAGE_OFFSET+0x1000000)

#else

/* 16MB ISA DMA zone */
#define MAX_DMA_PFN   ((16*1024*1024) >> PAGE_SHIFT)

/* 4GB broken PCI/AGP hardware bus master zone */
#define MAX_DMA32_PFN ((4UL*1024*1024*1024) >> PAGE_SHIFT)

/* Compat define for old dma zone */
#define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))

#endif

/* 8237 DMA controllers */
#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */

/* DMA controller registers */
#define DMA1_CMD_REG		0x08	/* command register (w) */
#define DMA1_STAT_REG		0x08	/* status register (r) */
#define DMA1_REQ_REG		0x09    /* request register (w) */
#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
#define DMA1_MODE_REG		0x0B	/* mode register (w) */
#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG		0x0D    /* Temporary Register (r) */
#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */

#define DMA2_CMD_REG		0xD0	/* command register (w) */
#define DMA2_STAT_REG		0xD0	/* status register (r) */
#define DMA2_REQ_REG		0xD2    /* request register (w) */
#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
#define DMA2_MODE_REG		0xD6	/* mode register (w) */
#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG		0xDA    /* Temporary Register (r) */
#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */

#define DMA_ADDR_0		0x00    /* DMA address registers */
#define DMA_ADDR_1		0x02
#define DMA_ADDR_2		0x04
#define DMA_ADDR_3		0x06
#define DMA_ADDR_4		0xC0
#define DMA_ADDR_5		0xC4
#define DMA_ADDR_6		0xC8
#define DMA_ADDR_7		0xCC

#define DMA_CNT_0		0x01    /* DMA count registers */
#define DMA_CNT_1		0x03
#define DMA_CNT_2		0x05
#define DMA_CNT_3		0x07
#define DMA_CNT_4		0xC2
#define DMA_CNT_5		0xC6
#define DMA_CNT_6		0xCA
#define DMA_CNT_7		0xCE

#define DMA_PAGE_0		0x87    /* DMA page registers */
#define DMA_PAGE_1		0x83
#define DMA_PAGE_2		0x81
#define DMA_PAGE_3		0x82
#define DMA_PAGE_5		0x8B
#define DMA_PAGE_6		0x89
#define DMA_PAGE_7		0x8A

/* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_READ		0x44
/* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_WRITE		0x48
/* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_MODE_CASCADE	0xC0

#define DMA_AUTOINIT		0x10


extern spinlock_t  dma_spin_lock;

static __inline__ unsigned long claim_dma_lock(void)
{
	unsigned long flags;
	spin_lock_irqsave(&dma_spin_lock, flags);
	return flags;
}

static __inline__ void release_dma_lock(unsigned long flags)
{
	spin_unlock_irqrestore(&dma_spin_lock, flags);
}

/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(dmanr, DMA1_MASK_REG);
	else
		dma_outb(dmanr & 3, DMA2_MASK_REG);
}

static __inline__ void disable_dma(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(dmanr | 4, DMA1_MASK_REG);
	else
		dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}

/* Clear the 'DMA Pointer Flip Flop'.
 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 * Use this once to initialize the FF to a known state.
 * After that, keep track of it. :-)
 * --- In order to do that, the DMA routines below should ---
 * --- only be used while holding the DMA lock ! ---
 */
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(0, DMA1_CLEAR_FF_REG);
	else
		dma_outb(0, DMA2_CLEAR_FF_REG);
}

/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
	if (dmanr <= 3)
		dma_outb(mode | dmanr, DMA1_MODE_REG);
	else
		dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
}

/* Set only the page register bits of the transfer address.
 * This is used for successive transfers when we know the contents of
 * the lower 16 bits of the DMA current address register, but a 64k boundary
 * may have been crossed.
 */
static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
{
	switch (dmanr) {
	case 0:
		dma_outb(pagenr, DMA_PAGE_0);
		break;
	case 1:
		dma_outb(pagenr, DMA_PAGE_1);
		break;
	case 2:
		dma_outb(pagenr, DMA_PAGE_2);
		break;
	case 3:
		dma_outb(pagenr, DMA_PAGE_3);
		break;
	case 5:
		dma_outb(pagenr & 0xfe, DMA_PAGE_5);
		break;
	case 6:
		dma_outb(pagenr & 0xfe, DMA_PAGE_6);
		break;
	case 7:
		dma_outb(pagenr & 0xfe, DMA_PAGE_7);
		break;
	}
}


/* Set transfer address & page bits for specific DMA channel.
 * Assumes dma flipflop is clear.
 */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
	set_dma_page(dmanr, a>>16);
	if (dmanr <= 3)  {
		dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
		dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
	}  else  {
	    dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
	    dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
	}
}


/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
 * a specific DMA channel.
 * You must ensure the parameters are valid.
 * NOTE: from a manual: "the number of transfers is one more
 * than the initial word count"! This is taken into account.
 * Assumes dma flip-flop is clear.
 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 */
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
	count--;
	if (dmanr <= 3)  {
	    dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
	    dma_outb((count >> 8) & 0xff,
		     ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
	} else {
	    dma_outb((count >> 1) & 0xff,
		     ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
	    dma_outb((count >> 9) & 0xff,
		     ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
	}
}


/* Get DMA residue count. After a DMA transfer, this
 * should return zero. Reading this while a DMA transfer is
 * still in progress will return unpredictable results.
 * If called before the channel has been used, it may return 1.
 * Otherwise, it returns the number of _bytes_ left to transfer.
 *
 * Assumes DMA flip-flop is clear.
 */
static __inline__ int get_dma_residue(unsigned int dmanr)
{
	unsigned int io_port;
	/* using short to get 16-bit wrap around */
	unsigned short count;

	io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
		: ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;

	count = 1 + dma_inb(io_port);
	count += dma_inb(io_port) << 8;

	return (dmanr <= 3) ? count : (count << 1);
}


/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char *device_id);
extern void free_dma(unsigned int dmanr);

/* From PCI */

#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy	(0)
#endif

#endif /* _ASM_X86_DMA_H */
Commit	Line	Data
f28b8d60 TG	1	/*
	2	* linux/include/asm/dma.h: Defines for using and allocating dma channels.
	3	* Written by Hennus Bergman, 1992.
	4	* High DMA channel support & info by Hannu Savolainen
	5	* and John Boyd, Nov. 1992.
	6	*/
	7
	8	#ifndef _ASM_X86_DMA_H
	9	#define _ASM_X86_DMA_H
	10
	11	#include <linux/spinlock.h> /* And spinlocks */
	12	#include <asm/io.h> /* need byte IO */
	13	#include <linux/delay.h>
	14
	15
	16	#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
	17	#define dma_outb outb_p
	18	#else
	19	#define dma_outb outb
	20	#endif
	21
	22	#define dma_inb inb
	23
	24	/*
	25	* NOTES about DMA transfers:
	26	*
	27	* controller 1: channels 0-3, byte operations, ports 00-1F
	28	* controller 2: channels 4-7, word operations, ports C0-DF
	29	*
	30	* - ALL registers are 8 bits only, regardless of transfer size
	31	* - channel 4 is not used - cascades 1 into 2.
	32	* - channels 0-3 are byte - addresses/counts are for physical bytes
	33	* - channels 5-7 are word - addresses/counts are for physical words
	34	* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
	35	* - transfer count loaded to registers is 1 less than actual count
	36	* - controller 2 offsets are all even (2x offsets for controller 1)
	37	* - page registers for 5-7 don't use data bit 0, represent 128K pages
	38	* - page registers for 0-3 use bit 0, represent 64K pages
	39	*
	40	* DMA transfers are limited to the lower 16MB of _physical_ memory.
	41	* Note that addresses loaded into registers must be _physical_ addresses,
	42	* not logical addresses (which may differ if paging is active).
	43	*
	44	* Address mapping for channels 0-3:
	45	*
	46	* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
	47	* \| ... \| \| ... \| \| ... \|
	48	* \| ... \| \| ... \| \| ... \|
	49	* \| ... \| \| ... \| \| ... \|
	50	* P7 ... P0 A7 ... A0 A7 ... A0
	51	* \| Page \| Addr MSB \| Addr LSB \| (DMA registers)
	52	*
	53	* Address mapping for channels 5-7:
	54	*
	55	* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
	56	* \| ... \| \ \ ... \ \ \ ... \ \
	57	* \| ... \| \ \ ... \ \ \ ... \ (not used)
	58	* \| ... \| \ \ ... \ \ \ ... \
	59	* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
	60	* \| Page \| Addr MSB \| Addr LSB \| (DMA registers)
	61	*
	62	* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
	63	* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
	64	* the hardware level, so odd-byte transfers aren't possible).
65	*
66	* Transfer count (_not # bytes_) is limited to 64K, represented as actual
67	* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
68	* and up to 128K bytes may be transferred on channels 5-7 in one operation.
69	*
70	*/
71
72	#define MAX_DMA_CHANNELS 8
73
96a388de	74	#ifdef CONFIG_X86_32
f28b8d60 TG	75
	76	/* The maximum address that we can perform a DMA transfer to on this platform */
	77	#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
	78
	79	#else
	80
	81	/* 16MB ISA DMA zone */
	82	#define MAX_DMA_PFN ((1610241024) >> PAGE_SHIFT)
	83
	84	/* 4GB broken PCI/AGP hardware bus master zone */
	85	#define MAX_DMA32_PFN ((4UL10241024*1024) >> PAGE_SHIFT)
	86
	87	/* Compat define for old dma zone */
	88	#define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
	89
	90	#endif
	91
	92	/* 8237 DMA controllers */
	93	#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
	94	#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
	95
	96	/* DMA controller registers */
	97	#define DMA1_CMD_REG 0x08 /* command register (w) */
	98	#define DMA1_STAT_REG 0x08 /* status register (r) */
	99	#define DMA1_REQ_REG 0x09 /* request register (w) */
	100	#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
	101	#define DMA1_MODE_REG 0x0B /* mode register (w) */
	102	#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
	103	#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
	104	#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
	105	#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
	106	#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
	107
	108	#define DMA2_CMD_REG 0xD0 /* command register (w) */
	109	#define DMA2_STAT_REG 0xD0 /* status register (r) */
	110	#define DMA2_REQ_REG 0xD2 /* request register (w) */
	111	#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
	112	#define DMA2_MODE_REG 0xD6 /* mode register (w) */
	113	#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
	114	#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
	115	#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
	116	#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
	117	#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
	118
	119	#define DMA_ADDR_0 0x00 /* DMA address registers */
	120	#define DMA_ADDR_1 0x02
	121	#define DMA_ADDR_2 0x04
	122	#define DMA_ADDR_3 0x06
	123	#define DMA_ADDR_4 0xC0
	124	#define DMA_ADDR_5 0xC4
	125	#define DMA_ADDR_6 0xC8
	126	#define DMA_ADDR_7 0xCC
	127
	128	#define DMA_CNT_0 0x01 /* DMA count registers */
	129	#define DMA_CNT_1 0x03
	130	#define DMA_CNT_2 0x05
	131	#define DMA_CNT_3 0x07
	132	#define DMA_CNT_4 0xC2
	133	#define DMA_CNT_5 0xC6
	134	#define DMA_CNT_6 0xCA
	135	#define DMA_CNT_7 0xCE
	136
	137	#define DMA_PAGE_0 0x87 /* DMA page registers */
	138	#define DMA_PAGE_1 0x83
139	#define DMA_PAGE_2 0x81
140	#define DMA_PAGE_3 0x82
141	#define DMA_PAGE_5 0x8B
142	#define DMA_PAGE_6 0x89
143	#define DMA_PAGE_7 0x8A
144
145	/* I/O to memory, no autoinit, increment, single mode */
146	#define DMA_MODE_READ 0x44
147	/* memory to I/O, no autoinit, increment, single mode */
148	#define DMA_MODE_WRITE 0x48
149	/* pass thru DREQ->HRQ, DACK<-HLDA only */
150	#define DMA_MODE_CASCADE 0xC0
151
152	#define DMA_AUTOINIT 0x10
153
154
155	extern spinlock_t dma_spin_lock;
156
157	static __inline__ unsigned long claim_dma_lock(void)
158	{
159	unsigned long flags;
160	spin_lock_irqsave(&dma_spin_lock, flags);
161	return flags;
162	}
163
164	static __inline__ void release_dma_lock(unsigned long flags)
165	{
166	spin_unlock_irqrestore(&dma_spin_lock, flags);
167	}
168
169	/* enable/disable a specific DMA channel */
170	static __inline__ void enable_dma(unsigned int dmanr)
171	{
172	if (dmanr <= 3)
173	dma_outb(dmanr, DMA1_MASK_REG);
174	else
175	dma_outb(dmanr & 3, DMA2_MASK_REG);
176	}
177
178	static __inline__ void disable_dma(unsigned int dmanr)
179	{
180	if (dmanr <= 3)
181	dma_outb(dmanr \| 4, DMA1_MASK_REG);
182	else
183	dma_outb((dmanr & 3) \| 4, DMA2_MASK_REG);
184	}
185
186	/* Clear the 'DMA Pointer Flip Flop'.
187	* Write 0 for LSB/MSB, 1 for MSB/LSB access.
188	* Use this once to initialize the FF to a known state.
189	* After that, keep track of it. :-)
190	* --- In order to do that, the DMA routines below should ---
191	* --- only be used while holding the DMA lock ! ---
192	*/
193	static __inline__ void clear_dma_ff(unsigned int dmanr)
194	{
195	if (dmanr <= 3)
196	dma_outb(0, DMA1_CLEAR_FF_REG);
197	else
198	dma_outb(0, DMA2_CLEAR_FF_REG);
199	}
200
201	/* set mode (above) for a specific DMA channel */
202	static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
203	{
204	if (dmanr <= 3)
205	dma_outb(mode \| dmanr, DMA1_MODE_REG);
206	else
207	dma_outb(mode \| (dmanr & 3), DMA2_MODE_REG);
208	}
209
210	/* Set only the page register bits of the transfer address.
211	* This is used for successive transfers when we know the contents of
212	* the lower 16 bits of the DMA current address register, but a 64k boundary
213	* may have been crossed.
214	*/
215	static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
216	{
217	switch (dmanr) {
218	case 0:
219	dma_outb(pagenr, DMA_PAGE_0);
220	break;
221	case 1:
222	dma_outb(pagenr, DMA_PAGE_1);
223	break;
224	case 2:
225	dma_outb(pagenr, DMA_PAGE_2);
226	break;
227	case 3:
228	dma_outb(pagenr, DMA_PAGE_3);
229	break;
230	case 5:
231	dma_outb(pagenr & 0xfe, DMA_PAGE_5);
232	break;
233	case 6:
234	dma_outb(pagenr & 0xfe, DMA_PAGE_6);
235	break;
236	case 7:
237	dma_outb(pagenr & 0xfe, DMA_PAGE_7);
238	break;
239	}
240	}
241
242
243	/* Set transfer address & page bits for specific DMA channel.
244	* Assumes dma flipflop is clear.
245	*/
246	static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
247	{
248	set_dma_page(dmanr, a>>16);
249	if (dmanr <= 3) {
250	dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
251	dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
252	} else {
253	dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
254	dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
255	}
256	}
257
258
259	/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
260	* a specific DMA channel.
261	* You must ensure the parameters are valid.
262	* NOTE: from a manual: "the number of transfers is one more
263	* than the initial word count"! This is taken into account.
264	* Assumes dma flip-flop is clear.
265	* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
266	*/
267	static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
268	{
269	count--;
270	if (dmanr <= 3) {
271	dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
272	dma_outb((count >> 8) & 0xff,
273	((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
274	} else {
275	dma_outb((count >> 1) & 0xff,
276	((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
277	dma_outb((count >> 9) & 0xff,
278	((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
279	}
280	}
281
282
283	/* Get DMA residue count. After a DMA transfer, this
284	* should return zero. Reading this while a DMA transfer is
285	* still in progress will return unpredictable results.
286	* If called before the channel has been used, it may return 1.
287	* Otherwise, it returns the number of _bytes_ left to transfer.
288	*
289	* Assumes DMA flip-flop is clear.
290	*/
291	static __inline__ int get_dma_residue(unsigned int dmanr)
292	{
293	unsigned int io_port;
294	/* using short to get 16-bit wrap around */
295	unsigned short count;
296
297	io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
298	: ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
299
300	count = 1 + dma_inb(io_port);
301	count += dma_inb(io_port) << 8;
302
303	return (dmanr <= 3) ? count : (count << 1);
304	}
305
306
307	/* These are in kernel/dma.c: */
308	extern int request_dma(unsigned int dmanr, const char *device_id);
309	extern void free_dma(unsigned int dmanr);
310
311	/* From PCI */
312
313	#ifdef CONFIG_PCI
314	extern int isa_dma_bridge_buggy;
96a388de	315	#else
f28b8d60	316	#define isa_dma_bridge_buggy (0)
96a388de	317	#endif
f28b8d60 TG	318
f28b8d60 TG	319	#endif /* _ASM_X86_DMA_H */