[mirror_ubuntu-bionic-kernel.git] / include / asm-x86 / i387.h

/*
 * Copyright (C) 1994 Linus Torvalds
 *
 * Pentium III FXSR, SSE support
 * General FPU state handling cleanups
 *	Gareth Hughes <gareth@valinux.com>, May 2000
 * x86-64 work by Andi Kleen 2002
 */

#ifndef ASM_X86__I387_H
#define ASM_X86__I387_H

#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/regset.h>
#include <asm/asm.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
#include <asm/user.h>
#include <asm/uaccess.h>
#include <asm/xsave.h>

extern void fpu_init(void);
extern void mxcsr_feature_mask_init(void);
extern int init_fpu(struct task_struct *child);
extern asmlinkage void math_state_restore(void);
extern void init_thread_xstate(void);

extern user_regset_active_fn fpregs_active, xfpregs_active;
extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;

#ifdef CONFIG_IA32_EMULATION
struct _fpstate_ia32;
extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
#endif

#define X87_FSW_ES (1 << 7)	/* Exception Summary */

#ifdef CONFIG_X86_64

/* Ignore delayed exceptions from user space */
static inline void tolerant_fwait(void)
{
	asm volatile("1: fwait\n"
		     "2:\n"
		     _ASM_EXTABLE(1b, 2b));
}

static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
{
	int err;

	asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     _ASM_EXTABLE(1b, 3b)
		     : [err] "=r" (err)
#if 0 /* See comment in __save_init_fpu() below. */
		     : [fx] "r" (fx), "m" (*fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
#endif
	return err;
}

static inline int restore_fpu_checking(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE)
		return xrstor_checking(&tsk->thread.xstate->xsave);
	else
		return fxrstor_checking(&tsk->thread.xstate->fxsave);
}

/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
   is pending. Clear the x87 state here by setting it to fixed
   values. The kernel data segment can be sometimes 0 and sometimes
   new user value. Both should be ok.
   Use the PDA as safe address because it should be already in L1. */
static inline void clear_fpu_state(struct task_struct *tsk)
{
	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;

	/*
	 * xsave header may indicate the init state of the FP.
	 */
	if ((task_thread_info(tsk)->status & TS_XSAVE) &&
	    !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
		return;

	if (unlikely(fx->swd & X87_FSW_ES))
		asm volatile("fnclex");
	alternative_input(ASM_NOP8 ASM_NOP2,
			  "    emms\n"		/* clear stack tags */
			  "    fildl %%gs:0",	/* load to clear state */
			  X86_FEATURE_FXSAVE_LEAK);
}

static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
{
	int err;

	asm volatile("1:  rex64/fxsave (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     _ASM_EXTABLE(1b, 3b)
		     : [err] "=r" (err), "=m" (*fx)
#if 0 /* See comment in __fxsave_clear() below. */
		     : [fx] "r" (fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "0" (0));
#endif
	if (unlikely(err) &&
	    __clear_user(fx, sizeof(struct i387_fxsave_struct)))
		err = -EFAULT;
	/* No need to clear here because the caller clears USED_MATH */
	return err;
}

static inline void fxsave(struct task_struct *tsk)
{
	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	   uses any extended registers for addressing, a second REX prefix
	   will be generated (to the assembler, rex64 followed by semicolon
	   is a separate instruction), and hence the 64-bitness is lost. */
#if 0
	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	   starting with gas 2.16. */
	__asm__ __volatile__("fxsaveq %0"
			     : "=m" (tsk->thread.xstate->fxsave));
#elif 0
	/* Using, as a workaround, the properly prefixed form below isn't
	   accepted by any binutils version so far released, complaining that
	   the same type of prefix is used twice if an extended register is
	   needed for addressing (fix submitted to mainline 2005-11-21). */
	__asm__ __volatile__("rex64/fxsave %0"
			     : "=m" (tsk->thread.xstate->fxsave));
#else
	/* This, however, we can work around by forcing the compiler to select
	   an addressing mode that doesn't require extended registers. */
	__asm__ __volatile__("rex64/fxsave (%1)"
			     : "=m" (tsk->thread.xstate->fxsave)
			     : "cdaSDb" (&tsk->thread.xstate->fxsave));
#endif
}

static inline void __save_init_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE)
		xsave(tsk);
	else
		fxsave(tsk);

	clear_fpu_state(tsk);
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

#else  /* CONFIG_X86_32 */

extern void finit(void);

static inline void tolerant_fwait(void)
{
	asm volatile("fnclex ; fwait");
}

static inline void restore_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE) {
		xrstor_checking(&tsk->thread.xstate->xsave);
		return;
	}
	/*
	 * The "nop" is needed to make the instructions the same
	 * length.
	 */
	alternative_input(
		"nop ; frstor %1",
		"fxrstor %1",
		X86_FEATURE_FXSR,
		"m" (tsk->thread.xstate->fxsave));
}

/* We need a safe address that is cheap to find and that is already
   in L1 during context switch. The best choices are unfortunately
   different for UP and SMP */
#ifdef CONFIG_SMP
#define safe_address (__per_cpu_offset[0])
#else
#define safe_address (kstat_cpu(0).cpustat.user)
#endif

/*
 * These must be called with preempt disabled
 */
static inline void __save_init_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE) {
		struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
		struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;

		xsave(tsk);

		/*
		 * xsave header may indicate the init state of the FP.
		 */
		if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
			goto end;

		if (unlikely(fx->swd & X87_FSW_ES))
			asm volatile("fnclex");

		/*
		 * we can do a simple return here or be paranoid :)
		 */
		goto clear_state;
	}

	/* Use more nops than strictly needed in case the compiler
	   varies code */
	alternative_input(
		"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
		"fxsave %[fx]\n"
		"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
		X86_FEATURE_FXSR,
		[fx] "m" (tsk->thread.xstate->fxsave),
		[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
clear_state:
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	   is pending.  Clear the x87 state here by setting it to fixed
	   values. safe_address is a random variable that should be in L1 */
	alternative_input(
		GENERIC_NOP8 GENERIC_NOP2,
		"emms\n\t"	  	/* clear stack tags */
		"fildl %[addr]", 	/* set F?P to defined value */
		X86_FEATURE_FXSAVE_LEAK,
		[addr] "m" (safe_address));
end:
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

/*
 * Signal frame handlers...
 */
extern int save_i387(struct _fpstate __user *buf);
extern int restore_i387(struct _fpstate __user *buf);

#endif	/* CONFIG_X86_64 */

static inline void __unlazy_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		__save_init_fpu(tsk);
		stts();
	} else
		tsk->fpu_counter = 0;
}

static inline void __clear_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		tolerant_fwait();
		task_thread_info(tsk)->status &= ~TS_USEDFPU;
		stts();
	}
}

static inline void kernel_fpu_begin(void)
{
	struct thread_info *me = current_thread_info();
	preempt_disable();
	if (me->status & TS_USEDFPU)
		__save_init_fpu(me->task);
	else
		clts();
}

static inline void kernel_fpu_end(void)
{
	stts();
	preempt_enable();
}

#ifdef CONFIG_X86_64

static inline void save_init_fpu(struct task_struct *tsk)
{
	__save_init_fpu(tsk);
	stts();
}

#define unlazy_fpu	__unlazy_fpu
#define clear_fpu	__clear_fpu

#else  /* CONFIG_X86_32 */

/*
 * These disable preemption on their own and are safe
 */
static inline void save_init_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__save_init_fpu(tsk);
	stts();
	preempt_enable();
}

static inline void unlazy_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__unlazy_fpu(tsk);
	preempt_enable();
}

static inline void clear_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__clear_fpu(tsk);
	preempt_enable();
}

#endif	/* CONFIG_X86_64 */

/*
 * i387 state interaction
 */
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.xstate->fxsave.cwd;
	} else {
		return (unsigned short)tsk->thread.xstate->fsave.cwd;
	}
}

static inline unsigned short get_fpu_swd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.xstate->fxsave.swd;
	} else {
		return (unsigned short)tsk->thread.xstate->fsave.swd;
	}
}

static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
{
	if (cpu_has_xmm) {
		return tsk->thread.xstate->fxsave.mxcsr;
	} else {
		return MXCSR_DEFAULT;
	}
}

#endif /* ASM_X86__I387_H */
Commit	Line	Data
1eeaed76 RM	1	/*
	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Pentium III FXSR, SSE support
	5	* General FPU state handling cleanups
	6	* Gareth Hughes <gareth@valinux.com>, May 2000
	7	* x86-64 work by Andi Kleen 2002
	8	*/
	9
77ef50a5 VN	10	#ifndef ASM_X86__I387_H
77ef50a5 VN	11	#define ASM_X86__I387_H
1eeaed76 RM	12
	13	#include <linux/sched.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/regset.h>
92c37fa3	16	#include <asm/asm.h>
1eeaed76 RM	17	#include <asm/processor.h>
	18	#include <asm/sigcontext.h>
	19	#include <asm/user.h>
	20	#include <asm/uaccess.h>
dc1e35c6	21	#include <asm/xsave.h>
1eeaed76 RM	22
1eeaed76 RM	23	extern void fpu_init(void);
1eeaed76	24	extern void mxcsr_feature_mask_init(void);
aa283f49	25	extern int init_fpu(struct task_struct *child);
1eeaed76	26	extern asmlinkage void math_state_restore(void);
61c4628b	27	extern void init_thread_xstate(void);
1eeaed76 RM	28
	29	extern user_regset_active_fn fpregs_active, xfpregs_active;
	30	extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
	31	extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
	32
	33	#ifdef CONFIG_IA32_EMULATION
	34	struct _fpstate_ia32;
	35	extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
	36	extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
	37	#endif
	38
b359e8a4 SS	39	#define X87_FSW_ES (1 << 7) /* Exception Summary */
b359e8a4 SS	40
1eeaed76 RM	41	#ifdef CONFIG_X86_64
	42
	43	/* Ignore delayed exceptions from user space */
	44	static inline void tolerant_fwait(void)
	45	{
	46	asm volatile("1: fwait\n"
	47	"2:\n"
affe6637	48	_ASM_EXTABLE(1b, 2b));
1eeaed76 RM	49	}
1eeaed76 RM	50
b359e8a4	51	static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
1eeaed76 RM	52	{
	53	int err;
	54
	55	asm volatile("1: rex64/fxrstor (%[fx])\n\t"
	56	"2:\n"
	57	".section .fixup,\"ax\"\n"
	58	"3: movl $-1,%[err]\n"
	59	" jmp 2b\n"
	60	".previous\n"
affe6637	61	_ASM_EXTABLE(1b, 3b)
1eeaed76 RM	62	: [err] "=r" (err)
	63	#if 0 /* See comment in __save_init_fpu() below. */
	64	: [fx] "r" (fx), "m" (*fx), "0" (0));
	65	#else
	66	: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
	67	#endif
1eeaed76 RM	68	return err;
	69	}
	70
b359e8a4 SS	71	static inline int restore_fpu_checking(struct task_struct *tsk)
	72	{
	73	if (task_thread_info(tsk)->status & TS_XSAVE)
	74	return xrstor_checking(&tsk->thread.xstate->xsave);
	75	else
	76	return fxrstor_checking(&tsk->thread.xstate->fxsave);
	77	}
1eeaed76 RM	78
	79	/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
	80	is pending. Clear the x87 state here by setting it to fixed
	81	values. The kernel data segment can be sometimes 0 and sometimes
	82	new user value. Both should be ok.
	83	Use the PDA as safe address because it should be already in L1. */
b359e8a4	84	static inline void clear_fpu_state(struct task_struct *tsk)
1eeaed76	85	{
b359e8a4 SS	86	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
	87	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
	88
	89	/*
	90	* xsave header may indicate the init state of the FP.
	91	*/
	92	if ((task_thread_info(tsk)->status & TS_XSAVE) &&
	93	!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
	94	return;
	95
1eeaed76	96	if (unlikely(fx->swd & X87_FSW_ES))
affe6637	97	asm volatile("fnclex");
1eeaed76	98	alternative_input(ASM_NOP8 ASM_NOP2,
affe6637 JP	99	" emms\n" /* clear stack tags */
	100	" fildl %%gs:0", /* load to clear state */
	101	X86_FEATURE_FXSAVE_LEAK);
1eeaed76 RM	102	}
	103
	104	static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
	105	{
	106	int err;
	107
	108	asm volatile("1: rex64/fxsave (%[fx])\n\t"
	109	"2:\n"
	110	".section .fixup,\"ax\"\n"
	111	"3: movl $-1,%[err]\n"
	112	" jmp 2b\n"
	113	".previous\n"
affe6637	114	_ASM_EXTABLE(1b, 3b)
1eeaed76 RM	115	: [err] "=r" (err), "=m" (*fx)
	116	#if 0 /* See comment in __fxsave_clear() below. */
	117	: [fx] "r" (fx), "0" (0));
	118	#else
	119	: [fx] "cdaSDb" (fx), "0" (0));
	120	#endif
affe6637 JP	121	if (unlikely(err) &&
affe6637 JP	122	__clear_user(fx, sizeof(struct i387_fxsave_struct)))
1eeaed76 RM	123	err = -EFAULT;
	124	/* No need to clear here because the caller clears USED_MATH */
	125	return err;
	126	}
	127
b359e8a4	128	static inline void fxsave(struct task_struct *tsk)
1eeaed76 RM	129	{
	130	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	131	uses any extended registers for addressing, a second REX prefix
	132	will be generated (to the assembler, rex64 followed by semicolon
	133	is a separate instruction), and hence the 64-bitness is lost. */
	134	#if 0
	135	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	136	starting with gas 2.16. */
	137	__asm__ __volatile__("fxsaveq %0"
61c4628b	138	: "=m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	139	#elif 0
	140	/* Using, as a workaround, the properly prefixed form below isn't
	141	accepted by any binutils version so far released, complaining that
	142	the same type of prefix is used twice if an extended register is
	143	needed for addressing (fix submitted to mainline 2005-11-21). */
	144	__asm__ __volatile__("rex64/fxsave %0"
61c4628b	145	: "=m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	146	#else
	147	/* This, however, we can work around by forcing the compiler to select
	148	an addressing mode that doesn't require extended registers. */
61c4628b SS	149	__asm__ __volatile__("rex64/fxsave (%1)"
	150	: "=m" (tsk->thread.xstate->fxsave)
	151	: "cdaSDb" (&tsk->thread.xstate->fxsave));
1eeaed76	152	#endif
b359e8a4 SS	153	}
	154
	155	static inline void __save_init_fpu(struct task_struct *tsk)
	156	{
	157	if (task_thread_info(tsk)->status & TS_XSAVE)
	158	xsave(tsk);
	159	else
	160	fxsave(tsk);
	161
	162	clear_fpu_state(tsk);
1eeaed76 RM	163	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	164	}
	165
1eeaed76 RM	166	#else /* CONFIG_X86_32 */
1eeaed76 RM	167
e8a496ac SS	168	extern void finit(void);
e8a496ac SS	169
1eeaed76 RM	170	static inline void tolerant_fwait(void)
	171	{
	172	asm volatile("fnclex ; fwait");
	173	}
	174
	175	static inline void restore_fpu(struct task_struct *tsk)
	176	{
b359e8a4 SS	177	if (task_thread_info(tsk)->status & TS_XSAVE) {
	178	xrstor_checking(&tsk->thread.xstate->xsave);
	179	return;
	180	}
1eeaed76 RM	181	/*
	182	* The "nop" is needed to make the instructions the same
	183	* length.
	184	*/
	185	alternative_input(
	186	"nop ; frstor %1",
	187	"fxrstor %1",
	188	X86_FEATURE_FXSR,
61c4628b	189	"m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	190	}
	191
	192	/* We need a safe address that is cheap to find and that is already
	193	in L1 during context switch. The best choices are unfortunately
	194	different for UP and SMP */
	195	#ifdef CONFIG_SMP
	196	#define safe_address (__per_cpu_offset[0])
	197	#else
	198	#define safe_address (kstat_cpu(0).cpustat.user)
	199	#endif
	200
	201	/*
	202	* These must be called with preempt disabled
	203	*/
	204	static inline void __save_init_fpu(struct task_struct *tsk)
	205	{
b359e8a4 SS	206	if (task_thread_info(tsk)->status & TS_XSAVE) {
	207	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
	208	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
	209
	210	xsave(tsk);
	211
	212	/*
	213	* xsave header may indicate the init state of the FP.
	214	*/
	215	if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
	216	goto end;
	217
	218	if (unlikely(fx->swd & X87_FSW_ES))
	219	asm volatile("fnclex");
	220
	221	/*
	222	* we can do a simple return here or be paranoid :)
	223	*/
	224	goto clear_state;
	225	}
	226
1eeaed76 RM	227	/* Use more nops than strictly needed in case the compiler
	228	varies code */
	229	alternative_input(
	230	"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
	231	"fxsave %[fx]\n"
	232	"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
	233	X86_FEATURE_FXSR,
61c4628b SS	234	[fx] "m" (tsk->thread.xstate->fxsave),
61c4628b SS	235	[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
b359e8a4	236	clear_state:
1eeaed76 RM	237	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	238	is pending. Clear the x87 state here by setting it to fixed
	239	values. safe_address is a random variable that should be in L1 */
	240	alternative_input(
	241	GENERIC_NOP8 GENERIC_NOP2,
	242	"emms\n\t" /* clear stack tags */
	243	"fildl %[addr]", /* set F?P to defined value */
	244	X86_FEATURE_FXSAVE_LEAK,
	245	[addr] "m" (safe_address));
b359e8a4	246	end:
1eeaed76 RM	247	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	248	}
	249
	250	/*
	251	* Signal frame handlers...
	252	*/
	253	extern int save_i387(struct _fpstate __user *buf);
	254	extern int restore_i387(struct _fpstate __user *buf);
	255
	256	#endif /* CONFIG_X86_64 */
	257
	258	static inline void __unlazy_fpu(struct task_struct *tsk)
	259	{
	260	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	261	__save_init_fpu(tsk);
	262	stts();
	263	} else
	264	tsk->fpu_counter = 0;
	265	}
	266
	267	static inline void __clear_fpu(struct task_struct *tsk)
	268	{
	269	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	270	tolerant_fwait();
	271	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	272	stts();
	273	}
	274	}
	275
	276	static inline void kernel_fpu_begin(void)
	277	{
	278	struct thread_info *me = current_thread_info();
	279	preempt_disable();
	280	if (me->status & TS_USEDFPU)
	281	__save_init_fpu(me->task);
	282	else
	283	clts();
	284	}
	285
	286	static inline void kernel_fpu_end(void)
	287	{
	288	stts();
	289	preempt_enable();
	290	}
	291
	292	#ifdef CONFIG_X86_64
	293
	294	static inline void save_init_fpu(struct task_struct *tsk)
	295	{
	296	__save_init_fpu(tsk);
	297	stts();
	298	}
	299
	300	#define unlazy_fpu __unlazy_fpu
	301	#define clear_fpu __clear_fpu
	302
	303	#else /* CONFIG_X86_32 */
	304
	305	/*
	306	* These disable preemption on their own and are safe
	307	*/
	308	static inline void save_init_fpu(struct task_struct *tsk)
	309	{
	310	preempt_disable();
311	__save_init_fpu(tsk);
312	stts();
313	preempt_enable();
314	}
315
316	static inline void unlazy_fpu(struct task_struct *tsk)
317	{
318	preempt_disable();
319	__unlazy_fpu(tsk);
320	preempt_enable();
321	}
322
323	static inline void clear_fpu(struct task_struct *tsk)
324	{
325	preempt_disable();
326	__clear_fpu(tsk);
327	preempt_enable();
328	}
329
330	#endif /* CONFIG_X86_64 */
331
1eeaed76 RM	332	/*
	333	* i387 state interaction
	334	*/
	335	static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
	336	{
	337	if (cpu_has_fxsr) {
61c4628b	338	return tsk->thread.xstate->fxsave.cwd;
1eeaed76	339	} else {
1679f271	340	return (unsigned short)tsk->thread.xstate->fsave.cwd;
1eeaed76 RM	341	}
	342	}
	343
	344	static inline unsigned short get_fpu_swd(struct task_struct *tsk)
	345	{
	346	if (cpu_has_fxsr) {
61c4628b	347	return tsk->thread.xstate->fxsave.swd;
1eeaed76	348	} else {
1679f271	349	return (unsigned short)tsk->thread.xstate->fsave.swd;
1eeaed76 RM	350	}
	351	}
	352
	353	static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
	354	{
	355	if (cpu_has_xmm) {
61c4628b	356	return tsk->thread.xstate->fxsave.mxcsr;
1eeaed76 RM	357	} else {
	358	return MXCSR_DEFAULT;
	359	}
	360	}
	361
77ef50a5	362	#endif /* ASM_X86__I387_H */