]>
Commit | Line | Data |
---|---|---|
d3561b7f RR |
1 | #ifndef __ASM_PARAVIRT_H |
2 | #define __ASM_PARAVIRT_H | |
3 | /* Various instructions on x86 need to be replaced for | |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
da181a8b | 7 | #include <asm/page.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
139ec7c4 | 10 | /* Bitmask of what can be clobbered: usually at least eax. */ |
21438f7c GOC |
11 | #define CLBR_NONE 0 |
12 | #define CLBR_EAX (1 << 0) | |
13 | #define CLBR_ECX (1 << 1) | |
14 | #define CLBR_EDX (1 << 2) | |
15 | ||
16 | #ifdef CONFIG_X86_64 | |
17 | #define CLBR_RSI (1 << 3) | |
18 | #define CLBR_RDI (1 << 4) | |
19 | #define CLBR_R8 (1 << 5) | |
20 | #define CLBR_R9 (1 << 6) | |
21 | #define CLBR_R10 (1 << 7) | |
22 | #define CLBR_R11 (1 << 8) | |
23 | #define CLBR_ANY ((1 << 9) - 1) | |
24 | #include <asm/desc_defs.h> | |
25 | #else | |
26 | /* CLBR_ANY should match all regs platform has. For i386, that's just it */ | |
27 | #define CLBR_ANY ((1 << 3) - 1) | |
28 | #endif /* X86_64 */ | |
139ec7c4 | 29 | |
d3561b7f | 30 | #ifndef __ASSEMBLY__ |
3dc494e8 | 31 | #include <linux/types.h> |
d4c10477 | 32 | #include <linux/cpumask.h> |
ce6234b5 | 33 | #include <asm/kmap_types.h> |
8d947344 | 34 | #include <asm/desc_defs.h> |
3dc494e8 | 35 | |
ce6234b5 | 36 | struct page; |
d3561b7f | 37 | struct thread_struct; |
6b68f01b | 38 | struct desc_ptr; |
d3561b7f | 39 | struct tss_struct; |
da181a8b | 40 | struct mm_struct; |
90a0a06a | 41 | struct desc_struct; |
294688c0 | 42 | |
93b1eab3 JF |
43 | /* general info */ |
44 | struct pv_info { | |
d3561b7f | 45 | unsigned int kernel_rpl; |
5311ab62 | 46 | int shared_kernel_pmd; |
93b1eab3 | 47 | int paravirt_enabled; |
d3561b7f | 48 | const char *name; |
93b1eab3 | 49 | }; |
d3561b7f | 50 | |
93b1eab3 | 51 | struct pv_init_ops { |
139ec7c4 | 52 | /* |
93b1eab3 JF |
53 | * Patch may replace one of the defined code sequences with |
54 | * arbitrary code, subject to the same register constraints. | |
55 | * This generally means the code is not free to clobber any | |
56 | * registers other than EAX. The patch function should return | |
57 | * the number of bytes of code generated, as we nop pad the | |
58 | * rest in generic code. | |
139ec7c4 | 59 | */ |
ab144f5e AK |
60 | unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, |
61 | unsigned long addr, unsigned len); | |
139ec7c4 | 62 | |
294688c0 | 63 | /* Basic arch-specific setup */ |
d3561b7f RR |
64 | void (*arch_setup)(void); |
65 | char *(*memory_setup)(void); | |
6996d3b6 JF |
66 | void (*post_allocator_init)(void); |
67 | ||
294688c0 | 68 | /* Print a banner to identify the environment */ |
d3561b7f | 69 | void (*banner)(void); |
93b1eab3 JF |
70 | }; |
71 | ||
72 | ||
8965c1c0 | 73 | struct pv_lazy_ops { |
93b1eab3 | 74 | /* Set deferred update mode, used for batching operations. */ |
8965c1c0 JF |
75 | void (*enter)(void); |
76 | void (*leave)(void); | |
93b1eab3 JF |
77 | }; |
78 | ||
79 | struct pv_time_ops { | |
80 | void (*time_init)(void); | |
d3561b7f | 81 | |
294688c0 | 82 | /* Set and set time of day */ |
d3561b7f RR |
83 | unsigned long (*get_wallclock)(void); |
84 | int (*set_wallclock)(unsigned long); | |
d3561b7f | 85 | |
93b1eab3 JF |
86 | unsigned long long (*sched_clock)(void); |
87 | unsigned long (*get_cpu_khz)(void); | |
88 | }; | |
d3561b7f | 89 | |
93b1eab3 | 90 | struct pv_cpu_ops { |
294688c0 | 91 | /* hooks for various privileged instructions */ |
1a1eecd1 AK |
92 | unsigned long (*get_debugreg)(int regno); |
93 | void (*set_debugreg)(int regno, unsigned long value); | |
d3561b7f | 94 | |
1a1eecd1 | 95 | void (*clts)(void); |
d3561b7f | 96 | |
1a1eecd1 AK |
97 | unsigned long (*read_cr0)(void); |
98 | void (*write_cr0)(unsigned long); | |
d3561b7f | 99 | |
1a1eecd1 AK |
100 | unsigned long (*read_cr4_safe)(void); |
101 | unsigned long (*read_cr4)(void); | |
102 | void (*write_cr4)(unsigned long); | |
d3561b7f | 103 | |
4c9890c2 GOC |
104 | #ifdef CONFIG_X86_64 |
105 | unsigned long (*read_cr8)(void); | |
106 | void (*write_cr8)(unsigned long); | |
107 | #endif | |
108 | ||
294688c0 | 109 | /* Segment descriptor handling */ |
1a1eecd1 | 110 | void (*load_tr_desc)(void); |
6b68f01b GOC |
111 | void (*load_gdt)(const struct desc_ptr *); |
112 | void (*load_idt)(const struct desc_ptr *); | |
113 | void (*store_gdt)(struct desc_ptr *); | |
114 | void (*store_idt)(struct desc_ptr *); | |
1a1eecd1 AK |
115 | void (*set_ldt)(const void *desc, unsigned entries); |
116 | unsigned long (*store_tr)(void); | |
117 | void (*load_tls)(struct thread_struct *t, unsigned int cpu); | |
75b8bb3e GOC |
118 | void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum, |
119 | const void *desc); | |
90a0a06a | 120 | void (*write_gdt_entry)(struct desc_struct *, |
014b15be | 121 | int entrynum, const void *desc, int size); |
8d947344 GOC |
122 | void (*write_idt_entry)(gate_desc *, |
123 | int entrynum, const gate_desc *gate); | |
faca6227 | 124 | void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t); |
d3561b7f | 125 | |
1a1eecd1 | 126 | void (*set_iopl_mask)(unsigned mask); |
93b1eab3 JF |
127 | |
128 | void (*wbinvd)(void); | |
1a1eecd1 | 129 | void (*io_delay)(void); |
d3561b7f | 130 | |
93b1eab3 JF |
131 | /* cpuid emulation, mostly so that caps bits can be disabled */ |
132 | void (*cpuid)(unsigned int *eax, unsigned int *ebx, | |
133 | unsigned int *ecx, unsigned int *edx); | |
134 | ||
135 | /* MSR, PMC and TSR operations. | |
136 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ | |
137 | u64 (*read_msr)(unsigned int msr, int *err); | |
c9dcda5c | 138 | int (*write_msr)(unsigned int msr, unsigned low, unsigned high); |
93b1eab3 JF |
139 | |
140 | u64 (*read_tsc)(void); | |
b8d1fae7 | 141 | u64 (*read_pmc)(int counter); |
e5aaac44 | 142 | unsigned long long (*read_tscp)(unsigned int *aux); |
93b1eab3 JF |
143 | |
144 | /* These two are jmp to, not actually called. */ | |
6abcd98f | 145 | void (*irq_enable_syscall_ret)(void); |
93b1eab3 | 146 | void (*iret)(void); |
8965c1c0 | 147 | |
e801f864 GOC |
148 | void (*swapgs)(void); |
149 | ||
8965c1c0 | 150 | struct pv_lazy_ops lazy_mode; |
93b1eab3 JF |
151 | }; |
152 | ||
153 | struct pv_irq_ops { | |
154 | void (*init_IRQ)(void); | |
155 | ||
294688c0 | 156 | /* |
93b1eab3 JF |
157 | * Get/set interrupt state. save_fl and restore_fl are only |
158 | * expected to use X86_EFLAGS_IF; all other bits | |
159 | * returned from save_fl are undefined, and may be ignored by | |
160 | * restore_fl. | |
294688c0 | 161 | */ |
93b1eab3 JF |
162 | unsigned long (*save_fl)(void); |
163 | void (*restore_fl)(unsigned long); | |
164 | void (*irq_disable)(void); | |
165 | void (*irq_enable)(void); | |
166 | void (*safe_halt)(void); | |
167 | void (*halt)(void); | |
168 | }; | |
d6dd61c8 | 169 | |
93b1eab3 | 170 | struct pv_apic_ops { |
13623d79 | 171 | #ifdef CONFIG_X86_LOCAL_APIC |
294688c0 JF |
172 | /* |
173 | * Direct APIC operations, principally for VMI. Ideally | |
174 | * these shouldn't be in this interface. | |
175 | */ | |
42e0a9aa TG |
176 | void (*apic_write)(unsigned long reg, u32 v); |
177 | void (*apic_write_atomic)(unsigned long reg, u32 v); | |
178 | u32 (*apic_read)(unsigned long reg); | |
bbab4f3b ZA |
179 | void (*setup_boot_clock)(void); |
180 | void (*setup_secondary_clock)(void); | |
294688c0 JF |
181 | |
182 | void (*startup_ipi_hook)(int phys_apicid, | |
183 | unsigned long start_eip, | |
184 | unsigned long start_esp); | |
13623d79 | 185 | #endif |
93b1eab3 JF |
186 | }; |
187 | ||
188 | struct pv_mmu_ops { | |
189 | /* | |
190 | * Called before/after init_mm pagetable setup. setup_start | |
191 | * may reset %cr3, and may pre-install parts of the pagetable; | |
192 | * pagetable setup is expected to preserve any existing | |
193 | * mapping. | |
194 | */ | |
195 | void (*pagetable_setup_start)(pgd_t *pgd_base); | |
196 | void (*pagetable_setup_done)(pgd_t *pgd_base); | |
197 | ||
198 | unsigned long (*read_cr2)(void); | |
199 | void (*write_cr2)(unsigned long); | |
200 | ||
201 | unsigned long (*read_cr3)(void); | |
202 | void (*write_cr3)(unsigned long); | |
203 | ||
204 | /* | |
205 | * Hooks for intercepting the creation/use/destruction of an | |
206 | * mm_struct. | |
207 | */ | |
208 | void (*activate_mm)(struct mm_struct *prev, | |
209 | struct mm_struct *next); | |
210 | void (*dup_mmap)(struct mm_struct *oldmm, | |
211 | struct mm_struct *mm); | |
212 | void (*exit_mmap)(struct mm_struct *mm); | |
213 | ||
13623d79 | 214 | |
294688c0 | 215 | /* TLB operations */ |
1a1eecd1 AK |
216 | void (*flush_tlb_user)(void); |
217 | void (*flush_tlb_kernel)(void); | |
f8822f42 | 218 | void (*flush_tlb_single)(unsigned long addr); |
d4c10477 JF |
219 | void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm, |
220 | unsigned long va); | |
1a1eecd1 | 221 | |
294688c0 | 222 | /* Hooks for allocating/releasing pagetable pages */ |
6944a9c8 JF |
223 | void (*alloc_pte)(struct mm_struct *mm, u32 pfn); |
224 | void (*alloc_pmd)(struct mm_struct *mm, u32 pfn); | |
225 | void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); | |
2761fa09 | 226 | void (*alloc_pud)(struct mm_struct *mm, u32 pfn); |
6944a9c8 JF |
227 | void (*release_pte)(u32 pfn); |
228 | void (*release_pmd)(u32 pfn); | |
2761fa09 | 229 | void (*release_pud)(u32 pfn); |
1a1eecd1 | 230 | |
294688c0 | 231 | /* Pagetable manipulation functions */ |
1a1eecd1 | 232 | void (*set_pte)(pte_t *ptep, pte_t pteval); |
294688c0 JF |
233 | void (*set_pte_at)(struct mm_struct *mm, unsigned long addr, |
234 | pte_t *ptep, pte_t pteval); | |
1a1eecd1 | 235 | void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval); |
49cd740b JP |
236 | void (*pte_update)(struct mm_struct *mm, unsigned long addr, |
237 | pte_t *ptep); | |
294688c0 JF |
238 | void (*pte_update_defer)(struct mm_struct *mm, |
239 | unsigned long addr, pte_t *ptep); | |
3dc494e8 | 240 | |
5b8dd1e9 JF |
241 | pteval_t (*pte_val)(pte_t); |
242 | pte_t (*make_pte)(pteval_t pte); | |
243 | ||
244 | pgdval_t (*pgd_val)(pgd_t); | |
245 | pgd_t (*make_pgd)(pgdval_t pgd); | |
246 | ||
247 | #if PAGETABLE_LEVELS >= 3 | |
da181a8b | 248 | #ifdef CONFIG_X86_PAE |
1a1eecd1 | 249 | void (*set_pte_atomic)(pte_t *ptep, pte_t pteval); |
93b1eab3 JF |
250 | void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, |
251 | pte_t *ptep, pte_t pte); | |
49cd740b JP |
252 | void (*pte_clear)(struct mm_struct *mm, unsigned long addr, |
253 | pte_t *ptep); | |
1a1eecd1 | 254 | void (*pmd_clear)(pmd_t *pmdp); |
3dc494e8 | 255 | |
5b8dd1e9 | 256 | #endif /* CONFIG_X86_PAE */ |
3dc494e8 | 257 | |
5b8dd1e9 | 258 | void (*set_pud)(pud_t *pudp, pud_t pudval); |
3dc494e8 | 259 | |
5b8dd1e9 JF |
260 | pmdval_t (*pmd_val)(pmd_t); |
261 | pmd_t (*make_pmd)(pmdval_t pmd); | |
262 | ||
263 | #if PAGETABLE_LEVELS == 4 | |
264 | pudval_t (*pud_val)(pud_t); | |
265 | pud_t (*make_pud)(pudval_t pud); | |
9042219c EH |
266 | |
267 | void (*set_pgd)(pgd_t *pudp, pgd_t pgdval); | |
5b8dd1e9 JF |
268 | #endif /* PAGETABLE_LEVELS == 4 */ |
269 | #endif /* PAGETABLE_LEVELS >= 3 */ | |
da181a8b | 270 | |
93b1eab3 JF |
271 | #ifdef CONFIG_HIGHPTE |
272 | void *(*kmap_atomic_pte)(struct page *page, enum km_type type); | |
273 | #endif | |
8965c1c0 JF |
274 | |
275 | struct pv_lazy_ops lazy_mode; | |
93b1eab3 | 276 | }; |
9226d125 | 277 | |
93b1eab3 JF |
278 | /* This contains all the paravirt structures: we get a convenient |
279 | * number for each function using the offset which we use to indicate | |
280 | * what to patch. */ | |
49cd740b | 281 | struct paravirt_patch_template { |
93b1eab3 | 282 | struct pv_init_ops pv_init_ops; |
93b1eab3 JF |
283 | struct pv_time_ops pv_time_ops; |
284 | struct pv_cpu_ops pv_cpu_ops; | |
285 | struct pv_irq_ops pv_irq_ops; | |
286 | struct pv_apic_ops pv_apic_ops; | |
287 | struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f RR |
288 | }; |
289 | ||
93b1eab3 JF |
290 | extern struct pv_info pv_info; |
291 | extern struct pv_init_ops pv_init_ops; | |
93b1eab3 JF |
292 | extern struct pv_time_ops pv_time_ops; |
293 | extern struct pv_cpu_ops pv_cpu_ops; | |
294 | extern struct pv_irq_ops pv_irq_ops; | |
295 | extern struct pv_apic_ops pv_apic_ops; | |
296 | extern struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f | 297 | |
d5822035 | 298 | #define PARAVIRT_PATCH(x) \ |
93b1eab3 | 299 | (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) |
d5822035 | 300 | |
93b1eab3 JF |
301 | #define paravirt_type(op) \ |
302 | [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ | |
303 | [paravirt_opptr] "m" (op) | |
d5822035 JF |
304 | #define paravirt_clobber(clobber) \ |
305 | [paravirt_clobber] "i" (clobber) | |
306 | ||
294688c0 JF |
307 | /* |
308 | * Generate some code, and mark it as patchable by the | |
309 | * apply_paravirt() alternate instruction patcher. | |
310 | */ | |
d5822035 JF |
311 | #define _paravirt_alt(insn_string, type, clobber) \ |
312 | "771:\n\t" insn_string "\n" "772:\n" \ | |
313 | ".pushsection .parainstructions,\"a\"\n" \ | |
658be9d3 GOC |
314 | _ASM_ALIGN "\n" \ |
315 | _ASM_PTR " 771b\n" \ | |
d5822035 JF |
316 | " .byte " type "\n" \ |
317 | " .byte 772b-771b\n" \ | |
318 | " .short " clobber "\n" \ | |
319 | ".popsection\n" | |
320 | ||
294688c0 | 321 | /* Generate patchable code, with the default asm parameters. */ |
f8822f42 | 322 | #define paravirt_alt(insn_string) \ |
d5822035 JF |
323 | _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]") |
324 | ||
2f485ef5 GOC |
325 | /* Simple instruction patching code. */ |
326 | #define DEF_NATIVE(ops, name, code) \ | |
327 | extern const char start_##ops##_##name[], end_##ops##_##name[]; \ | |
328 | asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":") | |
329 | ||
63f70270 JF |
330 | unsigned paravirt_patch_nop(void); |
331 | unsigned paravirt_patch_ignore(unsigned len); | |
ab144f5e AK |
332 | unsigned paravirt_patch_call(void *insnbuf, |
333 | const void *target, u16 tgt_clobbers, | |
334 | unsigned long addr, u16 site_clobbers, | |
63f70270 | 335 | unsigned len); |
93b1eab3 | 336 | unsigned paravirt_patch_jmp(void *insnbuf, const void *target, |
ab144f5e AK |
337 | unsigned long addr, unsigned len); |
338 | unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf, | |
339 | unsigned long addr, unsigned len); | |
63f70270 | 340 | |
ab144f5e | 341 | unsigned paravirt_patch_insns(void *insnbuf, unsigned len, |
63f70270 JF |
342 | const char *start, const char *end); |
343 | ||
2f485ef5 GOC |
344 | unsigned native_patch(u8 type, u16 clobbers, void *ibuf, |
345 | unsigned long addr, unsigned len); | |
346 | ||
d572929c | 347 | int paravirt_disable_iospace(void); |
63f70270 | 348 | |
294688c0 JF |
349 | /* |
350 | * This generates an indirect call based on the operation type number. | |
351 | * The type number, computed in PARAVIRT_PATCH, is derived from the | |
93b1eab3 JF |
352 | * offset into the paravirt_patch_template structure, and can therefore be |
353 | * freely converted back into a structure offset. | |
294688c0 | 354 | */ |
93b1eab3 | 355 | #define PARAVIRT_CALL "call *%[paravirt_opptr];" |
294688c0 JF |
356 | |
357 | /* | |
93b1eab3 JF |
358 | * These macros are intended to wrap calls through one of the paravirt |
359 | * ops structs, so that they can be later identified and patched at | |
294688c0 JF |
360 | * runtime. |
361 | * | |
362 | * Normally, a call to a pv_op function is a simple indirect call: | |
a4746364 | 363 | * (pv_op_struct.operations)(args...). |
294688c0 JF |
364 | * |
365 | * Unfortunately, this is a relatively slow operation for modern CPUs, | |
366 | * because it cannot necessarily determine what the destination | |
367 | * address is. In this case, the address is a runtime constant, so at | |
368 | * the very least we can patch the call to e a simple direct call, or | |
369 | * ideally, patch an inline implementation into the callsite. (Direct | |
370 | * calls are essentially free, because the call and return addresses | |
371 | * are completely predictable.) | |
372 | * | |
a4746364 | 373 | * For i386, these macros rely on the standard gcc "regparm(3)" calling |
294688c0 JF |
374 | * convention, in which the first three arguments are placed in %eax, |
375 | * %edx, %ecx (in that order), and the remaining arguments are placed | |
376 | * on the stack. All caller-save registers (eax,edx,ecx) are expected | |
377 | * to be modified (either clobbered or used for return values). | |
a4746364 GOC |
378 | * X86_64, on the other hand, already specifies a register-based calling |
379 | * conventions, returning at %rax, with parameteres going on %rdi, %rsi, | |
380 | * %rdx, and %rcx. Note that for this reason, x86_64 does not need any | |
381 | * special handling for dealing with 4 arguments, unlike i386. | |
382 | * However, x86_64 also have to clobber all caller saved registers, which | |
383 | * unfortunately, are quite a bit (r8 - r11) | |
294688c0 JF |
384 | * |
385 | * The call instruction itself is marked by placing its start address | |
386 | * and size into the .parainstructions section, so that | |
387 | * apply_paravirt() in arch/i386/kernel/alternative.c can do the | |
93b1eab3 | 388 | * appropriate patching under the control of the backend pv_init_ops |
294688c0 JF |
389 | * implementation. |
390 | * | |
391 | * Unfortunately there's no way to get gcc to generate the args setup | |
392 | * for the call, and then allow the call itself to be generated by an | |
393 | * inline asm. Because of this, we must do the complete arg setup and | |
394 | * return value handling from within these macros. This is fairly | |
395 | * cumbersome. | |
396 | * | |
397 | * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments. | |
398 | * It could be extended to more arguments, but there would be little | |
399 | * to be gained from that. For each number of arguments, there are | |
400 | * the two VCALL and CALL variants for void and non-void functions. | |
401 | * | |
402 | * When there is a return value, the invoker of the macro must specify | |
403 | * the return type. The macro then uses sizeof() on that type to | |
404 | * determine whether its a 32 or 64 bit value, and places the return | |
405 | * in the right register(s) (just %eax for 32-bit, and %edx:%eax for | |
a4746364 GOC |
406 | * 64-bit). For x86_64 machines, it just returns at %rax regardless of |
407 | * the return value size. | |
294688c0 JF |
408 | * |
409 | * 64-bit arguments are passed as a pair of adjacent 32-bit arguments | |
a4746364 GOC |
410 | * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments |
411 | * in low,high order | |
294688c0 JF |
412 | * |
413 | * Small structures are passed and returned in registers. The macro | |
414 | * calling convention can't directly deal with this, so the wrapper | |
415 | * functions must do this. | |
416 | * | |
417 | * These PVOP_* macros are only defined within this header. This | |
418 | * means that all uses must be wrapped in inline functions. This also | |
419 | * makes sure the incoming and outgoing types are always correct. | |
420 | */ | |
a4746364 GOC |
421 | #ifdef CONFIG_X86_32 |
422 | #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx | |
423 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS | |
424 | #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \ | |
425 | "=c" (__ecx) | |
426 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS | |
427 | #define EXTRA_CLOBBERS | |
428 | #define VEXTRA_CLOBBERS | |
429 | #else | |
430 | #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx | |
431 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax | |
432 | #define PVOP_VCALL_CLOBBERS "=D" (__edi), \ | |
433 | "=S" (__esi), "=d" (__edx), \ | |
434 | "=c" (__ecx) | |
435 | ||
436 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax) | |
437 | ||
438 | #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11" | |
439 | #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11" | |
440 | #endif | |
441 | ||
1a45b7aa | 442 | #define __PVOP_CALL(rettype, op, pre, post, ...) \ |
f8822f42 | 443 | ({ \ |
1a45b7aa | 444 | rettype __ret; \ |
a4746364 GOC |
445 | PVOP_CALL_ARGS; \ |
446 | /* This is 32-bit specific, but is okay in 64-bit */ \ | |
447 | /* since this condition will never hold */ \ | |
1a45b7aa JF |
448 | if (sizeof(rettype) > sizeof(unsigned long)) { \ |
449 | asm volatile(pre \ | |
450 | paravirt_alt(PARAVIRT_CALL) \ | |
451 | post \ | |
a4746364 | 452 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
453 | : paravirt_type(op), \ |
454 | paravirt_clobber(CLBR_ANY), \ | |
455 | ##__VA_ARGS__ \ | |
a4746364 | 456 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 457 | __ret = (rettype)((((u64)__edx) << 32) | __eax); \ |
f8822f42 | 458 | } else { \ |
1a45b7aa | 459 | asm volatile(pre \ |
f8822f42 | 460 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 461 | post \ |
a4746364 | 462 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
463 | : paravirt_type(op), \ |
464 | paravirt_clobber(CLBR_ANY), \ | |
465 | ##__VA_ARGS__ \ | |
a4746364 | 466 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 467 | __ret = (rettype)__eax; \ |
f8822f42 JF |
468 | } \ |
469 | __ret; \ | |
470 | }) | |
1a45b7aa | 471 | #define __PVOP_VCALL(op, pre, post, ...) \ |
f8822f42 | 472 | ({ \ |
a4746364 | 473 | PVOP_VCALL_ARGS; \ |
1a45b7aa | 474 | asm volatile(pre \ |
f8822f42 | 475 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 476 | post \ |
a4746364 | 477 | : PVOP_VCALL_CLOBBERS \ |
1a45b7aa JF |
478 | : paravirt_type(op), \ |
479 | paravirt_clobber(CLBR_ANY), \ | |
480 | ##__VA_ARGS__ \ | |
a4746364 | 481 | : "memory", "cc" VEXTRA_CLOBBERS); \ |
f8822f42 JF |
482 | }) |
483 | ||
1a45b7aa JF |
484 | #define PVOP_CALL0(rettype, op) \ |
485 | __PVOP_CALL(rettype, op, "", "") | |
486 | #define PVOP_VCALL0(op) \ | |
487 | __PVOP_VCALL(op, "", "") | |
488 | ||
489 | #define PVOP_CALL1(rettype, op, arg1) \ | |
a4746364 | 490 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa | 491 | #define PVOP_VCALL1(op, arg1) \ |
a4746364 | 492 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa JF |
493 | |
494 | #define PVOP_CALL2(rettype, op, arg1, arg2) \ | |
a4746364 GOC |
495 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
496 | "1" ((unsigned long)(arg2))) | |
1a45b7aa | 497 | #define PVOP_VCALL2(op, arg1, arg2) \ |
a4746364 GOC |
498 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
499 | "1" ((unsigned long)(arg2))) | |
1a45b7aa JF |
500 | |
501 | #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \ | |
a4746364 GOC |
502 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
503 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 504 | #define PVOP_VCALL3(op, arg1, arg2, arg3) \ |
a4746364 GOC |
505 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
506 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 507 | |
a4746364 GOC |
508 | /* This is the only difference in x86_64. We can make it much simpler */ |
509 | #ifdef CONFIG_X86_32 | |
1a45b7aa JF |
510 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ |
511 | __PVOP_CALL(rettype, op, \ | |
512 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
513 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
514 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
515 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
516 | __PVOP_VCALL(op, \ | |
517 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
518 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
519 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
a4746364 GOC |
520 | #else |
521 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ | |
522 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ | |
523 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
524 | "3"((unsigned long)(arg4))) | |
525 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
526 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ | |
527 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
528 | "3"((unsigned long)(arg4))) | |
529 | #endif | |
1a45b7aa | 530 | |
f8822f42 JF |
531 | static inline int paravirt_enabled(void) |
532 | { | |
93b1eab3 | 533 | return pv_info.paravirt_enabled; |
f8822f42 | 534 | } |
d3561b7f | 535 | |
faca6227 | 536 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
537 | struct thread_struct *thread) |
538 | { | |
faca6227 | 539 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
540 | } |
541 | ||
93b1eab3 | 542 | #define ARCH_SETUP pv_init_ops.arch_setup(); |
d3561b7f RR |
543 | static inline unsigned long get_wallclock(void) |
544 | { | |
93b1eab3 | 545 | return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock); |
d3561b7f RR |
546 | } |
547 | ||
548 | static inline int set_wallclock(unsigned long nowtime) | |
549 | { | |
93b1eab3 | 550 | return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime); |
d3561b7f RR |
551 | } |
552 | ||
e30fab3a | 553 | static inline void (*choose_time_init(void))(void) |
d3561b7f | 554 | { |
93b1eab3 | 555 | return pv_time_ops.time_init; |
d3561b7f RR |
556 | } |
557 | ||
558 | /* The paravirtualized CPUID instruction. */ | |
559 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
560 | unsigned int *ecx, unsigned int *edx) | |
561 | { | |
93b1eab3 | 562 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
563 | } |
564 | ||
565 | /* | |
566 | * These special macros can be used to get or set a debugging register | |
567 | */ | |
f8822f42 JF |
568 | static inline unsigned long paravirt_get_debugreg(int reg) |
569 | { | |
93b1eab3 | 570 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
571 | } |
572 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
573 | static inline void set_debugreg(unsigned long val, int reg) | |
574 | { | |
93b1eab3 | 575 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 576 | } |
d3561b7f | 577 | |
f8822f42 JF |
578 | static inline void clts(void) |
579 | { | |
93b1eab3 | 580 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 581 | } |
d3561b7f | 582 | |
f8822f42 JF |
583 | static inline unsigned long read_cr0(void) |
584 | { | |
93b1eab3 | 585 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 586 | } |
d3561b7f | 587 | |
f8822f42 JF |
588 | static inline void write_cr0(unsigned long x) |
589 | { | |
93b1eab3 | 590 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
591 | } |
592 | ||
593 | static inline unsigned long read_cr2(void) | |
594 | { | |
93b1eab3 | 595 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
596 | } |
597 | ||
598 | static inline void write_cr2(unsigned long x) | |
599 | { | |
93b1eab3 | 600 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
601 | } |
602 | ||
603 | static inline unsigned long read_cr3(void) | |
604 | { | |
93b1eab3 | 605 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 606 | } |
d3561b7f | 607 | |
f8822f42 JF |
608 | static inline void write_cr3(unsigned long x) |
609 | { | |
93b1eab3 | 610 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 611 | } |
d3561b7f | 612 | |
f8822f42 JF |
613 | static inline unsigned long read_cr4(void) |
614 | { | |
93b1eab3 | 615 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 JF |
616 | } |
617 | static inline unsigned long read_cr4_safe(void) | |
618 | { | |
93b1eab3 | 619 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 620 | } |
d3561b7f | 621 | |
f8822f42 JF |
622 | static inline void write_cr4(unsigned long x) |
623 | { | |
93b1eab3 | 624 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 625 | } |
3dc494e8 | 626 | |
94ea03cd | 627 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
628 | static inline unsigned long read_cr8(void) |
629 | { | |
630 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
631 | } | |
632 | ||
633 | static inline void write_cr8(unsigned long x) | |
634 | { | |
635 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
636 | } | |
94ea03cd | 637 | #endif |
4c9890c2 | 638 | |
d3561b7f RR |
639 | static inline void raw_safe_halt(void) |
640 | { | |
93b1eab3 | 641 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
642 | } |
643 | ||
644 | static inline void halt(void) | |
645 | { | |
93b1eab3 | 646 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
f8822f42 JF |
647 | } |
648 | ||
649 | static inline void wbinvd(void) | |
650 | { | |
93b1eab3 | 651 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 652 | } |
d3561b7f | 653 | |
93b1eab3 | 654 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 655 | |
f8822f42 JF |
656 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
657 | { | |
93b1eab3 | 658 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 JF |
659 | } |
660 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) | |
661 | { | |
93b1eab3 | 662 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
663 | } |
664 | ||
90a0a06a | 665 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
49cd740b JP |
666 | #define rdmsr(msr, val1, val2) \ |
667 | do { \ | |
f8822f42 JF |
668 | int _err; \ |
669 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
670 | val1 = (u32)_l; \ | |
671 | val2 = _l >> 32; \ | |
49cd740b | 672 | } while (0) |
d3561b7f | 673 | |
49cd740b JP |
674 | #define wrmsr(msr, val1, val2) \ |
675 | do { \ | |
f8822f42 | 676 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 677 | } while (0) |
d3561b7f | 678 | |
49cd740b JP |
679 | #define rdmsrl(msr, val) \ |
680 | do { \ | |
f8822f42 JF |
681 | int _err; \ |
682 | val = paravirt_read_msr(msr, &_err); \ | |
49cd740b | 683 | } while (0) |
d3561b7f | 684 | |
49cd740b JP |
685 | #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) |
686 | #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b) | |
d3561b7f RR |
687 | |
688 | /* rdmsr with exception handling */ | |
49cd740b JP |
689 | #define rdmsr_safe(msr, a, b) \ |
690 | ({ \ | |
f8822f42 JF |
691 | int _err; \ |
692 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
693 | (*a) = (u32)_l; \ | |
694 | (*b) = _l >> 32; \ | |
49cd740b JP |
695 | _err; \ |
696 | }) | |
d3561b7f | 697 | |
1de87bd4 AK |
698 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
699 | { | |
700 | int err; | |
701 | ||
702 | *p = paravirt_read_msr(msr, &err); | |
703 | return err; | |
704 | } | |
f8822f42 JF |
705 | |
706 | static inline u64 paravirt_read_tsc(void) | |
707 | { | |
93b1eab3 | 708 | return PVOP_CALL0(u64, pv_cpu_ops.read_tsc); |
f8822f42 | 709 | } |
d3561b7f | 710 | |
49cd740b JP |
711 | #define rdtscl(low) \ |
712 | do { \ | |
f8822f42 JF |
713 | u64 _l = paravirt_read_tsc(); \ |
714 | low = (int)_l; \ | |
49cd740b | 715 | } while (0) |
d3561b7f | 716 | |
f8822f42 | 717 | #define rdtscll(val) (val = paravirt_read_tsc()) |
d3561b7f | 718 | |
688340ea JF |
719 | static inline unsigned long long paravirt_sched_clock(void) |
720 | { | |
93b1eab3 | 721 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 722 | } |
93b1eab3 | 723 | #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz()) |
6cb9a835 | 724 | |
f8822f42 JF |
725 | static inline unsigned long long paravirt_read_pmc(int counter) |
726 | { | |
93b1eab3 | 727 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 728 | } |
d3561b7f | 729 | |
49cd740b JP |
730 | #define rdpmc(counter, low, high) \ |
731 | do { \ | |
f8822f42 JF |
732 | u64 _l = paravirt_read_pmc(counter); \ |
733 | low = (u32)_l; \ | |
734 | high = _l >> 32; \ | |
49cd740b | 735 | } while (0) |
3dc494e8 | 736 | |
e5aaac44 GOC |
737 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) |
738 | { | |
739 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); | |
740 | } | |
741 | ||
742 | #define rdtscp(low, high, aux) \ | |
743 | do { \ | |
744 | int __aux; \ | |
745 | unsigned long __val = paravirt_rdtscp(&__aux); \ | |
746 | (low) = (u32)__val; \ | |
747 | (high) = (u32)(__val >> 32); \ | |
748 | (aux) = __aux; \ | |
749 | } while (0) | |
750 | ||
751 | #define rdtscpll(val, aux) \ | |
752 | do { \ | |
753 | unsigned long __aux; \ | |
754 | val = paravirt_rdtscp(&__aux); \ | |
755 | (aux) = __aux; \ | |
756 | } while (0) | |
757 | ||
f8822f42 JF |
758 | static inline void load_TR_desc(void) |
759 | { | |
93b1eab3 | 760 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 761 | } |
6b68f01b | 762 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 763 | { |
93b1eab3 | 764 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 765 | } |
6b68f01b | 766 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 767 | { |
93b1eab3 | 768 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
769 | } |
770 | static inline void set_ldt(const void *addr, unsigned entries) | |
771 | { | |
93b1eab3 | 772 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 773 | } |
6b68f01b | 774 | static inline void store_gdt(struct desc_ptr *dtr) |
f8822f42 | 775 | { |
93b1eab3 | 776 | PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr); |
f8822f42 | 777 | } |
6b68f01b | 778 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 779 | { |
93b1eab3 | 780 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
781 | } |
782 | static inline unsigned long paravirt_store_tr(void) | |
783 | { | |
93b1eab3 | 784 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
785 | } |
786 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
787 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
788 | { | |
93b1eab3 | 789 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 790 | } |
75b8bb3e GOC |
791 | |
792 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, | |
793 | const void *desc) | |
f8822f42 | 794 | { |
75b8bb3e | 795 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 796 | } |
014b15be GOC |
797 | |
798 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
799 | void *desc, int type) | |
f8822f42 | 800 | { |
014b15be | 801 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 802 | } |
014b15be | 803 | |
8d947344 | 804 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 805 | { |
8d947344 | 806 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
807 | } |
808 | static inline void set_iopl_mask(unsigned mask) | |
809 | { | |
93b1eab3 | 810 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 811 | } |
3dc494e8 | 812 | |
d3561b7f | 813 | /* The paravirtualized I/O functions */ |
49cd740b JP |
814 | static inline void slow_down_io(void) |
815 | { | |
93b1eab3 | 816 | pv_cpu_ops.io_delay(); |
d3561b7f | 817 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
818 | pv_cpu_ops.io_delay(); |
819 | pv_cpu_ops.io_delay(); | |
820 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
821 | #endif |
822 | } | |
823 | ||
13623d79 RR |
824 | #ifdef CONFIG_X86_LOCAL_APIC |
825 | /* | |
826 | * Basic functions accessing APICs. | |
827 | */ | |
42e0a9aa | 828 | static inline void apic_write(unsigned long reg, u32 v) |
13623d79 | 829 | { |
93b1eab3 | 830 | PVOP_VCALL2(pv_apic_ops.apic_write, reg, v); |
13623d79 RR |
831 | } |
832 | ||
42e0a9aa | 833 | static inline void apic_write_atomic(unsigned long reg, u32 v) |
13623d79 | 834 | { |
93b1eab3 | 835 | PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v); |
13623d79 RR |
836 | } |
837 | ||
42e0a9aa | 838 | static inline u32 apic_read(unsigned long reg) |
13623d79 | 839 | { |
93b1eab3 | 840 | return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg); |
13623d79 | 841 | } |
bbab4f3b ZA |
842 | |
843 | static inline void setup_boot_clock(void) | |
844 | { | |
93b1eab3 | 845 | PVOP_VCALL0(pv_apic_ops.setup_boot_clock); |
bbab4f3b ZA |
846 | } |
847 | ||
848 | static inline void setup_secondary_clock(void) | |
849 | { | |
93b1eab3 | 850 | PVOP_VCALL0(pv_apic_ops.setup_secondary_clock); |
bbab4f3b | 851 | } |
13623d79 RR |
852 | #endif |
853 | ||
6996d3b6 JF |
854 | static inline void paravirt_post_allocator_init(void) |
855 | { | |
93b1eab3 JF |
856 | if (pv_init_ops.post_allocator_init) |
857 | (*pv_init_ops.post_allocator_init)(); | |
6996d3b6 JF |
858 | } |
859 | ||
b239fb25 JF |
860 | static inline void paravirt_pagetable_setup_start(pgd_t *base) |
861 | { | |
93b1eab3 | 862 | (*pv_mmu_ops.pagetable_setup_start)(base); |
b239fb25 JF |
863 | } |
864 | ||
865 | static inline void paravirt_pagetable_setup_done(pgd_t *base) | |
866 | { | |
93b1eab3 | 867 | (*pv_mmu_ops.pagetable_setup_done)(base); |
b239fb25 | 868 | } |
3dc494e8 | 869 | |
ae5da273 ZA |
870 | #ifdef CONFIG_SMP |
871 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
872 | unsigned long start_esp) | |
873 | { | |
93b1eab3 JF |
874 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
875 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
876 | } |
877 | #endif | |
13623d79 | 878 | |
d6dd61c8 JF |
879 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
880 | struct mm_struct *next) | |
881 | { | |
93b1eab3 | 882 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
883 | } |
884 | ||
885 | static inline void arch_dup_mmap(struct mm_struct *oldmm, | |
886 | struct mm_struct *mm) | |
887 | { | |
93b1eab3 | 888 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
889 | } |
890 | ||
891 | static inline void arch_exit_mmap(struct mm_struct *mm) | |
892 | { | |
93b1eab3 | 893 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
894 | } |
895 | ||
f8822f42 JF |
896 | static inline void __flush_tlb(void) |
897 | { | |
93b1eab3 | 898 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
899 | } |
900 | static inline void __flush_tlb_global(void) | |
901 | { | |
93b1eab3 | 902 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
903 | } |
904 | static inline void __flush_tlb_single(unsigned long addr) | |
905 | { | |
93b1eab3 | 906 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 907 | } |
da181a8b | 908 | |
d4c10477 JF |
909 | static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, |
910 | unsigned long va) | |
911 | { | |
93b1eab3 | 912 | PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va); |
d4c10477 JF |
913 | } |
914 | ||
6944a9c8 | 915 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 916 | { |
6944a9c8 | 917 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 918 | } |
6944a9c8 | 919 | static inline void paravirt_release_pte(unsigned pfn) |
f8822f42 | 920 | { |
6944a9c8 | 921 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 922 | } |
c119ecce | 923 | |
6944a9c8 | 924 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 925 | { |
6944a9c8 | 926 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 927 | } |
c119ecce | 928 | |
6944a9c8 JF |
929 | static inline void paravirt_alloc_pmd_clone(unsigned pfn, unsigned clonepfn, |
930 | unsigned start, unsigned count) | |
f8822f42 | 931 | { |
6944a9c8 | 932 | PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count); |
f8822f42 | 933 | } |
6944a9c8 | 934 | static inline void paravirt_release_pmd(unsigned pfn) |
da181a8b | 935 | { |
6944a9c8 | 936 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
937 | } |
938 | ||
2761fa09 JF |
939 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned pfn) |
940 | { | |
941 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
942 | } | |
943 | static inline void paravirt_release_pud(unsigned pfn) | |
944 | { | |
945 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
946 | } | |
947 | ||
ce6234b5 JF |
948 | #ifdef CONFIG_HIGHPTE |
949 | static inline void *kmap_atomic_pte(struct page *page, enum km_type type) | |
950 | { | |
951 | unsigned long ret; | |
93b1eab3 | 952 | ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type); |
ce6234b5 JF |
953 | return (void *)ret; |
954 | } | |
955 | #endif | |
956 | ||
f8822f42 JF |
957 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
958 | pte_t *ptep) | |
da181a8b | 959 | { |
93b1eab3 | 960 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b RR |
961 | } |
962 | ||
f8822f42 JF |
963 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
964 | pte_t *ptep) | |
da181a8b | 965 | { |
93b1eab3 | 966 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
967 | } |
968 | ||
773221f4 | 969 | static inline pte_t __pte(pteval_t val) |
da181a8b | 970 | { |
773221f4 JF |
971 | pteval_t ret; |
972 | ||
973 | if (sizeof(pteval_t) > sizeof(long)) | |
974 | ret = PVOP_CALL2(pteval_t, | |
975 | pv_mmu_ops.make_pte, | |
976 | val, (u64)val >> 32); | |
977 | else | |
978 | ret = PVOP_CALL1(pteval_t, | |
979 | pv_mmu_ops.make_pte, | |
980 | val); | |
981 | ||
c8e5393a | 982 | return (pte_t) { .pte = ret }; |
da181a8b RR |
983 | } |
984 | ||
773221f4 JF |
985 | static inline pteval_t pte_val(pte_t pte) |
986 | { | |
987 | pteval_t ret; | |
988 | ||
989 | if (sizeof(pteval_t) > sizeof(long)) | |
990 | ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val, | |
991 | pte.pte, (u64)pte.pte >> 32); | |
992 | else | |
993 | ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val, | |
994 | pte.pte); | |
995 | ||
996 | return ret; | |
997 | } | |
998 | ||
ef38503e | 999 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 1000 | { |
ef38503e JF |
1001 | pgdval_t ret; |
1002 | ||
1003 | if (sizeof(pgdval_t) > sizeof(long)) | |
1004 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd, | |
1005 | val, (u64)val >> 32); | |
1006 | else | |
1007 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd, | |
1008 | val); | |
1009 | ||
1010 | return (pgd_t) { ret }; | |
1011 | } | |
1012 | ||
1013 | static inline pgdval_t pgd_val(pgd_t pgd) | |
1014 | { | |
1015 | pgdval_t ret; | |
1016 | ||
1017 | if (sizeof(pgdval_t) > sizeof(long)) | |
1018 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val, | |
1019 | pgd.pgd, (u64)pgd.pgd >> 32); | |
1020 | else | |
1021 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val, | |
1022 | pgd.pgd); | |
1023 | ||
1024 | return ret; | |
f8822f42 JF |
1025 | } |
1026 | ||
4eed80cd JF |
1027 | static inline void set_pte(pte_t *ptep, pte_t pte) |
1028 | { | |
1029 | if (sizeof(pteval_t) > sizeof(long)) | |
1030 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
1031 | pte.pte, (u64)pte.pte >> 32); | |
1032 | else | |
1033 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
1034 | pte.pte); | |
1035 | } | |
1036 | ||
1037 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1038 | pte_t *ptep, pte_t pte) | |
1039 | { | |
1040 | if (sizeof(pteval_t) > sizeof(long)) | |
1041 | /* 5 arg words */ | |
1042 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
1043 | else | |
1044 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
1045 | } | |
1046 | ||
60b3f626 JF |
1047 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
1048 | { | |
1049 | pmdval_t val = native_pmd_val(pmd); | |
1050 | ||
1051 | if (sizeof(pmdval_t) > sizeof(long)) | |
1052 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
1053 | else | |
1054 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
1055 | } | |
1056 | ||
1fe91514 GOC |
1057 | #if PAGETABLE_LEVELS >= 3 |
1058 | static inline pmd_t __pmd(pmdval_t val) | |
1059 | { | |
1060 | pmdval_t ret; | |
1061 | ||
1062 | if (sizeof(pmdval_t) > sizeof(long)) | |
1063 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd, | |
1064 | val, (u64)val >> 32); | |
1065 | else | |
1066 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd, | |
1067 | val); | |
1068 | ||
1069 | return (pmd_t) { ret }; | |
1070 | } | |
1071 | ||
1072 | static inline pmdval_t pmd_val(pmd_t pmd) | |
1073 | { | |
1074 | pmdval_t ret; | |
1075 | ||
1076 | if (sizeof(pmdval_t) > sizeof(long)) | |
1077 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val, | |
1078 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1079 | else | |
1080 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val, | |
1081 | pmd.pmd); | |
1082 | ||
1083 | return ret; | |
1084 | } | |
1085 | ||
1086 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
1087 | { | |
1088 | pudval_t val = native_pud_val(pud); | |
1089 | ||
1090 | if (sizeof(pudval_t) > sizeof(long)) | |
1091 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
1092 | val, (u64)val >> 32); | |
1093 | else | |
1094 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
1095 | val); | |
1096 | } | |
9042219c EH |
1097 | #if PAGETABLE_LEVELS == 4 |
1098 | static inline pud_t __pud(pudval_t val) | |
1099 | { | |
1100 | pudval_t ret; | |
1101 | ||
1102 | if (sizeof(pudval_t) > sizeof(long)) | |
1103 | ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud, | |
1104 | val, (u64)val >> 32); | |
1105 | else | |
1106 | ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud, | |
1107 | val); | |
1108 | ||
1109 | return (pud_t) { ret }; | |
1110 | } | |
1111 | ||
1112 | static inline pudval_t pud_val(pud_t pud) | |
1113 | { | |
1114 | pudval_t ret; | |
1115 | ||
1116 | if (sizeof(pudval_t) > sizeof(long)) | |
1117 | ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val, | |
1118 | pud.pud, (u64)pud.pud >> 32); | |
1119 | else | |
1120 | ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val, | |
1121 | pud.pud); | |
1122 | ||
1123 | return ret; | |
1124 | } | |
1125 | ||
1126 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
1127 | { | |
1128 | pgdval_t val = native_pgd_val(pgd); | |
1129 | ||
1130 | if (sizeof(pgdval_t) > sizeof(long)) | |
1131 | PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp, | |
1132 | val, (u64)val >> 32); | |
1133 | else | |
1134 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, | |
1135 | val); | |
1136 | } | |
1137 | ||
1138 | static inline void pgd_clear(pgd_t *pgdp) | |
1139 | { | |
1140 | set_pgd(pgdp, __pgd(0)); | |
1141 | } | |
1142 | ||
1143 | static inline void pud_clear(pud_t *pudp) | |
1144 | { | |
1145 | set_pud(pudp, __pud(0)); | |
1146 | } | |
1147 | ||
1148 | #endif /* PAGETABLE_LEVELS == 4 */ | |
1149 | ||
1fe91514 GOC |
1150 | #endif /* PAGETABLE_LEVELS >= 3 */ |
1151 | ||
4eed80cd JF |
1152 | #ifdef CONFIG_X86_PAE |
1153 | /* Special-case pte-setting operations for PAE, which can't update a | |
1154 | 64-bit pte atomically */ | |
1155 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1156 | { | |
1157 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
1158 | pte.pte, pte.pte >> 32); | |
1159 | } | |
1160 | ||
1161 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1162 | pte_t *ptep, pte_t pte) | |
1163 | { | |
1164 | /* 5 arg words */ | |
1165 | pv_mmu_ops.set_pte_present(mm, addr, ptep, pte); | |
1166 | } | |
1167 | ||
1168 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1169 | pte_t *ptep) | |
1170 | { | |
1171 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
1172 | } | |
60b3f626 JF |
1173 | |
1174 | static inline void pmd_clear(pmd_t *pmdp) | |
1175 | { | |
1176 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
1177 | } | |
4eed80cd JF |
1178 | #else /* !CONFIG_X86_PAE */ |
1179 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1180 | { | |
1181 | set_pte(ptep, pte); | |
1182 | } | |
1183 | ||
1184 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1185 | pte_t *ptep, pte_t pte) | |
1186 | { | |
1187 | set_pte(ptep, pte); | |
1188 | } | |
1189 | ||
1190 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1191 | pte_t *ptep) | |
1192 | { | |
1193 | set_pte_at(mm, addr, ptep, __pte(0)); | |
1194 | } | |
60b3f626 JF |
1195 | |
1196 | static inline void pmd_clear(pmd_t *pmdp) | |
1197 | { | |
1198 | set_pmd(pmdp, __pmd(0)); | |
1199 | } | |
4eed80cd JF |
1200 | #endif /* CONFIG_X86_PAE */ |
1201 | ||
8965c1c0 JF |
1202 | /* Lazy mode for batching updates / context switch */ |
1203 | enum paravirt_lazy_mode { | |
1204 | PARAVIRT_LAZY_NONE, | |
1205 | PARAVIRT_LAZY_MMU, | |
1206 | PARAVIRT_LAZY_CPU, | |
1207 | }; | |
1208 | ||
1209 | enum paravirt_lazy_mode paravirt_get_lazy_mode(void); | |
1210 | void paravirt_enter_lazy_cpu(void); | |
1211 | void paravirt_leave_lazy_cpu(void); | |
1212 | void paravirt_enter_lazy_mmu(void); | |
1213 | void paravirt_leave_lazy_mmu(void); | |
1214 | void paravirt_leave_lazy(enum paravirt_lazy_mode mode); | |
1215 | ||
9226d125 | 1216 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE |
f8822f42 JF |
1217 | static inline void arch_enter_lazy_cpu_mode(void) |
1218 | { | |
8965c1c0 | 1219 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter); |
f8822f42 JF |
1220 | } |
1221 | ||
1222 | static inline void arch_leave_lazy_cpu_mode(void) | |
1223 | { | |
8965c1c0 | 1224 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave); |
f8822f42 JF |
1225 | } |
1226 | ||
1227 | static inline void arch_flush_lazy_cpu_mode(void) | |
1228 | { | |
8965c1c0 JF |
1229 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) { |
1230 | arch_leave_lazy_cpu_mode(); | |
1231 | arch_enter_lazy_cpu_mode(); | |
1232 | } | |
f8822f42 JF |
1233 | } |
1234 | ||
9226d125 ZA |
1235 | |
1236 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
f8822f42 JF |
1237 | static inline void arch_enter_lazy_mmu_mode(void) |
1238 | { | |
8965c1c0 | 1239 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
1240 | } |
1241 | ||
1242 | static inline void arch_leave_lazy_mmu_mode(void) | |
1243 | { | |
8965c1c0 | 1244 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
1245 | } |
1246 | ||
1247 | static inline void arch_flush_lazy_mmu_mode(void) | |
1248 | { | |
8965c1c0 JF |
1249 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) { |
1250 | arch_leave_lazy_mmu_mode(); | |
1251 | arch_enter_lazy_mmu_mode(); | |
1252 | } | |
f8822f42 | 1253 | } |
9226d125 | 1254 | |
45876233 JF |
1255 | void _paravirt_nop(void); |
1256 | #define paravirt_nop ((void *)_paravirt_nop) | |
1257 | ||
139ec7c4 | 1258 | /* These all sit in the .parainstructions section to tell us what to patch. */ |
98de032b | 1259 | struct paravirt_patch_site { |
139ec7c4 RR |
1260 | u8 *instr; /* original instructions */ |
1261 | u8 instrtype; /* type of this instruction */ | |
1262 | u8 len; /* length of original instruction */ | |
1263 | u16 clobbers; /* what registers you may clobber */ | |
1264 | }; | |
1265 | ||
98de032b JF |
1266 | extern struct paravirt_patch_site __parainstructions[], |
1267 | __parainstructions_end[]; | |
1268 | ||
2e47d3e6 GOC |
1269 | #ifdef CONFIG_X86_32 |
1270 | #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;" | |
1271 | #define PV_RESTORE_REGS "popl %%edx; popl %%ecx" | |
1272 | #define PV_FLAGS_ARG "0" | |
1273 | #define PV_EXTRA_CLOBBERS | |
1274 | #define PV_VEXTRA_CLOBBERS | |
1275 | #else | |
1276 | /* We save some registers, but all of them, that's too much. We clobber all | |
1277 | * caller saved registers but the argument parameter */ | |
1278 | #define PV_SAVE_REGS "pushq %%rdi;" | |
1279 | #define PV_RESTORE_REGS "popq %%rdi;" | |
1280 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx" | |
1281 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx" | |
1282 | #define PV_FLAGS_ARG "D" | |
1283 | #endif | |
1284 | ||
139ec7c4 RR |
1285 | static inline unsigned long __raw_local_save_flags(void) |
1286 | { | |
1287 | unsigned long f; | |
1288 | ||
2e47d3e6 | 1289 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1290 | PARAVIRT_CALL |
2e47d3e6 | 1291 | PV_RESTORE_REGS) |
d5822035 | 1292 | : "=a"(f) |
93b1eab3 | 1293 | : paravirt_type(pv_irq_ops.save_fl), |
42c24fa2 | 1294 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1295 | : "memory", "cc" PV_VEXTRA_CLOBBERS); |
139ec7c4 RR |
1296 | return f; |
1297 | } | |
1298 | ||
1299 | static inline void raw_local_irq_restore(unsigned long f) | |
1300 | { | |
2e47d3e6 | 1301 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1302 | PARAVIRT_CALL |
2e47d3e6 | 1303 | PV_RESTORE_REGS) |
d5822035 | 1304 | : "=a"(f) |
2e47d3e6 | 1305 | : PV_FLAGS_ARG(f), |
93b1eab3 | 1306 | paravirt_type(pv_irq_ops.restore_fl), |
d5822035 | 1307 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1308 | : "memory", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1309 | } |
1310 | ||
1311 | static inline void raw_local_irq_disable(void) | |
1312 | { | |
2e47d3e6 | 1313 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1314 | PARAVIRT_CALL |
2e47d3e6 | 1315 | PV_RESTORE_REGS) |
d5822035 | 1316 | : |
93b1eab3 | 1317 | : paravirt_type(pv_irq_ops.irq_disable), |
d5822035 | 1318 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1319 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1320 | } |
1321 | ||
1322 | static inline void raw_local_irq_enable(void) | |
1323 | { | |
2e47d3e6 | 1324 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1325 | PARAVIRT_CALL |
2e47d3e6 | 1326 | PV_RESTORE_REGS) |
d5822035 | 1327 | : |
93b1eab3 | 1328 | : paravirt_type(pv_irq_ops.irq_enable), |
d5822035 | 1329 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1330 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1331 | } |
1332 | ||
1333 | static inline unsigned long __raw_local_irq_save(void) | |
1334 | { | |
1335 | unsigned long f; | |
1336 | ||
d5822035 JF |
1337 | f = __raw_local_save_flags(); |
1338 | raw_local_irq_disable(); | |
139ec7c4 RR |
1339 | return f; |
1340 | } | |
1341 | ||
294688c0 | 1342 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 1343 | #undef PARAVIRT_CALL |
1a45b7aa JF |
1344 | #undef __PVOP_CALL |
1345 | #undef __PVOP_VCALL | |
f8822f42 JF |
1346 | #undef PVOP_VCALL0 |
1347 | #undef PVOP_CALL0 | |
1348 | #undef PVOP_VCALL1 | |
1349 | #undef PVOP_CALL1 | |
1350 | #undef PVOP_VCALL2 | |
1351 | #undef PVOP_CALL2 | |
1352 | #undef PVOP_VCALL3 | |
1353 | #undef PVOP_CALL3 | |
1354 | #undef PVOP_VCALL4 | |
1355 | #undef PVOP_CALL4 | |
139ec7c4 | 1356 | |
d3561b7f RR |
1357 | #else /* __ASSEMBLY__ */ |
1358 | ||
658be9d3 | 1359 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
1360 | 771:; \ |
1361 | ops; \ | |
1362 | 772:; \ | |
1363 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
1364 | .align algn; \ |
1365 | word 771b; \ | |
139ec7c4 RR |
1366 | .byte ptype; \ |
1367 | .byte 772b-771b; \ | |
1368 | .short clobbers; \ | |
1369 | .popsection | |
1370 | ||
658be9d3 GOC |
1371 | |
1372 | #ifdef CONFIG_X86_64 | |
6057fc82 GOC |
1373 | #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx |
1374 | #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax | |
1375 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) | |
658be9d3 GOC |
1376 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
1377 | #else | |
6057fc82 GOC |
1378 | #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx |
1379 | #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax | |
1380 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) | |
658be9d3 GOC |
1381 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
1382 | #endif | |
1383 | ||
93b1eab3 JF |
1384 | #define INTERRUPT_RETURN \ |
1385 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
1386 | jmp *%cs:pv_cpu_ops+PV_CPU_iret) | |
d5822035 JF |
1387 | |
1388 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1389 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
6057fc82 | 1390 | PV_SAVE_REGS; \ |
93b1eab3 | 1391 | call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \ |
6057fc82 | 1392 | PV_RESTORE_REGS;) \ |
d5822035 JF |
1393 | |
1394 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1395 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
6057fc82 | 1396 | PV_SAVE_REGS; \ |
93b1eab3 | 1397 | call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \ |
6057fc82 | 1398 | PV_RESTORE_REGS;) |
d5822035 | 1399 | |
6abcd98f GOC |
1400 | #define ENABLE_INTERRUPTS_SYSCALL_RET \ |
1401 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\ | |
1402 | CLBR_NONE, \ | |
1403 | jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret) | |
139ec7c4 | 1404 | |
2e47d3e6 | 1405 | |
6057fc82 | 1406 | #ifdef CONFIG_X86_32 |
139ec7c4 | 1407 | #define GET_CR0_INTO_EAX \ |
42c24fa2 | 1408 | push %ecx; push %edx; \ |
93b1eab3 | 1409 | call *pv_cpu_ops+PV_CPU_read_cr0; \ |
42c24fa2 | 1410 | pop %edx; pop %ecx |
4a8c4c4e | 1411 | #else |
e801f864 GOC |
1412 | #define SWAPGS \ |
1413 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
1414 | PV_SAVE_REGS; \ | |
1415 | call *pv_cpu_ops+PV_CPU_swapgs; \ | |
1416 | PV_RESTORE_REGS \ | |
1417 | ) | |
1418 | ||
4a8c4c4e GOC |
1419 | #define GET_CR2_INTO_RCX \ |
1420 | call *pv_mmu_ops+PV_MMU_read_cr2; \ | |
1421 | movq %rax, %rcx; \ | |
1422 | xorq %rax, %rax; | |
1423 | ||
6057fc82 | 1424 | #endif |
139ec7c4 | 1425 | |
d3561b7f RR |
1426 | #endif /* __ASSEMBLY__ */ |
1427 | #endif /* CONFIG_PARAVIRT */ | |
1428 | #endif /* __ASM_PARAVIRT_H */ |