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d3561b7f RR |
1 | #ifndef __ASM_PARAVIRT_H |
2 | #define __ASM_PARAVIRT_H | |
3 | /* Various instructions on x86 need to be replaced for | |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
da181a8b | 7 | #include <asm/page.h> |
d3561b7f | 8 | |
139ec7c4 RR |
9 | /* Bitmask of what can be clobbered: usually at least eax. */ |
10 | #define CLBR_NONE 0x0 | |
11 | #define CLBR_EAX 0x1 | |
12 | #define CLBR_ECX 0x2 | |
13 | #define CLBR_EDX 0x4 | |
14 | #define CLBR_ANY 0x7 | |
15 | ||
d3561b7f | 16 | #ifndef __ASSEMBLY__ |
3dc494e8 | 17 | #include <linux/types.h> |
d4c10477 | 18 | #include <linux/cpumask.h> |
ce6234b5 | 19 | #include <asm/kmap_types.h> |
3dc494e8 | 20 | |
ce6234b5 | 21 | struct page; |
d3561b7f RR |
22 | struct thread_struct; |
23 | struct Xgt_desc_struct; | |
24 | struct tss_struct; | |
da181a8b | 25 | struct mm_struct; |
90a0a06a | 26 | struct desc_struct; |
294688c0 JF |
27 | |
28 | /* Lazy mode for batching updates / context switch */ | |
29 | enum paravirt_lazy_mode { | |
30 | PARAVIRT_LAZY_NONE = 0, | |
31 | PARAVIRT_LAZY_MMU = 1, | |
32 | PARAVIRT_LAZY_CPU = 2, | |
4e0fa856 | 33 | PARAVIRT_LAZY_FLUSH = 3, |
294688c0 JF |
34 | }; |
35 | ||
93b1eab3 JF |
36 | |
37 | /* general info */ | |
38 | struct pv_info { | |
d3561b7f | 39 | unsigned int kernel_rpl; |
5311ab62 | 40 | int shared_kernel_pmd; |
93b1eab3 | 41 | int paravirt_enabled; |
d3561b7f | 42 | const char *name; |
93b1eab3 | 43 | }; |
d3561b7f | 44 | |
93b1eab3 | 45 | struct pv_init_ops { |
139ec7c4 | 46 | /* |
93b1eab3 JF |
47 | * Patch may replace one of the defined code sequences with |
48 | * arbitrary code, subject to the same register constraints. | |
49 | * This generally means the code is not free to clobber any | |
50 | * registers other than EAX. The patch function should return | |
51 | * the number of bytes of code generated, as we nop pad the | |
52 | * rest in generic code. | |
139ec7c4 | 53 | */ |
ab144f5e AK |
54 | unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, |
55 | unsigned long addr, unsigned len); | |
139ec7c4 | 56 | |
294688c0 | 57 | /* Basic arch-specific setup */ |
d3561b7f RR |
58 | void (*arch_setup)(void); |
59 | char *(*memory_setup)(void); | |
6996d3b6 JF |
60 | void (*post_allocator_init)(void); |
61 | ||
294688c0 | 62 | /* Print a banner to identify the environment */ |
d3561b7f | 63 | void (*banner)(void); |
93b1eab3 JF |
64 | }; |
65 | ||
66 | ||
67 | struct pv_misc_ops { | |
68 | /* Set deferred update mode, used for batching operations. */ | |
69 | void (*set_lazy_mode)(enum paravirt_lazy_mode mode); | |
70 | }; | |
71 | ||
72 | struct pv_time_ops { | |
73 | void (*time_init)(void); | |
d3561b7f | 74 | |
294688c0 | 75 | /* Set and set time of day */ |
d3561b7f RR |
76 | unsigned long (*get_wallclock)(void); |
77 | int (*set_wallclock)(unsigned long); | |
d3561b7f | 78 | |
93b1eab3 JF |
79 | unsigned long long (*sched_clock)(void); |
80 | unsigned long (*get_cpu_khz)(void); | |
81 | }; | |
d3561b7f | 82 | |
93b1eab3 | 83 | struct pv_cpu_ops { |
294688c0 | 84 | /* hooks for various privileged instructions */ |
1a1eecd1 AK |
85 | unsigned long (*get_debugreg)(int regno); |
86 | void (*set_debugreg)(int regno, unsigned long value); | |
d3561b7f | 87 | |
1a1eecd1 | 88 | void (*clts)(void); |
d3561b7f | 89 | |
1a1eecd1 AK |
90 | unsigned long (*read_cr0)(void); |
91 | void (*write_cr0)(unsigned long); | |
d3561b7f | 92 | |
1a1eecd1 AK |
93 | unsigned long (*read_cr4_safe)(void); |
94 | unsigned long (*read_cr4)(void); | |
95 | void (*write_cr4)(unsigned long); | |
d3561b7f | 96 | |
294688c0 | 97 | /* Segment descriptor handling */ |
1a1eecd1 AK |
98 | void (*load_tr_desc)(void); |
99 | void (*load_gdt)(const struct Xgt_desc_struct *); | |
100 | void (*load_idt)(const struct Xgt_desc_struct *); | |
101 | void (*store_gdt)(struct Xgt_desc_struct *); | |
102 | void (*store_idt)(struct Xgt_desc_struct *); | |
103 | void (*set_ldt)(const void *desc, unsigned entries); | |
104 | unsigned long (*store_tr)(void); | |
105 | void (*load_tls)(struct thread_struct *t, unsigned int cpu); | |
90a0a06a RR |
106 | void (*write_ldt_entry)(struct desc_struct *, |
107 | int entrynum, u32 low, u32 high); | |
108 | void (*write_gdt_entry)(struct desc_struct *, | |
109 | int entrynum, u32 low, u32 high); | |
110 | void (*write_idt_entry)(struct desc_struct *, | |
111 | int entrynum, u32 low, u32 high); | |
112 | void (*load_esp0)(struct tss_struct *tss, struct thread_struct *t); | |
d3561b7f | 113 | |
1a1eecd1 | 114 | void (*set_iopl_mask)(unsigned mask); |
93b1eab3 JF |
115 | |
116 | void (*wbinvd)(void); | |
1a1eecd1 | 117 | void (*io_delay)(void); |
d3561b7f | 118 | |
93b1eab3 JF |
119 | /* cpuid emulation, mostly so that caps bits can be disabled */ |
120 | void (*cpuid)(unsigned int *eax, unsigned int *ebx, | |
121 | unsigned int *ecx, unsigned int *edx); | |
122 | ||
123 | /* MSR, PMC and TSR operations. | |
124 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ | |
125 | u64 (*read_msr)(unsigned int msr, int *err); | |
126 | int (*write_msr)(unsigned int msr, u64 val); | |
127 | ||
128 | u64 (*read_tsc)(void); | |
129 | u64 (*read_pmc)(void); | |
130 | ||
131 | /* These two are jmp to, not actually called. */ | |
132 | void (*irq_enable_sysexit)(void); | |
133 | void (*iret)(void); | |
134 | }; | |
135 | ||
136 | struct pv_irq_ops { | |
137 | void (*init_IRQ)(void); | |
138 | ||
294688c0 | 139 | /* |
93b1eab3 JF |
140 | * Get/set interrupt state. save_fl and restore_fl are only |
141 | * expected to use X86_EFLAGS_IF; all other bits | |
142 | * returned from save_fl are undefined, and may be ignored by | |
143 | * restore_fl. | |
294688c0 | 144 | */ |
93b1eab3 JF |
145 | unsigned long (*save_fl)(void); |
146 | void (*restore_fl)(unsigned long); | |
147 | void (*irq_disable)(void); | |
148 | void (*irq_enable)(void); | |
149 | void (*safe_halt)(void); | |
150 | void (*halt)(void); | |
151 | }; | |
d6dd61c8 | 152 | |
93b1eab3 | 153 | struct pv_apic_ops { |
13623d79 | 154 | #ifdef CONFIG_X86_LOCAL_APIC |
294688c0 JF |
155 | /* |
156 | * Direct APIC operations, principally for VMI. Ideally | |
157 | * these shouldn't be in this interface. | |
158 | */ | |
1a1eecd1 AK |
159 | void (*apic_write)(unsigned long reg, unsigned long v); |
160 | void (*apic_write_atomic)(unsigned long reg, unsigned long v); | |
161 | unsigned long (*apic_read)(unsigned long reg); | |
bbab4f3b ZA |
162 | void (*setup_boot_clock)(void); |
163 | void (*setup_secondary_clock)(void); | |
294688c0 JF |
164 | |
165 | void (*startup_ipi_hook)(int phys_apicid, | |
166 | unsigned long start_eip, | |
167 | unsigned long start_esp); | |
13623d79 | 168 | #endif |
93b1eab3 JF |
169 | }; |
170 | ||
171 | struct pv_mmu_ops { | |
172 | /* | |
173 | * Called before/after init_mm pagetable setup. setup_start | |
174 | * may reset %cr3, and may pre-install parts of the pagetable; | |
175 | * pagetable setup is expected to preserve any existing | |
176 | * mapping. | |
177 | */ | |
178 | void (*pagetable_setup_start)(pgd_t *pgd_base); | |
179 | void (*pagetable_setup_done)(pgd_t *pgd_base); | |
180 | ||
181 | unsigned long (*read_cr2)(void); | |
182 | void (*write_cr2)(unsigned long); | |
183 | ||
184 | unsigned long (*read_cr3)(void); | |
185 | void (*write_cr3)(unsigned long); | |
186 | ||
187 | /* | |
188 | * Hooks for intercepting the creation/use/destruction of an | |
189 | * mm_struct. | |
190 | */ | |
191 | void (*activate_mm)(struct mm_struct *prev, | |
192 | struct mm_struct *next); | |
193 | void (*dup_mmap)(struct mm_struct *oldmm, | |
194 | struct mm_struct *mm); | |
195 | void (*exit_mmap)(struct mm_struct *mm); | |
196 | ||
13623d79 | 197 | |
294688c0 | 198 | /* TLB operations */ |
1a1eecd1 AK |
199 | void (*flush_tlb_user)(void); |
200 | void (*flush_tlb_kernel)(void); | |
f8822f42 | 201 | void (*flush_tlb_single)(unsigned long addr); |
d4c10477 JF |
202 | void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm, |
203 | unsigned long va); | |
1a1eecd1 | 204 | |
294688c0 | 205 | /* Hooks for allocating/releasing pagetable pages */ |
fdb4c338 | 206 | void (*alloc_pt)(struct mm_struct *mm, u32 pfn); |
1a1eecd1 AK |
207 | void (*alloc_pd)(u32 pfn); |
208 | void (*alloc_pd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); | |
209 | void (*release_pt)(u32 pfn); | |
210 | void (*release_pd)(u32 pfn); | |
211 | ||
294688c0 | 212 | /* Pagetable manipulation functions */ |
1a1eecd1 | 213 | void (*set_pte)(pte_t *ptep, pte_t pteval); |
294688c0 JF |
214 | void (*set_pte_at)(struct mm_struct *mm, unsigned long addr, |
215 | pte_t *ptep, pte_t pteval); | |
1a1eecd1 | 216 | void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval); |
3dc494e8 | 217 | void (*pte_update)(struct mm_struct *mm, unsigned long addr, pte_t *ptep); |
294688c0 JF |
218 | void (*pte_update_defer)(struct mm_struct *mm, |
219 | unsigned long addr, pte_t *ptep); | |
3dc494e8 | 220 | |
da181a8b | 221 | #ifdef CONFIG_X86_PAE |
1a1eecd1 | 222 | void (*set_pte_atomic)(pte_t *ptep, pte_t pteval); |
93b1eab3 JF |
223 | void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, |
224 | pte_t *ptep, pte_t pte); | |
1a1eecd1 | 225 | void (*set_pud)(pud_t *pudp, pud_t pudval); |
93b1eab3 | 226 | void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep); |
1a1eecd1 | 227 | void (*pmd_clear)(pmd_t *pmdp); |
3dc494e8 JF |
228 | |
229 | unsigned long long (*pte_val)(pte_t); | |
230 | unsigned long long (*pmd_val)(pmd_t); | |
231 | unsigned long long (*pgd_val)(pgd_t); | |
232 | ||
233 | pte_t (*make_pte)(unsigned long long pte); | |
234 | pmd_t (*make_pmd)(unsigned long long pmd); | |
235 | pgd_t (*make_pgd)(unsigned long long pgd); | |
236 | #else | |
237 | unsigned long (*pte_val)(pte_t); | |
238 | unsigned long (*pgd_val)(pgd_t); | |
239 | ||
240 | pte_t (*make_pte)(unsigned long pte); | |
241 | pgd_t (*make_pgd)(unsigned long pgd); | |
da181a8b RR |
242 | #endif |
243 | ||
93b1eab3 JF |
244 | #ifdef CONFIG_HIGHPTE |
245 | void *(*kmap_atomic_pte)(struct page *page, enum km_type type); | |
246 | #endif | |
247 | }; | |
9226d125 | 248 | |
93b1eab3 JF |
249 | /* This contains all the paravirt structures: we get a convenient |
250 | * number for each function using the offset which we use to indicate | |
251 | * what to patch. */ | |
252 | struct paravirt_patch_template | |
253 | { | |
254 | struct pv_init_ops pv_init_ops; | |
255 | struct pv_misc_ops pv_misc_ops; | |
256 | struct pv_time_ops pv_time_ops; | |
257 | struct pv_cpu_ops pv_cpu_ops; | |
258 | struct pv_irq_ops pv_irq_ops; | |
259 | struct pv_apic_ops pv_apic_ops; | |
260 | struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f RR |
261 | }; |
262 | ||
93b1eab3 JF |
263 | extern struct pv_info pv_info; |
264 | extern struct pv_init_ops pv_init_ops; | |
265 | extern struct pv_misc_ops pv_misc_ops; | |
266 | extern struct pv_time_ops pv_time_ops; | |
267 | extern struct pv_cpu_ops pv_cpu_ops; | |
268 | extern struct pv_irq_ops pv_irq_ops; | |
269 | extern struct pv_apic_ops pv_apic_ops; | |
270 | extern struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f | 271 | |
d5822035 | 272 | #define PARAVIRT_PATCH(x) \ |
93b1eab3 | 273 | (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) |
d5822035 | 274 | |
93b1eab3 JF |
275 | #define paravirt_type(op) \ |
276 | [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ | |
277 | [paravirt_opptr] "m" (op) | |
d5822035 JF |
278 | #define paravirt_clobber(clobber) \ |
279 | [paravirt_clobber] "i" (clobber) | |
280 | ||
294688c0 JF |
281 | /* |
282 | * Generate some code, and mark it as patchable by the | |
283 | * apply_paravirt() alternate instruction patcher. | |
284 | */ | |
d5822035 JF |
285 | #define _paravirt_alt(insn_string, type, clobber) \ |
286 | "771:\n\t" insn_string "\n" "772:\n" \ | |
287 | ".pushsection .parainstructions,\"a\"\n" \ | |
288 | " .long 771b\n" \ | |
289 | " .byte " type "\n" \ | |
290 | " .byte 772b-771b\n" \ | |
291 | " .short " clobber "\n" \ | |
292 | ".popsection\n" | |
293 | ||
294688c0 | 294 | /* Generate patchable code, with the default asm parameters. */ |
f8822f42 | 295 | #define paravirt_alt(insn_string) \ |
d5822035 JF |
296 | _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]") |
297 | ||
63f70270 JF |
298 | unsigned paravirt_patch_nop(void); |
299 | unsigned paravirt_patch_ignore(unsigned len); | |
ab144f5e AK |
300 | unsigned paravirt_patch_call(void *insnbuf, |
301 | const void *target, u16 tgt_clobbers, | |
302 | unsigned long addr, u16 site_clobbers, | |
63f70270 | 303 | unsigned len); |
93b1eab3 | 304 | unsigned paravirt_patch_jmp(void *insnbuf, const void *target, |
ab144f5e AK |
305 | unsigned long addr, unsigned len); |
306 | unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf, | |
307 | unsigned long addr, unsigned len); | |
63f70270 | 308 | |
ab144f5e | 309 | unsigned paravirt_patch_insns(void *insnbuf, unsigned len, |
63f70270 JF |
310 | const char *start, const char *end); |
311 | ||
d572929c | 312 | int paravirt_disable_iospace(void); |
63f70270 | 313 | |
294688c0 JF |
314 | /* |
315 | * This generates an indirect call based on the operation type number. | |
316 | * The type number, computed in PARAVIRT_PATCH, is derived from the | |
93b1eab3 JF |
317 | * offset into the paravirt_patch_template structure, and can therefore be |
318 | * freely converted back into a structure offset. | |
294688c0 | 319 | */ |
93b1eab3 | 320 | #define PARAVIRT_CALL "call *%[paravirt_opptr];" |
294688c0 JF |
321 | |
322 | /* | |
93b1eab3 JF |
323 | * These macros are intended to wrap calls through one of the paravirt |
324 | * ops structs, so that they can be later identified and patched at | |
294688c0 JF |
325 | * runtime. |
326 | * | |
327 | * Normally, a call to a pv_op function is a simple indirect call: | |
328 | * (paravirt_ops.operations)(args...). | |
329 | * | |
330 | * Unfortunately, this is a relatively slow operation for modern CPUs, | |
331 | * because it cannot necessarily determine what the destination | |
332 | * address is. In this case, the address is a runtime constant, so at | |
333 | * the very least we can patch the call to e a simple direct call, or | |
334 | * ideally, patch an inline implementation into the callsite. (Direct | |
335 | * calls are essentially free, because the call and return addresses | |
336 | * are completely predictable.) | |
337 | * | |
338 | * These macros rely on the standard gcc "regparm(3)" calling | |
339 | * convention, in which the first three arguments are placed in %eax, | |
340 | * %edx, %ecx (in that order), and the remaining arguments are placed | |
341 | * on the stack. All caller-save registers (eax,edx,ecx) are expected | |
342 | * to be modified (either clobbered or used for return values). | |
343 | * | |
344 | * The call instruction itself is marked by placing its start address | |
345 | * and size into the .parainstructions section, so that | |
346 | * apply_paravirt() in arch/i386/kernel/alternative.c can do the | |
93b1eab3 | 347 | * appropriate patching under the control of the backend pv_init_ops |
294688c0 JF |
348 | * implementation. |
349 | * | |
350 | * Unfortunately there's no way to get gcc to generate the args setup | |
351 | * for the call, and then allow the call itself to be generated by an | |
352 | * inline asm. Because of this, we must do the complete arg setup and | |
353 | * return value handling from within these macros. This is fairly | |
354 | * cumbersome. | |
355 | * | |
356 | * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments. | |
357 | * It could be extended to more arguments, but there would be little | |
358 | * to be gained from that. For each number of arguments, there are | |
359 | * the two VCALL and CALL variants for void and non-void functions. | |
360 | * | |
361 | * When there is a return value, the invoker of the macro must specify | |
362 | * the return type. The macro then uses sizeof() on that type to | |
363 | * determine whether its a 32 or 64 bit value, and places the return | |
364 | * in the right register(s) (just %eax for 32-bit, and %edx:%eax for | |
365 | * 64-bit). | |
366 | * | |
367 | * 64-bit arguments are passed as a pair of adjacent 32-bit arguments | |
368 | * in low,high order. | |
369 | * | |
370 | * Small structures are passed and returned in registers. The macro | |
371 | * calling convention can't directly deal with this, so the wrapper | |
372 | * functions must do this. | |
373 | * | |
374 | * These PVOP_* macros are only defined within this header. This | |
375 | * means that all uses must be wrapped in inline functions. This also | |
376 | * makes sure the incoming and outgoing types are always correct. | |
377 | */ | |
1a45b7aa | 378 | #define __PVOP_CALL(rettype, op, pre, post, ...) \ |
f8822f42 | 379 | ({ \ |
1a45b7aa | 380 | rettype __ret; \ |
f8822f42 | 381 | unsigned long __eax, __edx, __ecx; \ |
1a45b7aa JF |
382 | if (sizeof(rettype) > sizeof(unsigned long)) { \ |
383 | asm volatile(pre \ | |
384 | paravirt_alt(PARAVIRT_CALL) \ | |
385 | post \ | |
386 | : "=a" (__eax), "=d" (__edx), \ | |
f8822f42 | 387 | "=c" (__ecx) \ |
1a45b7aa JF |
388 | : paravirt_type(op), \ |
389 | paravirt_clobber(CLBR_ANY), \ | |
390 | ##__VA_ARGS__ \ | |
f8822f42 | 391 | : "memory", "cc"); \ |
1a45b7aa | 392 | __ret = (rettype)((((u64)__edx) << 32) | __eax); \ |
f8822f42 | 393 | } else { \ |
1a45b7aa | 394 | asm volatile(pre \ |
f8822f42 | 395 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa JF |
396 | post \ |
397 | : "=a" (__eax), "=d" (__edx), \ | |
398 | "=c" (__ecx) \ | |
399 | : paravirt_type(op), \ | |
400 | paravirt_clobber(CLBR_ANY), \ | |
401 | ##__VA_ARGS__ \ | |
f8822f42 | 402 | : "memory", "cc"); \ |
1a45b7aa | 403 | __ret = (rettype)__eax; \ |
f8822f42 JF |
404 | } \ |
405 | __ret; \ | |
406 | }) | |
1a45b7aa | 407 | #define __PVOP_VCALL(op, pre, post, ...) \ |
f8822f42 JF |
408 | ({ \ |
409 | unsigned long __eax, __edx, __ecx; \ | |
1a45b7aa | 410 | asm volatile(pre \ |
f8822f42 | 411 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 412 | post \ |
f8822f42 | 413 | : "=a" (__eax), "=d" (__edx), "=c" (__ecx) \ |
1a45b7aa JF |
414 | : paravirt_type(op), \ |
415 | paravirt_clobber(CLBR_ANY), \ | |
416 | ##__VA_ARGS__ \ | |
f8822f42 JF |
417 | : "memory", "cc"); \ |
418 | }) | |
419 | ||
1a45b7aa JF |
420 | #define PVOP_CALL0(rettype, op) \ |
421 | __PVOP_CALL(rettype, op, "", "") | |
422 | #define PVOP_VCALL0(op) \ | |
423 | __PVOP_VCALL(op, "", "") | |
424 | ||
425 | #define PVOP_CALL1(rettype, op, arg1) \ | |
426 | __PVOP_CALL(rettype, op, "", "", "0" ((u32)(arg1))) | |
427 | #define PVOP_VCALL1(op, arg1) \ | |
428 | __PVOP_VCALL(op, "", "", "0" ((u32)(arg1))) | |
429 | ||
430 | #define PVOP_CALL2(rettype, op, arg1, arg2) \ | |
431 | __PVOP_CALL(rettype, op, "", "", "0" ((u32)(arg1)), "1" ((u32)(arg2))) | |
432 | #define PVOP_VCALL2(op, arg1, arg2) \ | |
433 | __PVOP_VCALL(op, "", "", "0" ((u32)(arg1)), "1" ((u32)(arg2))) | |
434 | ||
435 | #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \ | |
436 | __PVOP_CALL(rettype, op, "", "", "0" ((u32)(arg1)), \ | |
437 | "1"((u32)(arg2)), "2"((u32)(arg3))) | |
438 | #define PVOP_VCALL3(op, arg1, arg2, arg3) \ | |
439 | __PVOP_VCALL(op, "", "", "0" ((u32)(arg1)), "1"((u32)(arg2)), \ | |
440 | "2"((u32)(arg3))) | |
441 | ||
442 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ | |
443 | __PVOP_CALL(rettype, op, \ | |
444 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
445 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
446 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
447 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
448 | __PVOP_VCALL(op, \ | |
449 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
450 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
451 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
452 | ||
f8822f42 JF |
453 | static inline int paravirt_enabled(void) |
454 | { | |
93b1eab3 | 455 | return pv_info.paravirt_enabled; |
f8822f42 | 456 | } |
d3561b7f RR |
457 | |
458 | static inline void load_esp0(struct tss_struct *tss, | |
459 | struct thread_struct *thread) | |
460 | { | |
93b1eab3 | 461 | PVOP_VCALL2(pv_cpu_ops.load_esp0, tss, thread); |
d3561b7f RR |
462 | } |
463 | ||
93b1eab3 | 464 | #define ARCH_SETUP pv_init_ops.arch_setup(); |
d3561b7f RR |
465 | static inline unsigned long get_wallclock(void) |
466 | { | |
93b1eab3 | 467 | return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock); |
d3561b7f RR |
468 | } |
469 | ||
470 | static inline int set_wallclock(unsigned long nowtime) | |
471 | { | |
93b1eab3 | 472 | return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime); |
d3561b7f RR |
473 | } |
474 | ||
e30fab3a | 475 | static inline void (*choose_time_init(void))(void) |
d3561b7f | 476 | { |
93b1eab3 | 477 | return pv_time_ops.time_init; |
d3561b7f RR |
478 | } |
479 | ||
480 | /* The paravirtualized CPUID instruction. */ | |
481 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
482 | unsigned int *ecx, unsigned int *edx) | |
483 | { | |
93b1eab3 | 484 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
485 | } |
486 | ||
487 | /* | |
488 | * These special macros can be used to get or set a debugging register | |
489 | */ | |
f8822f42 JF |
490 | static inline unsigned long paravirt_get_debugreg(int reg) |
491 | { | |
93b1eab3 | 492 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
493 | } |
494 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
495 | static inline void set_debugreg(unsigned long val, int reg) | |
496 | { | |
93b1eab3 | 497 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 498 | } |
d3561b7f | 499 | |
f8822f42 JF |
500 | static inline void clts(void) |
501 | { | |
93b1eab3 | 502 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 503 | } |
d3561b7f | 504 | |
f8822f42 JF |
505 | static inline unsigned long read_cr0(void) |
506 | { | |
93b1eab3 | 507 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 508 | } |
d3561b7f | 509 | |
f8822f42 JF |
510 | static inline void write_cr0(unsigned long x) |
511 | { | |
93b1eab3 | 512 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
513 | } |
514 | ||
515 | static inline unsigned long read_cr2(void) | |
516 | { | |
93b1eab3 | 517 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
518 | } |
519 | ||
520 | static inline void write_cr2(unsigned long x) | |
521 | { | |
93b1eab3 | 522 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
523 | } |
524 | ||
525 | static inline unsigned long read_cr3(void) | |
526 | { | |
93b1eab3 | 527 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 528 | } |
d3561b7f | 529 | |
f8822f42 JF |
530 | static inline void write_cr3(unsigned long x) |
531 | { | |
93b1eab3 | 532 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 533 | } |
d3561b7f | 534 | |
f8822f42 JF |
535 | static inline unsigned long read_cr4(void) |
536 | { | |
93b1eab3 | 537 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 JF |
538 | } |
539 | static inline unsigned long read_cr4_safe(void) | |
540 | { | |
93b1eab3 | 541 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 542 | } |
d3561b7f | 543 | |
f8822f42 JF |
544 | static inline void write_cr4(unsigned long x) |
545 | { | |
93b1eab3 | 546 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 547 | } |
3dc494e8 | 548 | |
d3561b7f RR |
549 | static inline void raw_safe_halt(void) |
550 | { | |
93b1eab3 | 551 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
552 | } |
553 | ||
554 | static inline void halt(void) | |
555 | { | |
93b1eab3 | 556 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
f8822f42 JF |
557 | } |
558 | ||
559 | static inline void wbinvd(void) | |
560 | { | |
93b1eab3 | 561 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 562 | } |
d3561b7f | 563 | |
93b1eab3 | 564 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 565 | |
f8822f42 JF |
566 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
567 | { | |
93b1eab3 | 568 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 JF |
569 | } |
570 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) | |
571 | { | |
93b1eab3 | 572 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
573 | } |
574 | ||
90a0a06a | 575 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
f8822f42 JF |
576 | #define rdmsr(msr,val1,val2) do { \ |
577 | int _err; \ | |
578 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
579 | val1 = (u32)_l; \ | |
580 | val2 = _l >> 32; \ | |
d3561b7f RR |
581 | } while(0) |
582 | ||
f8822f42 JF |
583 | #define wrmsr(msr,val1,val2) do { \ |
584 | paravirt_write_msr(msr, val1, val2); \ | |
d3561b7f RR |
585 | } while(0) |
586 | ||
f8822f42 JF |
587 | #define rdmsrl(msr,val) do { \ |
588 | int _err; \ | |
589 | val = paravirt_read_msr(msr, &_err); \ | |
d3561b7f RR |
590 | } while(0) |
591 | ||
b9e3614f | 592 | #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) |
f8822f42 | 593 | #define wrmsr_safe(msr,a,b) paravirt_write_msr(msr, a, b) |
d3561b7f RR |
594 | |
595 | /* rdmsr with exception handling */ | |
f8822f42 JF |
596 | #define rdmsr_safe(msr,a,b) ({ \ |
597 | int _err; \ | |
598 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
599 | (*a) = (u32)_l; \ | |
600 | (*b) = _l >> 32; \ | |
d3561b7f RR |
601 | _err; }) |
602 | ||
f8822f42 JF |
603 | |
604 | static inline u64 paravirt_read_tsc(void) | |
605 | { | |
93b1eab3 | 606 | return PVOP_CALL0(u64, pv_cpu_ops.read_tsc); |
f8822f42 | 607 | } |
d3561b7f | 608 | |
f8822f42 JF |
609 | #define rdtscl(low) do { \ |
610 | u64 _l = paravirt_read_tsc(); \ | |
611 | low = (int)_l; \ | |
d3561b7f RR |
612 | } while(0) |
613 | ||
f8822f42 | 614 | #define rdtscll(val) (val = paravirt_read_tsc()) |
d3561b7f | 615 | |
688340ea JF |
616 | static inline unsigned long long paravirt_sched_clock(void) |
617 | { | |
93b1eab3 | 618 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 619 | } |
93b1eab3 | 620 | #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz()) |
6cb9a835 | 621 | |
d3561b7f RR |
622 | #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) |
623 | ||
f8822f42 JF |
624 | static inline unsigned long long paravirt_read_pmc(int counter) |
625 | { | |
93b1eab3 | 626 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 627 | } |
d3561b7f | 628 | |
f8822f42 JF |
629 | #define rdpmc(counter,low,high) do { \ |
630 | u64 _l = paravirt_read_pmc(counter); \ | |
631 | low = (u32)_l; \ | |
632 | high = _l >> 32; \ | |
633 | } while(0) | |
3dc494e8 | 634 | |
f8822f42 JF |
635 | static inline void load_TR_desc(void) |
636 | { | |
93b1eab3 | 637 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 JF |
638 | } |
639 | static inline void load_gdt(const struct Xgt_desc_struct *dtr) | |
640 | { | |
93b1eab3 | 641 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 JF |
642 | } |
643 | static inline void load_idt(const struct Xgt_desc_struct *dtr) | |
644 | { | |
93b1eab3 | 645 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
646 | } |
647 | static inline void set_ldt(const void *addr, unsigned entries) | |
648 | { | |
93b1eab3 | 649 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 JF |
650 | } |
651 | static inline void store_gdt(struct Xgt_desc_struct *dtr) | |
652 | { | |
93b1eab3 | 653 | PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr); |
f8822f42 JF |
654 | } |
655 | static inline void store_idt(struct Xgt_desc_struct *dtr) | |
656 | { | |
93b1eab3 | 657 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
658 | } |
659 | static inline unsigned long paravirt_store_tr(void) | |
660 | { | |
93b1eab3 | 661 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
662 | } |
663 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
664 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
665 | { | |
93b1eab3 | 666 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 JF |
667 | } |
668 | static inline void write_ldt_entry(void *dt, int entry, u32 low, u32 high) | |
669 | { | |
93b1eab3 | 670 | PVOP_VCALL4(pv_cpu_ops.write_ldt_entry, dt, entry, low, high); |
f8822f42 JF |
671 | } |
672 | static inline void write_gdt_entry(void *dt, int entry, u32 low, u32 high) | |
673 | { | |
93b1eab3 | 674 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, low, high); |
f8822f42 JF |
675 | } |
676 | static inline void write_idt_entry(void *dt, int entry, u32 low, u32 high) | |
677 | { | |
93b1eab3 | 678 | PVOP_VCALL4(pv_cpu_ops.write_idt_entry, dt, entry, low, high); |
f8822f42 JF |
679 | } |
680 | static inline void set_iopl_mask(unsigned mask) | |
681 | { | |
93b1eab3 | 682 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 683 | } |
3dc494e8 | 684 | |
d3561b7f RR |
685 | /* The paravirtualized I/O functions */ |
686 | static inline void slow_down_io(void) { | |
93b1eab3 | 687 | pv_cpu_ops.io_delay(); |
d3561b7f | 688 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
689 | pv_cpu_ops.io_delay(); |
690 | pv_cpu_ops.io_delay(); | |
691 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
692 | #endif |
693 | } | |
694 | ||
13623d79 RR |
695 | #ifdef CONFIG_X86_LOCAL_APIC |
696 | /* | |
697 | * Basic functions accessing APICs. | |
698 | */ | |
699 | static inline void apic_write(unsigned long reg, unsigned long v) | |
700 | { | |
93b1eab3 | 701 | PVOP_VCALL2(pv_apic_ops.apic_write, reg, v); |
13623d79 RR |
702 | } |
703 | ||
704 | static inline void apic_write_atomic(unsigned long reg, unsigned long v) | |
705 | { | |
93b1eab3 | 706 | PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v); |
13623d79 RR |
707 | } |
708 | ||
709 | static inline unsigned long apic_read(unsigned long reg) | |
710 | { | |
93b1eab3 | 711 | return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg); |
13623d79 | 712 | } |
bbab4f3b ZA |
713 | |
714 | static inline void setup_boot_clock(void) | |
715 | { | |
93b1eab3 | 716 | PVOP_VCALL0(pv_apic_ops.setup_boot_clock); |
bbab4f3b ZA |
717 | } |
718 | ||
719 | static inline void setup_secondary_clock(void) | |
720 | { | |
93b1eab3 | 721 | PVOP_VCALL0(pv_apic_ops.setup_secondary_clock); |
bbab4f3b | 722 | } |
13623d79 RR |
723 | #endif |
724 | ||
6996d3b6 JF |
725 | static inline void paravirt_post_allocator_init(void) |
726 | { | |
93b1eab3 JF |
727 | if (pv_init_ops.post_allocator_init) |
728 | (*pv_init_ops.post_allocator_init)(); | |
6996d3b6 JF |
729 | } |
730 | ||
b239fb25 JF |
731 | static inline void paravirt_pagetable_setup_start(pgd_t *base) |
732 | { | |
93b1eab3 | 733 | (*pv_mmu_ops.pagetable_setup_start)(base); |
b239fb25 JF |
734 | } |
735 | ||
736 | static inline void paravirt_pagetable_setup_done(pgd_t *base) | |
737 | { | |
93b1eab3 | 738 | (*pv_mmu_ops.pagetable_setup_done)(base); |
b239fb25 | 739 | } |
3dc494e8 | 740 | |
ae5da273 ZA |
741 | #ifdef CONFIG_SMP |
742 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
743 | unsigned long start_esp) | |
744 | { | |
93b1eab3 JF |
745 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
746 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
747 | } |
748 | #endif | |
13623d79 | 749 | |
d6dd61c8 JF |
750 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
751 | struct mm_struct *next) | |
752 | { | |
93b1eab3 | 753 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
754 | } |
755 | ||
756 | static inline void arch_dup_mmap(struct mm_struct *oldmm, | |
757 | struct mm_struct *mm) | |
758 | { | |
93b1eab3 | 759 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
760 | } |
761 | ||
762 | static inline void arch_exit_mmap(struct mm_struct *mm) | |
763 | { | |
93b1eab3 | 764 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
765 | } |
766 | ||
f8822f42 JF |
767 | static inline void __flush_tlb(void) |
768 | { | |
93b1eab3 | 769 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
770 | } |
771 | static inline void __flush_tlb_global(void) | |
772 | { | |
93b1eab3 | 773 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
774 | } |
775 | static inline void __flush_tlb_single(unsigned long addr) | |
776 | { | |
93b1eab3 | 777 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 778 | } |
da181a8b | 779 | |
d4c10477 JF |
780 | static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, |
781 | unsigned long va) | |
782 | { | |
93b1eab3 | 783 | PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va); |
d4c10477 JF |
784 | } |
785 | ||
fdb4c338 | 786 | static inline void paravirt_alloc_pt(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 787 | { |
93b1eab3 | 788 | PVOP_VCALL2(pv_mmu_ops.alloc_pt, mm, pfn); |
f8822f42 JF |
789 | } |
790 | static inline void paravirt_release_pt(unsigned pfn) | |
791 | { | |
93b1eab3 | 792 | PVOP_VCALL1(pv_mmu_ops.release_pt, pfn); |
f8822f42 | 793 | } |
c119ecce | 794 | |
f8822f42 JF |
795 | static inline void paravirt_alloc_pd(unsigned pfn) |
796 | { | |
93b1eab3 | 797 | PVOP_VCALL1(pv_mmu_ops.alloc_pd, pfn); |
f8822f42 | 798 | } |
c119ecce | 799 | |
f8822f42 JF |
800 | static inline void paravirt_alloc_pd_clone(unsigned pfn, unsigned clonepfn, |
801 | unsigned start, unsigned count) | |
802 | { | |
93b1eab3 | 803 | PVOP_VCALL4(pv_mmu_ops.alloc_pd_clone, pfn, clonepfn, start, count); |
f8822f42 JF |
804 | } |
805 | static inline void paravirt_release_pd(unsigned pfn) | |
da181a8b | 806 | { |
93b1eab3 | 807 | PVOP_VCALL1(pv_mmu_ops.release_pd, pfn); |
da181a8b RR |
808 | } |
809 | ||
ce6234b5 JF |
810 | #ifdef CONFIG_HIGHPTE |
811 | static inline void *kmap_atomic_pte(struct page *page, enum km_type type) | |
812 | { | |
813 | unsigned long ret; | |
93b1eab3 | 814 | ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type); |
ce6234b5 JF |
815 | return (void *)ret; |
816 | } | |
817 | #endif | |
818 | ||
f8822f42 JF |
819 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
820 | pte_t *ptep) | |
da181a8b | 821 | { |
93b1eab3 | 822 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b RR |
823 | } |
824 | ||
f8822f42 JF |
825 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
826 | pte_t *ptep) | |
da181a8b | 827 | { |
93b1eab3 | 828 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
829 | } |
830 | ||
f8822f42 JF |
831 | #ifdef CONFIG_X86_PAE |
832 | static inline pte_t __pte(unsigned long long val) | |
da181a8b | 833 | { |
93b1eab3 JF |
834 | unsigned long long ret = PVOP_CALL2(unsigned long long, |
835 | pv_mmu_ops.make_pte, | |
f8822f42 JF |
836 | val, val >> 32); |
837 | return (pte_t) { ret, ret >> 32 }; | |
da181a8b RR |
838 | } |
839 | ||
f8822f42 | 840 | static inline pmd_t __pmd(unsigned long long val) |
da181a8b | 841 | { |
93b1eab3 JF |
842 | return (pmd_t) { PVOP_CALL2(unsigned long long, pv_mmu_ops.make_pmd, |
843 | val, val >> 32) }; | |
f8822f42 JF |
844 | } |
845 | ||
846 | static inline pgd_t __pgd(unsigned long long val) | |
847 | { | |
93b1eab3 JF |
848 | return (pgd_t) { PVOP_CALL2(unsigned long long, pv_mmu_ops.make_pgd, |
849 | val, val >> 32) }; | |
f8822f42 JF |
850 | } |
851 | ||
852 | static inline unsigned long long pte_val(pte_t x) | |
853 | { | |
93b1eab3 JF |
854 | return PVOP_CALL2(unsigned long long, pv_mmu_ops.pte_val, |
855 | x.pte_low, x.pte_high); | |
f8822f42 JF |
856 | } |
857 | ||
858 | static inline unsigned long long pmd_val(pmd_t x) | |
859 | { | |
93b1eab3 JF |
860 | return PVOP_CALL2(unsigned long long, pv_mmu_ops.pmd_val, |
861 | x.pmd, x.pmd >> 32); | |
f8822f42 JF |
862 | } |
863 | ||
864 | static inline unsigned long long pgd_val(pgd_t x) | |
865 | { | |
93b1eab3 JF |
866 | return PVOP_CALL2(unsigned long long, pv_mmu_ops.pgd_val, |
867 | x.pgd, x.pgd >> 32); | |
f8822f42 JF |
868 | } |
869 | ||
870 | static inline void set_pte(pte_t *ptep, pte_t pteval) | |
871 | { | |
93b1eab3 | 872 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, pteval.pte_low, pteval.pte_high); |
f8822f42 JF |
873 | } |
874 | ||
875 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
876 | pte_t *ptep, pte_t pteval) | |
877 | { | |
878 | /* 5 arg words */ | |
93b1eab3 | 879 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pteval); |
da181a8b RR |
880 | } |
881 | ||
da181a8b RR |
882 | static inline void set_pte_atomic(pte_t *ptep, pte_t pteval) |
883 | { | |
93b1eab3 JF |
884 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, |
885 | pteval.pte_low, pteval.pte_high); | |
da181a8b RR |
886 | } |
887 | ||
f8822f42 JF |
888 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, |
889 | pte_t *ptep, pte_t pte) | |
da181a8b | 890 | { |
f8822f42 | 891 | /* 5 arg words */ |
93b1eab3 | 892 | pv_mmu_ops.set_pte_present(mm, addr, ptep, pte); |
da181a8b RR |
893 | } |
894 | ||
f8822f42 JF |
895 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval) |
896 | { | |
93b1eab3 JF |
897 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, |
898 | pmdval.pmd, pmdval.pmd >> 32); | |
f8822f42 JF |
899 | } |
900 | ||
da181a8b RR |
901 | static inline void set_pud(pud_t *pudp, pud_t pudval) |
902 | { | |
93b1eab3 JF |
903 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, |
904 | pudval.pgd.pgd, pudval.pgd.pgd >> 32); | |
da181a8b RR |
905 | } |
906 | ||
907 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
908 | { | |
93b1eab3 | 909 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); |
da181a8b RR |
910 | } |
911 | ||
912 | static inline void pmd_clear(pmd_t *pmdp) | |
913 | { | |
93b1eab3 | 914 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); |
f8822f42 JF |
915 | } |
916 | ||
f8822f42 | 917 | #else /* !CONFIG_X86_PAE */ |
4cdd9c89 | 918 | |
f8822f42 JF |
919 | static inline pte_t __pte(unsigned long val) |
920 | { | |
93b1eab3 | 921 | return (pte_t) { PVOP_CALL1(unsigned long, pv_mmu_ops.make_pte, val) }; |
da181a8b | 922 | } |
f8822f42 JF |
923 | |
924 | static inline pgd_t __pgd(unsigned long val) | |
925 | { | |
93b1eab3 | 926 | return (pgd_t) { PVOP_CALL1(unsigned long, pv_mmu_ops.make_pgd, val) }; |
f8822f42 JF |
927 | } |
928 | ||
929 | static inline unsigned long pte_val(pte_t x) | |
930 | { | |
93b1eab3 | 931 | return PVOP_CALL1(unsigned long, pv_mmu_ops.pte_val, x.pte_low); |
f8822f42 JF |
932 | } |
933 | ||
934 | static inline unsigned long pgd_val(pgd_t x) | |
935 | { | |
93b1eab3 | 936 | return PVOP_CALL1(unsigned long, pv_mmu_ops.pgd_val, x.pgd); |
f8822f42 JF |
937 | } |
938 | ||
939 | static inline void set_pte(pte_t *ptep, pte_t pteval) | |
940 | { | |
93b1eab3 | 941 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, pteval.pte_low); |
f8822f42 JF |
942 | } |
943 | ||
944 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
945 | pte_t *ptep, pte_t pteval) | |
946 | { | |
93b1eab3 | 947 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pteval.pte_low); |
f8822f42 JF |
948 | } |
949 | ||
950 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval) | |
951 | { | |
93b1eab3 | 952 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, pmdval.pud.pgd.pgd); |
f8822f42 | 953 | } |
f8822f42 | 954 | #endif /* CONFIG_X86_PAE */ |
da181a8b | 955 | |
9226d125 | 956 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE |
f8822f42 JF |
957 | static inline void arch_enter_lazy_cpu_mode(void) |
958 | { | |
93b1eab3 | 959 | PVOP_VCALL1(pv_misc_ops.set_lazy_mode, PARAVIRT_LAZY_CPU); |
f8822f42 JF |
960 | } |
961 | ||
962 | static inline void arch_leave_lazy_cpu_mode(void) | |
963 | { | |
93b1eab3 | 964 | PVOP_VCALL1(pv_misc_ops.set_lazy_mode, PARAVIRT_LAZY_NONE); |
f8822f42 JF |
965 | } |
966 | ||
967 | static inline void arch_flush_lazy_cpu_mode(void) | |
968 | { | |
93b1eab3 | 969 | PVOP_VCALL1(pv_misc_ops.set_lazy_mode, PARAVIRT_LAZY_FLUSH); |
f8822f42 JF |
970 | } |
971 | ||
9226d125 ZA |
972 | |
973 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
f8822f42 JF |
974 | static inline void arch_enter_lazy_mmu_mode(void) |
975 | { | |
93b1eab3 | 976 | PVOP_VCALL1(pv_misc_ops.set_lazy_mode, PARAVIRT_LAZY_MMU); |
f8822f42 JF |
977 | } |
978 | ||
979 | static inline void arch_leave_lazy_mmu_mode(void) | |
980 | { | |
93b1eab3 | 981 | PVOP_VCALL1(pv_misc_ops.set_lazy_mode, PARAVIRT_LAZY_NONE); |
f8822f42 JF |
982 | } |
983 | ||
984 | static inline void arch_flush_lazy_mmu_mode(void) | |
985 | { | |
93b1eab3 | 986 | PVOP_VCALL1(pv_misc_ops.set_lazy_mode, PARAVIRT_LAZY_FLUSH); |
f8822f42 | 987 | } |
9226d125 | 988 | |
45876233 JF |
989 | void _paravirt_nop(void); |
990 | #define paravirt_nop ((void *)_paravirt_nop) | |
991 | ||
139ec7c4 | 992 | /* These all sit in the .parainstructions section to tell us what to patch. */ |
98de032b | 993 | struct paravirt_patch_site { |
139ec7c4 RR |
994 | u8 *instr; /* original instructions */ |
995 | u8 instrtype; /* type of this instruction */ | |
996 | u8 len; /* length of original instruction */ | |
997 | u16 clobbers; /* what registers you may clobber */ | |
998 | }; | |
999 | ||
98de032b JF |
1000 | extern struct paravirt_patch_site __parainstructions[], |
1001 | __parainstructions_end[]; | |
1002 | ||
139ec7c4 RR |
1003 | static inline unsigned long __raw_local_save_flags(void) |
1004 | { | |
1005 | unsigned long f; | |
1006 | ||
d5822035 JF |
1007 | asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;" |
1008 | PARAVIRT_CALL | |
1009 | "popl %%edx; popl %%ecx") | |
1010 | : "=a"(f) | |
93b1eab3 | 1011 | : paravirt_type(pv_irq_ops.save_fl), |
42c24fa2 | 1012 | paravirt_clobber(CLBR_EAX) |
d5822035 | 1013 | : "memory", "cc"); |
139ec7c4 RR |
1014 | return f; |
1015 | } | |
1016 | ||
1017 | static inline void raw_local_irq_restore(unsigned long f) | |
1018 | { | |
d5822035 JF |
1019 | asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;" |
1020 | PARAVIRT_CALL | |
1021 | "popl %%edx; popl %%ecx") | |
1022 | : "=a"(f) | |
1023 | : "0"(f), | |
93b1eab3 | 1024 | paravirt_type(pv_irq_ops.restore_fl), |
d5822035 JF |
1025 | paravirt_clobber(CLBR_EAX) |
1026 | : "memory", "cc"); | |
139ec7c4 RR |
1027 | } |
1028 | ||
1029 | static inline void raw_local_irq_disable(void) | |
1030 | { | |
d5822035 JF |
1031 | asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;" |
1032 | PARAVIRT_CALL | |
1033 | "popl %%edx; popl %%ecx") | |
1034 | : | |
93b1eab3 | 1035 | : paravirt_type(pv_irq_ops.irq_disable), |
d5822035 JF |
1036 | paravirt_clobber(CLBR_EAX) |
1037 | : "memory", "eax", "cc"); | |
139ec7c4 RR |
1038 | } |
1039 | ||
1040 | static inline void raw_local_irq_enable(void) | |
1041 | { | |
d5822035 JF |
1042 | asm volatile(paravirt_alt("pushl %%ecx; pushl %%edx;" |
1043 | PARAVIRT_CALL | |
1044 | "popl %%edx; popl %%ecx") | |
1045 | : | |
93b1eab3 | 1046 | : paravirt_type(pv_irq_ops.irq_enable), |
d5822035 JF |
1047 | paravirt_clobber(CLBR_EAX) |
1048 | : "memory", "eax", "cc"); | |
139ec7c4 RR |
1049 | } |
1050 | ||
1051 | static inline unsigned long __raw_local_irq_save(void) | |
1052 | { | |
1053 | unsigned long f; | |
1054 | ||
d5822035 JF |
1055 | f = __raw_local_save_flags(); |
1056 | raw_local_irq_disable(); | |
139ec7c4 RR |
1057 | return f; |
1058 | } | |
1059 | ||
d5822035 JF |
1060 | #define CLI_STRING \ |
1061 | _paravirt_alt("pushl %%ecx; pushl %%edx;" \ | |
93b1eab3 | 1062 | "call *%[paravirt_cli_opptr];" \ |
d5822035 JF |
1063 | "popl %%edx; popl %%ecx", \ |
1064 | "%c[paravirt_cli_type]", "%c[paravirt_clobber]") | |
1065 | ||
1066 | #define STI_STRING \ | |
1067 | _paravirt_alt("pushl %%ecx; pushl %%edx;" \ | |
93b1eab3 | 1068 | "call *%[paravirt_sti_opptr];" \ |
d5822035 JF |
1069 | "popl %%edx; popl %%ecx", \ |
1070 | "%c[paravirt_sti_type]", "%c[paravirt_clobber]") | |
139ec7c4 | 1071 | |
139ec7c4 | 1072 | #define CLI_STI_CLOBBERS , "%eax" |
d5822035 | 1073 | #define CLI_STI_INPUT_ARGS \ |
139ec7c4 | 1074 | , \ |
93b1eab3 JF |
1075 | [paravirt_cli_type] "i" (PARAVIRT_PATCH(pv_irq_ops.irq_disable)), \ |
1076 | [paravirt_cli_opptr] "m" (pv_irq_ops.irq_disable), \ | |
1077 | [paravirt_sti_type] "i" (PARAVIRT_PATCH(pv_irq_ops.irq_enable)), \ | |
1078 | [paravirt_sti_opptr] "m" (pv_irq_ops.irq_enable), \ | |
d5822035 JF |
1079 | paravirt_clobber(CLBR_EAX) |
1080 | ||
294688c0 | 1081 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 1082 | #undef PARAVIRT_CALL |
1a45b7aa JF |
1083 | #undef __PVOP_CALL |
1084 | #undef __PVOP_VCALL | |
f8822f42 JF |
1085 | #undef PVOP_VCALL0 |
1086 | #undef PVOP_CALL0 | |
1087 | #undef PVOP_VCALL1 | |
1088 | #undef PVOP_CALL1 | |
1089 | #undef PVOP_VCALL2 | |
1090 | #undef PVOP_CALL2 | |
1091 | #undef PVOP_VCALL3 | |
1092 | #undef PVOP_CALL3 | |
1093 | #undef PVOP_VCALL4 | |
1094 | #undef PVOP_CALL4 | |
139ec7c4 | 1095 | |
d3561b7f RR |
1096 | #else /* __ASSEMBLY__ */ |
1097 | ||
93b1eab3 | 1098 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) |
d5822035 JF |
1099 | |
1100 | #define PARA_SITE(ptype, clobbers, ops) \ | |
139ec7c4 RR |
1101 | 771:; \ |
1102 | ops; \ | |
1103 | 772:; \ | |
1104 | .pushsection .parainstructions,"a"; \ | |
1105 | .long 771b; \ | |
1106 | .byte ptype; \ | |
1107 | .byte 772b-771b; \ | |
1108 | .short clobbers; \ | |
1109 | .popsection | |
1110 | ||
93b1eab3 JF |
1111 | #define INTERRUPT_RETURN \ |
1112 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
1113 | jmp *%cs:pv_cpu_ops+PV_CPU_iret) | |
d5822035 JF |
1114 | |
1115 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1116 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
42c24fa2 | 1117 | pushl %eax; pushl %ecx; pushl %edx; \ |
93b1eab3 | 1118 | call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \ |
42c24fa2 | 1119 | popl %edx; popl %ecx; popl %eax) \ |
d5822035 JF |
1120 | |
1121 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1122 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
42c24fa2 | 1123 | pushl %eax; pushl %ecx; pushl %edx; \ |
93b1eab3 | 1124 | call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \ |
42c24fa2 | 1125 | popl %edx; popl %ecx; popl %eax) |
d5822035 | 1126 | |
93b1eab3 JF |
1127 | #define ENABLE_INTERRUPTS_SYSEXIT \ |
1128 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), CLBR_NONE,\ | |
1129 | jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_sysexit) | |
139ec7c4 RR |
1130 | |
1131 | #define GET_CR0_INTO_EAX \ | |
42c24fa2 | 1132 | push %ecx; push %edx; \ |
93b1eab3 | 1133 | call *pv_cpu_ops+PV_CPU_read_cr0; \ |
42c24fa2 | 1134 | pop %edx; pop %ecx |
139ec7c4 | 1135 | |
d3561b7f RR |
1136 | #endif /* __ASSEMBLY__ */ |
1137 | #endif /* CONFIG_PARAVIRT */ | |
1138 | #endif /* __ASM_PARAVIRT_H */ |