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1da177e4 LT |
1 | #ifndef _I386_PGTABLE_3LEVEL_H |
2 | #define _I386_PGTABLE_3LEVEL_H | |
3 | ||
1da177e4 LT |
4 | /* |
5 | * Intel Physical Address Extension (PAE) Mode - three-level page | |
6 | * tables on PPro+ CPUs. | |
7 | * | |
8 | * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> | |
9 | */ | |
10 | ||
11 | #define pte_ERROR(e) \ | |
12 | printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) | |
13 | #define pmd_ERROR(e) \ | |
14 | printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) | |
15 | #define pgd_ERROR(e) \ | |
16 | printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) | |
17 | ||
6194ba6f JF |
18 | |
19 | static inline int pud_none(pud_t pud) | |
20 | { | |
21 | return pud_val(pud) == 0; | |
22 | } | |
23 | static inline int pud_bad(pud_t pud) | |
24 | { | |
25 | return (pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0; | |
26 | } | |
27 | static inline int pud_present(pud_t pud) | |
28 | { | |
29 | return pud_val(pud) & _PAGE_PRESENT; | |
30 | } | |
1da177e4 | 31 | |
1da177e4 LT |
32 | /* Rules for using set_pte: the pte being assigned *must* be |
33 | * either not present or in a state where the hardware will | |
34 | * not attempt to update the pte. In places where this is | |
35 | * not possible, use pte_get_and_clear to obtain the old pte | |
36 | * value and then use set_pte to update it. -ben | |
37 | */ | |
3dc494e8 | 38 | static inline void native_set_pte(pte_t *ptep, pte_t pte) |
1da177e4 LT |
39 | { |
40 | ptep->pte_high = pte.pte_high; | |
41 | smp_wmb(); | |
42 | ptep->pte_low = pte.pte_low; | |
43 | } | |
1da177e4 | 44 | |
d6d861e3 ZA |
45 | /* |
46 | * Since this is only called on user PTEs, and the page fault handler | |
47 | * must handle the already racy situation of simultaneous page faults, | |
48 | * we are justified in merely clearing the PTE present bit, followed | |
49 | * by a set. The ordering here is important. | |
50 | */ | |
3dc494e8 JF |
51 | static inline void native_set_pte_present(struct mm_struct *mm, unsigned long addr, |
52 | pte_t *ptep, pte_t pte) | |
d6d861e3 ZA |
53 | { |
54 | ptep->pte_low = 0; | |
55 | smp_wmb(); | |
56 | ptep->pte_high = pte.pte_high; | |
57 | smp_wmb(); | |
58 | ptep->pte_low = pte.pte_low; | |
59 | } | |
60 | ||
3dc494e8 JF |
61 | static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) |
62 | { | |
63 | set_64bit((unsigned long long *)(ptep),native_pte_val(pte)); | |
64 | } | |
65 | static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) | |
66 | { | |
67 | set_64bit((unsigned long long *)(pmdp),native_pmd_val(pmd)); | |
68 | } | |
69 | static inline void native_set_pud(pud_t *pudp, pud_t pud) | |
70 | { | |
6194ba6f | 71 | set_64bit((unsigned long long *)(pudp),native_pud_val(pud)); |
3dc494e8 | 72 | } |
1da177e4 | 73 | |
6e5882cf ZA |
74 | /* |
75 | * For PTEs and PDEs, we must clear the P-bit first when clearing a page table | |
76 | * entry, so clear the bottom half first and enforce ordering with a compiler | |
77 | * barrier. | |
78 | */ | |
3dc494e8 | 79 | static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
6e5882cf ZA |
80 | { |
81 | ptep->pte_low = 0; | |
82 | smp_wmb(); | |
83 | ptep->pte_high = 0; | |
84 | } | |
85 | ||
3dc494e8 | 86 | static inline void native_pmd_clear(pmd_t *pmd) |
6e5882cf ZA |
87 | { |
88 | u32 *tmp = (u32 *)pmd; | |
89 | *tmp = 0; | |
90 | smp_wmb(); | |
91 | *(tmp + 1) = 0; | |
92 | } | |
3dc494e8 | 93 | |
6194ba6f JF |
94 | static inline void pud_clear(pud_t *pudp) |
95 | { | |
edd6bcd8 JF |
96 | unsigned long pgd; |
97 | ||
6194ba6f JF |
98 | set_pud(pudp, __pud(0)); |
99 | ||
100 | /* | |
a67ad9c9 JF |
101 | * Pentium-II erratum A13: in PAE mode we explicitly have to flush |
102 | * the TLB via cr3 if the top-level pgd is changed... | |
6194ba6f | 103 | * |
edd6bcd8 JF |
104 | * Make sure the pud entry we're updating is within the |
105 | * current pgd to avoid unnecessary TLB flushes. | |
6194ba6f | 106 | */ |
edd6bcd8 JF |
107 | pgd = read_cr3(); |
108 | if (__pa(pudp) >= pgd && __pa(pudp) < (pgd + sizeof(pgd_t)*PTRS_PER_PGD)) | |
109 | write_cr3(pgd); | |
6194ba6f | 110 | } |
da181a8b RR |
111 | |
112 | #define pud_page(pud) \ | |
113 | ((struct page *) __va(pud_val(pud) & PAGE_MASK)) | |
114 | ||
115 | #define pud_page_vaddr(pud) \ | |
116 | ((unsigned long) __va(pud_val(pud) & PAGE_MASK)) | |
117 | ||
118 | ||
119 | /* Find an entry in the second-level page table.. */ | |
120 | #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \ | |
121 | pmd_index(address)) | |
6e5882cf | 122 | |
142dd975 | 123 | #ifdef CONFIG_SMP |
3dc494e8 | 124 | static inline pte_t native_ptep_get_and_clear(pte_t *ptep) |
1da177e4 LT |
125 | { |
126 | pte_t res; | |
127 | ||
128 | /* xchg acts as a barrier before the setting of the high bits */ | |
129 | res.pte_low = xchg(&ptep->pte_low, 0); | |
130 | res.pte_high = ptep->pte_high; | |
131 | ptep->pte_high = 0; | |
132 | ||
133 | return res; | |
134 | } | |
142dd975 ZA |
135 | #else |
136 | #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) | |
137 | #endif | |
1da177e4 | 138 | |
6049742d | 139 | #define __HAVE_ARCH_PTE_SAME |
1da177e4 LT |
140 | static inline int pte_same(pte_t a, pte_t b) |
141 | { | |
142 | return a.pte_low == b.pte_low && a.pte_high == b.pte_high; | |
143 | } | |
144 | ||
145 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
146 | ||
147 | static inline int pte_none(pte_t pte) | |
148 | { | |
149 | return !pte.pte_low && !pte.pte_high; | |
150 | } | |
151 | ||
152 | static inline unsigned long pte_pfn(pte_t pte) | |
153 | { | |
c3bcfb57 | 154 | return (pte_val(pte) & ~_PAGE_NX) >> PAGE_SHIFT; |
1da177e4 LT |
155 | } |
156 | ||
1da177e4 LT |
157 | /* |
158 | * Bits 0, 6 and 7 are taken in the low part of the pte, | |
159 | * put the 32 bits of offset into the high part. | |
160 | */ | |
161 | #define pte_to_pgoff(pte) ((pte).pte_high) | |
c8e5393a | 162 | #define pgoff_to_pte(off) ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } }) |
1da177e4 LT |
163 | #define PTE_FILE_MAX_BITS 32 |
164 | ||
165 | /* Encode and de-code a swap entry */ | |
166 | #define __swp_type(x) (((x).val) & 0x1f) | |
167 | #define __swp_offset(x) ((x).val >> 5) | |
168 | #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) | |
169 | #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high }) | |
c8e5393a | 170 | #define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } }) |
1da177e4 | 171 | |
1da177e4 | 172 | #endif /* _I386_PGTABLE_3LEVEL_H */ |