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1da177e4 LT |
1 | #ifndef _X86_64_PGTABLE_H |
2 | #define _X86_64_PGTABLE_H | |
3 | ||
6df95fd7 | 4 | #include <linux/const.h> |
9d291e78 VG |
5 | #ifndef __ASSEMBLY__ |
6 | ||
1da177e4 LT |
7 | /* |
8 | * This file contains the functions and defines necessary to modify and use | |
9 | * the x86-64 page table tree. | |
10 | */ | |
11 | #include <asm/processor.h> | |
1977f032 | 12 | #include <linux/bitops.h> |
1da177e4 LT |
13 | #include <linux/threads.h> |
14 | #include <asm/pda.h> | |
15 | ||
16 | extern pud_t level3_kernel_pgt[512]; | |
1da177e4 LT |
17 | extern pud_t level3_ident_pgt[512]; |
18 | extern pmd_t level2_kernel_pgt[512]; | |
19 | extern pgd_t init_level4_pgt[]; | |
1da177e4 | 20 | |
e3ebadd9 | 21 | #define swapper_pg_dir init_level4_pgt |
1da177e4 | 22 | |
1da177e4 LT |
23 | extern void paging_init(void); |
24 | extern void clear_kernel_mapping(unsigned long addr, unsigned long size); | |
25 | ||
9d291e78 VG |
26 | #endif /* !__ASSEMBLY__ */ |
27 | ||
1da177e4 LT |
28 | /* |
29 | * PGDIR_SHIFT determines what a top-level page table entry can map | |
30 | */ | |
31 | #define PGDIR_SHIFT 39 | |
32 | #define PTRS_PER_PGD 512 | |
33 | ||
34 | /* | |
35 | * 3rd level page | |
36 | */ | |
37 | #define PUD_SHIFT 30 | |
38 | #define PTRS_PER_PUD 512 | |
39 | ||
40 | /* | |
41 | * PMD_SHIFT determines the size of the area a middle-level | |
42 | * page table can map | |
43 | */ | |
44 | #define PMD_SHIFT 21 | |
45 | #define PTRS_PER_PMD 512 | |
46 | ||
47 | /* | |
48 | * entries per page directory level | |
49 | */ | |
50 | #define PTRS_PER_PTE 512 | |
51 | ||
9d291e78 VG |
52 | #ifndef __ASSEMBLY__ |
53 | ||
1da177e4 LT |
54 | #define pte_ERROR(e) \ |
55 | printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) | |
56 | #define pmd_ERROR(e) \ | |
57 | printk("%s:%d: bad pmd %p(%016lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) | |
58 | #define pud_ERROR(e) \ | |
59 | printk("%s:%d: bad pud %p(%016lx).\n", __FILE__, __LINE__, &(e), pud_val(e)) | |
60 | #define pgd_ERROR(e) \ | |
61 | printk("%s:%d: bad pgd %p(%016lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) | |
62 | ||
63 | #define pgd_none(x) (!pgd_val(x)) | |
64 | #define pud_none(x) (!pud_val(x)) | |
65 | ||
66 | static inline void set_pte(pte_t *dst, pte_t val) | |
67 | { | |
c8e5393a | 68 | *dst = val; |
1da177e4 LT |
69 | } |
70 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) | |
71 | ||
72 | static inline void set_pmd(pmd_t *dst, pmd_t val) | |
73 | { | |
7a2389b4 | 74 | *dst = val; |
1da177e4 LT |
75 | } |
76 | ||
77 | static inline void set_pud(pud_t *dst, pud_t val) | |
78 | { | |
7a2389b4 | 79 | *dst = val; |
1da177e4 LT |
80 | } |
81 | ||
9c0aa0f9 | 82 | static inline void pud_clear (pud_t *pud) |
1da177e4 LT |
83 | { |
84 | set_pud(pud, __pud(0)); | |
85 | } | |
86 | ||
87 | static inline void set_pgd(pgd_t *dst, pgd_t val) | |
88 | { | |
7a2389b4 | 89 | *dst = val; |
1da177e4 LT |
90 | } |
91 | ||
9c0aa0f9 | 92 | static inline void pgd_clear (pgd_t * pgd) |
1da177e4 LT |
93 | { |
94 | set_pgd(pgd, __pgd(0)); | |
95 | } | |
96 | ||
195466dc | 97 | #define native_ptep_get_and_clear(xp) __pte(xchg(&(xp)->pte, 0)) |
61e06037 | 98 | |
8c65b4a6 TS |
99 | struct mm_struct; |
100 | ||
195466dc | 101 | static inline pte_t native_ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full) |
61e06037 ZA |
102 | { |
103 | pte_t pte; | |
104 | if (full) { | |
105 | pte = *ptep; | |
106 | *ptep = __pte(0); | |
107 | } else { | |
195466dc | 108 | pte = native_ptep_get_and_clear(ptep); |
61e06037 ZA |
109 | } |
110 | return pte; | |
111 | } | |
112 | ||
1da177e4 LT |
113 | #define pte_same(a, b) ((a).pte == (b).pte) |
114 | ||
c728252c AV |
115 | #define pte_pgprot(a) (__pgprot((a).pte & ~PHYSICAL_PAGE_MASK)) |
116 | ||
9d291e78 VG |
117 | #endif /* !__ASSEMBLY__ */ |
118 | ||
119 | #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) | |
1da177e4 | 120 | #define PMD_MASK (~(PMD_SIZE-1)) |
9d291e78 | 121 | #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) |
1da177e4 | 122 | #define PUD_MASK (~(PUD_SIZE-1)) |
9d291e78 | 123 | #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) |
1da177e4 LT |
124 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
125 | ||
1da177e4 | 126 | |
63f6564d RD |
127 | #define MAXMEM _AC(0x3fffffffffff, UL) |
128 | #define VMALLOC_START _AC(0xffffc20000000000, UL) | |
129 | #define VMALLOC_END _AC(0xffffe1ffffffffff, UL) | |
0889eba5 | 130 | #define VMEMMAP_START _AC(0xffffe20000000000, UL) |
63f6564d RD |
131 | #define MODULES_VADDR _AC(0xffffffff88000000, UL) |
132 | #define MODULES_END _AC(0xfffffffffff00000, UL) | |
1da177e4 LT |
133 | #define MODULES_LEN (MODULES_END - MODULES_VADDR) |
134 | ||
9d291e78 VG |
135 | #ifndef __ASSEMBLY__ |
136 | ||
eab724e5 JB |
137 | static inline unsigned long pgd_bad(pgd_t pgd) |
138 | { | |
139 | return pgd_val(pgd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER); | |
140 | } | |
1da177e4 LT |
141 | |
142 | static inline unsigned long pud_bad(pud_t pud) | |
143 | { | |
eab724e5 JB |
144 | return pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER); |
145 | } | |
146 | ||
147 | static inline unsigned long pmd_bad(pmd_t pmd) | |
148 | { | |
149 | return pmd_val(pmd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER); | |
1da177e4 LT |
150 | } |
151 | ||
152 | #define pte_none(x) (!pte_val(x)) | |
153 | #define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE)) | |
195466dc | 154 | #define native_pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) |
1da177e4 | 155 | |
1c6f7030 | 156 | #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) /* FIXME: is this right? */ |
1da177e4 | 157 | #define pte_page(x) pfn_to_page(pte_pfn(x)) |
6b75aeed | 158 | #define pte_pfn(x) ((pte_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT) |
1da177e4 | 159 | |
1da177e4 LT |
160 | /* |
161 | * Macro to mark a page protection value as "uncacheable". | |
162 | */ | |
163 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) | |
164 | ||
1da177e4 LT |
165 | |
166 | /* | |
167 | * Conversion functions: convert a page and protection to a page entry, | |
168 | * and a page entry and page directory to the page they refer to. | |
169 | */ | |
170 | ||
1da177e4 LT |
171 | /* |
172 | * Level 4 access. | |
173 | */ | |
46a82b2d DM |
174 | #define pgd_page_vaddr(pgd) ((unsigned long) __va((unsigned long)pgd_val(pgd) & PTE_MASK)) |
175 | #define pgd_page(pgd) (pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT)) | |
1da177e4 LT |
176 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
177 | #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) | |
178 | #define pgd_offset_k(address) (init_level4_pgt + pgd_index(address)) | |
179 | #define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT) | |
180 | #define mk_kernel_pgd(address) ((pgd_t){ (address) | _KERNPG_TABLE }) | |
181 | ||
182 | /* PUD - Level3 access */ | |
183 | /* to find an entry in a page-table-directory. */ | |
46a82b2d DM |
184 | #define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK)) |
185 | #define pud_page(pud) (pfn_to_page(pud_val(pud) >> PAGE_SHIFT)) | |
1da177e4 | 186 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
46a82b2d | 187 | #define pud_offset(pgd, address) ((pud_t *) pgd_page_vaddr(*(pgd)) + pud_index(address)) |
1da177e4 LT |
188 | #define pud_present(pud) (pud_val(pud) & _PAGE_PRESENT) |
189 | ||
1da177e4 | 190 | /* PMD - Level 2 access */ |
46a82b2d | 191 | #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PTE_MASK)) |
1da177e4 LT |
192 | #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) |
193 | ||
194 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
46a82b2d | 195 | #define pmd_offset(dir, address) ((pmd_t *) pud_page_vaddr(*(dir)) + \ |
1da177e4 LT |
196 | pmd_index(address)) |
197 | #define pmd_none(x) (!pmd_val(x)) | |
198 | #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) | |
199 | #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) | |
1da177e4 | 200 | #define pfn_pmd(nr,prot) (__pmd(((nr) << PAGE_SHIFT) | pgprot_val(prot))) |
6b75aeed | 201 | #define pmd_pfn(x) ((pmd_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT) |
1da177e4 LT |
202 | |
203 | #define pte_to_pgoff(pte) ((pte_val(pte) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT) | |
c8e5393a | 204 | #define pgoff_to_pte(off) ((pte_t) { .pte = ((off) << PAGE_SHIFT) | _PAGE_FILE }) |
1da177e4 LT |
205 | #define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT |
206 | ||
207 | /* PTE - Level 1 access. */ | |
208 | ||
209 | /* page, protection -> pte */ | |
210 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
1da177e4 | 211 | |
1da177e4 | 212 | #define pte_index(address) \ |
1294b118 | 213 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) |
46a82b2d | 214 | #define pte_offset_kernel(dir, address) ((pte_t *) pmd_page_vaddr(*(dir)) + \ |
1da177e4 LT |
215 | pte_index(address)) |
216 | ||
217 | /* x86-64 always has all page tables mapped. */ | |
218 | #define pte_offset_map(dir,address) pte_offset_kernel(dir,address) | |
219 | #define pte_offset_map_nested(dir,address) pte_offset_kernel(dir,address) | |
220 | #define pte_unmap(pte) /* NOP */ | |
221 | #define pte_unmap_nested(pte) /* NOP */ | |
222 | ||
223 | #define update_mmu_cache(vma,address,pte) do { } while (0) | |
224 | ||
1da177e4 LT |
225 | /* Encode and de-code a swap entry */ |
226 | #define __swp_type(x) (((x).val >> 1) & 0x3f) | |
227 | #define __swp_offset(x) ((x).val >> 8) | |
228 | #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) }) | |
229 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
c8e5393a | 230 | #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) |
1da177e4 | 231 | |
8c914cb7 | 232 | extern spinlock_t pgd_lock; |
2bff7383 | 233 | extern struct list_head pgd_list; |
8c914cb7 | 234 | |
1da177e4 LT |
235 | extern int kern_addr_valid(unsigned long addr); |
236 | ||
19d36ccd AK |
237 | pte_t *lookup_address(unsigned long addr); |
238 | ||
1da177e4 LT |
239 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ |
240 | remap_pfn_range(vma, vaddr, pfn, size, prot) | |
241 | ||
1da177e4 | 242 | #define HAVE_ARCH_UNMAPPED_AREA |
cc503c1b | 243 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN |
1da177e4 LT |
244 | |
245 | #define pgtable_cache_init() do { } while (0) | |
da8f153e | 246 | #define check_pgt_cache() do { } while (0) |
1da177e4 LT |
247 | |
248 | #define PAGE_AGP PAGE_KERNEL_NOCACHE | |
249 | #define HAVE_PAGE_AGP 1 | |
250 | ||
251 | /* fs/proc/kcore.c */ | |
252 | #define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK) | |
253 | #define kc_offset_to_vaddr(o) \ | |
254 | (((o) & (1UL << (__VIRTUAL_MASK_SHIFT-1))) ? ((o) | (~__VIRTUAL_MASK)) : (o)) | |
255 | ||
1da177e4 | 256 | #define __HAVE_ARCH_PTE_SAME |
9d291e78 | 257 | #endif /* !__ASSEMBLY__ */ |
1da177e4 LT |
258 | |
259 | #endif /* _X86_64_PGTABLE_H */ |