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x86: check vmlinux limits, 64-bit
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1da177e4
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1#ifndef _X86_64_PGTABLE_H
2#define _X86_64_PGTABLE_H
3
6df95fd7 4#include <linux/const.h>
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VG
5#ifndef __ASSEMBLY__
6
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7/*
8 * This file contains the functions and defines necessary to modify and use
9 * the x86-64 page table tree.
10 */
11#include <asm/processor.h>
1977f032 12#include <linux/bitops.h>
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13#include <linux/threads.h>
14#include <asm/pda.h>
15
16extern pud_t level3_kernel_pgt[512];
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17extern pud_t level3_ident_pgt[512];
18extern pmd_t level2_kernel_pgt[512];
19extern pgd_t init_level4_pgt[];
1da177e4 20
e3ebadd9 21#define swapper_pg_dir init_level4_pgt
1da177e4 22
1da177e4 23extern void paging_init(void);
1da177e4 24
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25#endif /* !__ASSEMBLY__ */
26
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IM
27#define SHARED_KERNEL_PMD 1
28
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29/*
30 * PGDIR_SHIFT determines what a top-level page table entry can map
31 */
32#define PGDIR_SHIFT 39
33#define PTRS_PER_PGD 512
34
35/*
36 * 3rd level page
37 */
38#define PUD_SHIFT 30
39#define PTRS_PER_PUD 512
40
41/*
42 * PMD_SHIFT determines the size of the area a middle-level
43 * page table can map
44 */
45#define PMD_SHIFT 21
46#define PTRS_PER_PMD 512
47
48/*
49 * entries per page directory level
50 */
51#define PTRS_PER_PTE 512
52
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53#ifndef __ASSEMBLY__
54
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55#define pte_ERROR(e) \
56 printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
57#define pmd_ERROR(e) \
58 printk("%s:%d: bad pmd %p(%016lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
59#define pud_ERROR(e) \
60 printk("%s:%d: bad pud %p(%016lx).\n", __FILE__, __LINE__, &(e), pud_val(e))
61#define pgd_ERROR(e) \
62 printk("%s:%d: bad pgd %p(%016lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
63
64#define pgd_none(x) (!pgd_val(x))
65#define pud_none(x) (!pud_val(x))
66
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67struct mm_struct;
68
69static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
70 pte_t *ptep)
1da177e4 71{
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72 *ptep = native_make_pte(0);
73}
1da177e4 74
4891645e 75static inline void native_set_pte(pte_t *ptep, pte_t pte)
1da177e4 76{
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77 *ptep = pte;
78}
1da177e4 79
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80static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
81{
82 native_set_pte(ptep, pte);
83}
84
4891645e 85static inline pte_t native_ptep_get_and_clear(pte_t *xp)
1da177e4 86{
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JF
87#ifdef CONFIG_SMP
88 return native_make_pte(xchg(&xp->pte, 0));
89#else
90 /* native_local_ptep_get_and_clear, but duplicated because of cyclic dependency */
91 pte_t ret = *xp;
92 native_pte_clear(NULL, 0, xp);
93 return ret;
94#endif
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95}
96
4891645e 97static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
1da177e4 98{
4891645e 99 *pmdp = pmd;
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100}
101
4891645e 102static inline void native_pmd_clear(pmd_t *pmd)
1da177e4 103{
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104 native_set_pmd(pmd, native_make_pmd(0));
105}
1da177e4 106
4891645e 107static inline void native_set_pud(pud_t *pudp, pud_t pud)
1da177e4 108{
4891645e 109 *pudp = pud;
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110}
111
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112static inline void native_pud_clear(pud_t *pud)
113{
114 native_set_pud(pud, native_make_pud(0));
115}
61e06037 116
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117static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
118{
119 *pgdp = pgd;
120}
8c65b4a6 121
4891645e 122static inline void native_pgd_clear(pgd_t * pgd)
61e06037 123{
4891645e 124 native_set_pgd(pgd, native_make_pgd(0));
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125}
126
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127#define pte_same(a, b) ((a).pte == (b).pte)
128
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129#endif /* !__ASSEMBLY__ */
130
131#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
1da177e4 132#define PMD_MASK (~(PMD_SIZE-1))
9d291e78 133#define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
1da177e4 134#define PUD_MASK (~(PUD_SIZE-1))
9d291e78 135#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
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136#define PGDIR_MASK (~(PGDIR_SIZE-1))
137
1da177e4 138
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139#define MAXMEM _AC(0x3fffffffffff, UL)
140#define VMALLOC_START _AC(0xffffc20000000000, UL)
141#define VMALLOC_END _AC(0xffffe1ffffffffff, UL)
0889eba5 142#define VMEMMAP_START _AC(0xffffe20000000000, UL)
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143#define MODULES_VADDR _AC(0xffffffff88000000, UL)
144#define MODULES_END _AC(0xfffffffffff00000, UL)
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145#define MODULES_LEN (MODULES_END - MODULES_VADDR)
146
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147#ifndef __ASSEMBLY__
148
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JB
149static inline unsigned long pgd_bad(pgd_t pgd)
150{
151 return pgd_val(pgd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
152}
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153
154static inline unsigned long pud_bad(pud_t pud)
155{
a345b4ba 156 return pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
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JB
157}
158
159static inline unsigned long pmd_bad(pmd_t pmd)
160{
a345b4ba 161 return pmd_val(pmd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
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162}
163
164#define pte_none(x) (!pte_val(x))
165#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
1da177e4 166
1c6f7030 167#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) /* FIXME: is this right? */
1da177e4 168#define pte_page(x) pfn_to_page(pte_pfn(x))
6b75aeed 169#define pte_pfn(x) ((pte_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
1da177e4 170
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171/*
172 * Macro to mark a page protection value as "uncacheable".
173 */
174#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT))
175
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176
177/*
178 * Conversion functions: convert a page and protection to a page entry,
179 * and a page entry and page directory to the page they refer to.
180 */
181
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182/*
183 * Level 4 access.
184 */
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DM
185#define pgd_page_vaddr(pgd) ((unsigned long) __va((unsigned long)pgd_val(pgd) & PTE_MASK))
186#define pgd_page(pgd) (pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT))
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187#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
188#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
189#define pgd_offset_k(address) (init_level4_pgt + pgd_index(address))
190#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT)
e00fc542 191static inline int pgd_large(pgd_t pgd) { return 0; }
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192#define mk_kernel_pgd(address) ((pgd_t){ (address) | _KERNPG_TABLE })
193
194/* PUD - Level3 access */
195/* to find an entry in a page-table-directory. */
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DM
196#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK))
197#define pud_page(pud) (pfn_to_page(pud_val(pud) >> PAGE_SHIFT))
1da177e4 198#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
46a82b2d 199#define pud_offset(pgd, address) ((pud_t *) pgd_page_vaddr(*(pgd)) + pud_index(address))
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200#define pud_present(pud) (pud_val(pud) & _PAGE_PRESENT)
201
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AK
202static inline int pud_large(pud_t pte)
203{
204 return (pud_val(pte) & (_PAGE_PSE|_PAGE_PRESENT)) ==
205 (_PAGE_PSE|_PAGE_PRESENT);
206}
207
1da177e4 208/* PMD - Level 2 access */
46a82b2d 209#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PTE_MASK))
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LT
210#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
211
212#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
46a82b2d 213#define pmd_offset(dir, address) ((pmd_t *) pud_page_vaddr(*(dir)) + \
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214 pmd_index(address))
215#define pmd_none(x) (!pmd_val(x))
216#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
1da177e4 217#define pfn_pmd(nr,prot) (__pmd(((nr) << PAGE_SHIFT) | pgprot_val(prot)))
6b75aeed 218#define pmd_pfn(x) ((pmd_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
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219
220#define pte_to_pgoff(pte) ((pte_val(pte) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
c8e5393a 221#define pgoff_to_pte(off) ((pte_t) { .pte = ((off) << PAGE_SHIFT) | _PAGE_FILE })
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222#define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT
223
224/* PTE - Level 1 access. */
225
226/* page, protection -> pte */
227#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
1da177e4 228
1da177e4 229#define pte_index(address) \
1294b118 230 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
46a82b2d 231#define pte_offset_kernel(dir, address) ((pte_t *) pmd_page_vaddr(*(dir)) + \
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LT
232 pte_index(address))
233
234/* x86-64 always has all page tables mapped. */
235#define pte_offset_map(dir,address) pte_offset_kernel(dir,address)
236#define pte_offset_map_nested(dir,address) pte_offset_kernel(dir,address)
237#define pte_unmap(pte) /* NOP */
238#define pte_unmap_nested(pte) /* NOP */
239
240#define update_mmu_cache(vma,address,pte) do { } while (0)
241
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242/* Encode and de-code a swap entry */
243#define __swp_type(x) (((x).val >> 1) & 0x3f)
244#define __swp_offset(x) ((x).val >> 8)
245#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
246#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
c8e5393a 247#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
1da177e4 248
1da177e4 249extern int kern_addr_valid(unsigned long addr);
31eedd82 250extern void cleanup_highmap(void);
1da177e4 251
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LT
252#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
253 remap_pfn_range(vma, vaddr, pfn, size, prot)
254
1da177e4 255#define HAVE_ARCH_UNMAPPED_AREA
cc503c1b 256#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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LT
257
258#define pgtable_cache_init() do { } while (0)
da8f153e 259#define check_pgt_cache() do { } while (0)
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260
261#define PAGE_AGP PAGE_KERNEL_NOCACHE
262#define HAVE_PAGE_AGP 1
263
264/* fs/proc/kcore.c */
265#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
266#define kc_offset_to_vaddr(o) \
267 (((o) & (1UL << (__VIRTUAL_MASK_SHIFT-1))) ? ((o) | (~__VIRTUAL_MASK)) : (o))
268
1da177e4 269#define __HAVE_ARCH_PTE_SAME
9d291e78 270#endif /* !__ASSEMBLY__ */
1da177e4
LT
271
272#endif /* _X86_64_PGTABLE_H */