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1da177e4
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1#ifndef __ASM_SMP_H
2#define __ASM_SMP_H
3
4/*
5 * We need the APIC definitions automatically as part of 'smp.h'
6 */
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7#include <linux/threads.h>
8#include <linux/cpumask.h>
9#include <linux/bitops.h>
43999d9e 10#include <linux/init.h>
1da177e4 11extern int disable_apic;
1da177e4 12
1da177e4 13#include <asm/mpspec.h>
1da177e4 14#include <asm/apic.h>
00f1ea69 15#include <asm/io_apic.h>
1da177e4 16#include <asm/thread_info.h>
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17
18#ifdef CONFIG_SMP
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19
20#include <asm/pda.h>
21
22struct pt_regs;
23
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24extern cpumask_t cpu_present_mask;
25extern cpumask_t cpu_possible_map;
26extern cpumask_t cpu_online_map;
27extern cpumask_t cpu_callout_map;
3c021751 28extern cpumask_t cpu_initialized;
a8ab26fe 29
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30/*
31 * Private routines/data
32 */
33
34extern void smp_alloc_memory(void);
1da177e4 35extern volatile unsigned long smp_invalidate_needed;
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36extern void lock_ipi_call_lock(void);
37extern void unlock_ipi_call_lock(void);
1da177e4 38extern int smp_num_siblings;
1da177e4 39extern void smp_send_reschedule(int cpu);
3d483f47 40
08357611 41/*
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42 * cpu_sibling_map and cpu_core_map now live
43 * in the per cpu area
08357611 44 *
d5a7430d 45 * extern cpumask_t cpu_sibling_map[NR_CPUS];
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MT
46 * extern cpumask_t cpu_core_map[NR_CPUS];
47 */
d5a7430d 48DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
08357611 49DECLARE_PER_CPU(cpumask_t, cpu_core_map);
1e9f28fa 50extern u8 cpu_llc_id[NR_CPUS];
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51
52#define SMP_TRAMPOLINE_BASE 0x6000
53
54/*
55 * On x86 all CPUs are mapped 1:1 to the APIC space.
56 * This simplifies scheduling and IPI sending and
57 * compresses data structures.
58 */
59
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60static inline int num_booting_cpus(void)
61{
62 return cpus_weight(cpu_callout_map);
63}
64
39c715b7 65#define raw_smp_processor_id() read_pda(cpunumber)
1da177e4 66
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67extern int __cpu_disable(void);
68extern void __cpu_die(unsigned int cpu);
421c7ce6 69extern void prefill_possible_map(void);
420f8f68 70extern unsigned num_processors;
43999d9e 71extern unsigned __cpuinitdata disabled_cpus;
1da177e4 72
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73#define NO_PROC_ID 0xFF /* No processor magic marker */
74
2f4dfe20 75#endif /* CONFIG_SMP */
1da177e4 76
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77static inline int hard_smp_processor_id(void)
78{
79 /* we don't want to mark this access volatile - bad code generation */
80 return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
81}
82
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83/*
84 * Some lowlevel functions might want to know about
85 * the real APIC ID <-> CPU # mapping.
86 */
87extern u8 x86_cpu_to_apicid[NR_CPUS]; /* physical ID */
88extern u8 x86_cpu_to_log_apicid[NR_CPUS];
89extern u8 bios_cpu_apicid[];
90
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91static inline int cpu_present_to_apicid(int mps_cpu)
92{
93 if (mps_cpu < NR_CPUS)
94 return (int)bios_cpu_apicid[mps_cpu];
95 else
96 return BAD_APICID;
97}
98
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99#ifndef CONFIG_SMP
100#define stack_smp_processor_id() 0
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101#define cpu_logical_map(x) (x)
102#else
103#include <asm/thread_info.h>
104#define stack_smp_processor_id() \
105({ \
106 struct thread_info *ti; \
107 __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
108 ti->cpu; \
109})
110#endif
111
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112static __inline int logical_smp_processor_id(void)
113{
114 /* we don't want to mark this access volatile - bad code generation */
115 return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
116}
1da177e4 117
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118#ifdef CONFIG_SMP
119#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu]
120#else
121#define cpu_physical_id(cpu) boot_cpu_id
c08c8205 122#endif /* !CONFIG_SMP */
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123#endif
124