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1da177e4 LT |
1 | #ifndef _ASM_IO_H |
2 | #define _ASM_IO_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | ||
6 | /* | |
7 | * This file contains the definitions for the x86 IO instructions | |
8 | * inb/inw/inl/outb/outw/outl and the "string versions" of the same | |
9 | * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" | |
10 | * versions of the single-IO instructions (inb_p/inw_p/..). | |
11 | * | |
12 | * This file is not meant to be obfuscating: it's just complicated | |
13 | * to (a) handle it all in a way that makes gcc able to optimize it | |
14 | * as well as possible and (b) trying to avoid writing the same thing | |
15 | * over and over again with slight variations and possibly making a | |
16 | * mistake somewhere. | |
17 | */ | |
18 | ||
19 | /* | |
20 | * Thanks to James van Artsdalen for a better timing-fix than | |
21 | * the two short jumps: using outb's to a nonexistent port seems | |
22 | * to guarantee better timings even on fast machines. | |
23 | * | |
24 | * On the other hand, I'd like to be sure of a non-existent port: | |
25 | * I feel a bit unsafe about using 0x80 (should be safe, though) | |
26 | * | |
27 | * Linus | |
28 | */ | |
29 | ||
30 | /* | |
31 | * Bit simplified and optimized by Jan Hubicka | |
32 | * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. | |
33 | * | |
34 | * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, | |
35 | * isa_read[wl] and isa_write[wl] fixed | |
36 | * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> | |
37 | */ | |
38 | ||
39 | #define __SLOW_DOWN_IO "\noutb %%al,$0x80" | |
40 | ||
41 | #ifdef REALLY_SLOW_IO | |
42 | #define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO | |
43 | #else | |
44 | #define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO | |
45 | #endif | |
46 | ||
47 | /* | |
48 | * Talk about misusing macros.. | |
49 | */ | |
50 | #define __OUT1(s,x) \ | |
9c0aa0f9 | 51 | static inline void out##s(unsigned x value, unsigned short port) { |
1da177e4 LT |
52 | |
53 | #define __OUT2(s,s1,s2) \ | |
54 | __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1" | |
55 | ||
56 | #define __OUT(s,s1,x) \ | |
57 | __OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \ | |
58 | __OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} \ | |
59 | ||
60 | #define __IN1(s) \ | |
9c0aa0f9 | 61 | static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v; |
1da177e4 LT |
62 | |
63 | #define __IN2(s,s1,s2) \ | |
64 | __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0" | |
65 | ||
66 | #define __IN(s,s1,i...) \ | |
67 | __IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \ | |
68 | __IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \ | |
69 | ||
70 | #define __INS(s) \ | |
9c0aa0f9 | 71 | static inline void ins##s(unsigned short port, void * addr, unsigned long count) \ |
1da177e4 LT |
72 | { __asm__ __volatile__ ("rep ; ins" #s \ |
73 | : "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } | |
74 | ||
75 | #define __OUTS(s) \ | |
9c0aa0f9 | 76 | static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \ |
1da177e4 LT |
77 | { __asm__ __volatile__ ("rep ; outs" #s \ |
78 | : "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } | |
79 | ||
80 | #define RETURN_TYPE unsigned char | |
81 | __IN(b,"") | |
82 | #undef RETURN_TYPE | |
83 | #define RETURN_TYPE unsigned short | |
84 | __IN(w,"") | |
85 | #undef RETURN_TYPE | |
86 | #define RETURN_TYPE unsigned int | |
87 | __IN(l,"") | |
88 | #undef RETURN_TYPE | |
89 | ||
90 | __OUT(b,"b",char) | |
91 | __OUT(w,"w",short) | |
92 | __OUT(l,,int) | |
93 | ||
94 | __INS(b) | |
95 | __INS(w) | |
96 | __INS(l) | |
97 | ||
98 | __OUTS(b) | |
99 | __OUTS(w) | |
100 | __OUTS(l) | |
101 | ||
102 | #define IO_SPACE_LIMIT 0xffff | |
103 | ||
104 | #if defined(__KERNEL__) && __x86_64__ | |
105 | ||
106 | #include <linux/vmalloc.h> | |
107 | ||
108 | #ifndef __i386__ | |
109 | /* | |
110 | * Change virtual addresses to physical addresses and vv. | |
111 | * These are pretty trivial | |
112 | */ | |
9c0aa0f9 | 113 | static inline unsigned long virt_to_phys(volatile void * address) |
1da177e4 LT |
114 | { |
115 | return __pa(address); | |
116 | } | |
117 | ||
9c0aa0f9 | 118 | static inline void * phys_to_virt(unsigned long address) |
1da177e4 LT |
119 | { |
120 | return __va(address); | |
121 | } | |
122 | #endif | |
123 | ||
124 | /* | |
125 | * Change "struct page" to physical address. | |
126 | */ | |
1da177e4 | 127 | #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) |
1da177e4 LT |
128 | |
129 | #include <asm-generic/iomap.h> | |
130 | ||
131 | extern void __iomem *__ioremap(unsigned long offset, unsigned long size, unsigned long flags); | |
132 | ||
9c0aa0f9 | 133 | static inline void __iomem * ioremap (unsigned long offset, unsigned long size) |
1da177e4 LT |
134 | { |
135 | return __ioremap(offset, size, 0); | |
136 | } | |
137 | ||
138 | /* | |
139 | * This one maps high address device memory and turns off caching for that area. | |
140 | * it's useful if some control registers are in such an area and write combining | |
141 | * or read caching is not desirable: | |
142 | */ | |
143 | extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); | |
144 | extern void iounmap(volatile void __iomem *addr); | |
145 | ||
e9928674 AK |
146 | /* Use normal IO mappings for DMI */ |
147 | #define dmi_ioremap ioremap | |
148 | #define dmi_iounmap(x,l) iounmap(x) | |
149 | #define dmi_alloc(l) kmalloc(l, GFP_ATOMIC) | |
150 | ||
1da177e4 LT |
151 | /* |
152 | * ISA I/O bus memory addresses are 1:1 with the physical address. | |
153 | */ | |
154 | #define isa_virt_to_bus virt_to_phys | |
155 | #define isa_page_to_bus page_to_phys | |
156 | #define isa_bus_to_virt phys_to_virt | |
157 | ||
158 | /* | |
159 | * However PCI ones are not necessarily 1:1 and therefore these interfaces | |
160 | * are forbidden in portable PCI drivers. | |
161 | * | |
162 | * Allow them on x86 for legacy drivers, though. | |
163 | */ | |
164 | #define virt_to_bus virt_to_phys | |
165 | #define bus_to_virt phys_to_virt | |
166 | ||
167 | /* | |
168 | * readX/writeX() are used to access memory mapped devices. On some | |
169 | * architectures the memory mapped IO stuff needs to be accessed | |
170 | * differently. On the x86 architecture, we just read/write the | |
171 | * memory location directly. | |
172 | */ | |
173 | ||
174 | static inline __u8 __readb(const volatile void __iomem *addr) | |
175 | { | |
176 | return *(__force volatile __u8 *)addr; | |
177 | } | |
178 | static inline __u16 __readw(const volatile void __iomem *addr) | |
179 | { | |
180 | return *(__force volatile __u16 *)addr; | |
181 | } | |
182 | static inline __u32 __readl(const volatile void __iomem *addr) | |
183 | { | |
184 | return *(__force volatile __u32 *)addr; | |
185 | } | |
186 | static inline __u64 __readq(const volatile void __iomem *addr) | |
187 | { | |
188 | return *(__force volatile __u64 *)addr; | |
189 | } | |
190 | #define readb(x) __readb(x) | |
191 | #define readw(x) __readw(x) | |
192 | #define readl(x) __readl(x) | |
193 | #define readq(x) __readq(x) | |
194 | #define readb_relaxed(a) readb(a) | |
195 | #define readw_relaxed(a) readw(a) | |
196 | #define readl_relaxed(a) readl(a) | |
197 | #define readq_relaxed(a) readq(a) | |
198 | #define __raw_readb readb | |
199 | #define __raw_readw readw | |
200 | #define __raw_readl readl | |
201 | #define __raw_readq readq | |
202 | ||
203 | #define mmiowb() | |
204 | ||
205 | #ifdef CONFIG_UNORDERED_IO | |
206 | static inline void __writel(__u32 val, volatile void __iomem *addr) | |
207 | { | |
208 | volatile __u32 __iomem *target = addr; | |
209 | asm volatile("movnti %1,%0" | |
210 | : "=m" (*target) | |
211 | : "r" (val) : "memory"); | |
212 | } | |
213 | ||
214 | static inline void __writeq(__u64 val, volatile void __iomem *addr) | |
215 | { | |
216 | volatile __u64 __iomem *target = addr; | |
217 | asm volatile("movnti %1,%0" | |
218 | : "=m" (*target) | |
219 | : "r" (val) : "memory"); | |
220 | } | |
221 | #else | |
222 | static inline void __writel(__u32 b, volatile void __iomem *addr) | |
223 | { | |
224 | *(__force volatile __u32 *)addr = b; | |
225 | } | |
226 | static inline void __writeq(__u64 b, volatile void __iomem *addr) | |
227 | { | |
228 | *(__force volatile __u64 *)addr = b; | |
229 | } | |
230 | #endif | |
231 | static inline void __writeb(__u8 b, volatile void __iomem *addr) | |
232 | { | |
233 | *(__force volatile __u8 *)addr = b; | |
234 | } | |
235 | static inline void __writew(__u16 b, volatile void __iomem *addr) | |
236 | { | |
237 | *(__force volatile __u16 *)addr = b; | |
238 | } | |
239 | #define writeq(val,addr) __writeq((val),(addr)) | |
240 | #define writel(val,addr) __writel((val),(addr)) | |
241 | #define writew(val,addr) __writew((val),(addr)) | |
242 | #define writeb(val,addr) __writeb((val),(addr)) | |
243 | #define __raw_writeb writeb | |
244 | #define __raw_writew writew | |
245 | #define __raw_writel writel | |
246 | #define __raw_writeq writeq | |
247 | ||
248 | void __memcpy_fromio(void*,unsigned long,unsigned); | |
249 | void __memcpy_toio(unsigned long,const void*,unsigned); | |
250 | ||
251 | static inline void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned len) | |
252 | { | |
253 | __memcpy_fromio(to,(unsigned long)from,len); | |
254 | } | |
255 | static inline void memcpy_toio(volatile void __iomem *to, const void *from, unsigned len) | |
256 | { | |
257 | __memcpy_toio((unsigned long)to,from,len); | |
258 | } | |
259 | ||
260 | void memset_io(volatile void __iomem *a, int b, size_t c); | |
261 | ||
262 | /* | |
263 | * ISA space is 'always mapped' on a typical x86 system, no need to | |
264 | * explicitly ioremap() it. The fact that the ISA IO space is mapped | |
265 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values | |
266 | * are physical addresses. The following constant pointer can be | |
267 | * used as the IO-area pointer (it can be iounmapped as well, so the | |
268 | * analogy with PCI is quite large): | |
269 | */ | |
270 | #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) | |
271 | ||
1da177e4 LT |
272 | /* |
273 | * Again, x86-64 does not require mem IO specific function. | |
274 | */ | |
275 | ||
276 | #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d)) | |
1da177e4 LT |
277 | |
278 | /** | |
279 | * check_signature - find BIOS signatures | |
280 | * @io_addr: mmio address to check | |
281 | * @signature: signature block | |
282 | * @length: length of signature | |
283 | * | |
284 | * Perform a signature comparison with the mmio address io_addr. This | |
285 | * address should have been obtained by ioremap. | |
286 | * Returns 1 on a match. | |
287 | */ | |
288 | ||
289 | static inline int check_signature(void __iomem *io_addr, | |
290 | const unsigned char *signature, int length) | |
291 | { | |
292 | int retval = 0; | |
293 | do { | |
294 | if (readb(io_addr) != *signature) | |
295 | goto out; | |
296 | io_addr++; | |
297 | signature++; | |
298 | length--; | |
299 | } while (length); | |
300 | retval = 1; | |
301 | out: | |
302 | return retval; | |
303 | } | |
304 | ||
305 | /* Nothing to do */ | |
306 | ||
307 | #define dma_cache_inv(_start,_size) do { } while (0) | |
308 | #define dma_cache_wback(_start,_size) do { } while (0) | |
309 | #define dma_cache_wback_inv(_start,_size) do { } while (0) | |
310 | ||
311 | #define flush_write_buffers() | |
312 | ||
313 | extern int iommu_bio_merge; | |
314 | #define BIO_VMERGE_BOUNDARY iommu_bio_merge | |
315 | ||
316 | /* | |
317 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
318 | * access | |
319 | */ | |
320 | #define xlate_dev_mem_ptr(p) __va(p) | |
321 | ||
322 | /* | |
323 | * Convert a virtual cached pointer to an uncached pointer | |
324 | */ | |
325 | #define xlate_dev_kmem_ptr(p) p | |
326 | ||
327 | #endif /* __KERNEL__ */ | |
328 | ||
329 | #endif |