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1da177e4 LT |
1 | #ifndef __ASM_MPSPEC_H |
2 | #define __ASM_MPSPEC_H | |
3 | ||
4 | /* | |
5 | * Structure definitions for SMP machines following the | |
6 | * Intel Multiprocessing Specification 1.1 and 1.4. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * This tag identifies where the SMP configuration | |
11 | * information is. | |
12 | */ | |
13 | ||
14 | #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') | |
15 | ||
16 | /* | |
17 | * A maximum of 255 APICs with the current APIC ID architecture. | |
18 | */ | |
8893166f | 19 | #define MAX_APICS 255 |
1da177e4 LT |
20 | |
21 | struct intel_mp_floating | |
22 | { | |
23 | char mpf_signature[4]; /* "_MP_" */ | |
24 | unsigned int mpf_physptr; /* Configuration table address */ | |
25 | unsigned char mpf_length; /* Our length (paragraphs) */ | |
26 | unsigned char mpf_specification;/* Specification version */ | |
27 | unsigned char mpf_checksum; /* Checksum (makes sum 0) */ | |
28 | unsigned char mpf_feature1; /* Standard or configuration ? */ | |
29 | unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ | |
30 | unsigned char mpf_feature3; /* Unused (0) */ | |
31 | unsigned char mpf_feature4; /* Unused (0) */ | |
32 | unsigned char mpf_feature5; /* Unused (0) */ | |
33 | }; | |
34 | ||
35 | struct mp_config_table | |
36 | { | |
37 | char mpc_signature[4]; | |
38 | #define MPC_SIGNATURE "PCMP" | |
39 | unsigned short mpc_length; /* Size of table */ | |
40 | char mpc_spec; /* 0x01 */ | |
41 | char mpc_checksum; | |
42 | char mpc_oem[8]; | |
43 | char mpc_productid[12]; | |
44 | unsigned int mpc_oemptr; /* 0 if not present */ | |
45 | unsigned short mpc_oemsize; /* 0 if not present */ | |
46 | unsigned short mpc_oemcount; | |
47 | unsigned int mpc_lapic; /* APIC address */ | |
48 | unsigned int reserved; | |
49 | }; | |
50 | ||
51 | /* Followed by entries */ | |
52 | ||
53 | #define MP_PROCESSOR 0 | |
54 | #define MP_BUS 1 | |
55 | #define MP_IOAPIC 2 | |
56 | #define MP_INTSRC 3 | |
57 | #define MP_LINTSRC 4 | |
58 | ||
59 | struct mpc_config_processor | |
60 | { | |
61 | unsigned char mpc_type; | |
62 | unsigned char mpc_apicid; /* Local APIC number */ | |
63 | unsigned char mpc_apicver; /* Its versions */ | |
64 | unsigned char mpc_cpuflag; | |
65 | #define CPU_ENABLED 1 /* Processor is available */ | |
66 | #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */ | |
67 | unsigned int mpc_cpufeature; | |
68 | #define CPU_STEPPING_MASK 0x0F | |
69 | #define CPU_MODEL_MASK 0xF0 | |
70 | #define CPU_FAMILY_MASK 0xF00 | |
71 | unsigned int mpc_featureflag; /* CPUID feature value */ | |
72 | unsigned int mpc_reserved[2]; | |
73 | }; | |
74 | ||
75 | struct mpc_config_bus | |
76 | { | |
77 | unsigned char mpc_type; | |
78 | unsigned char mpc_busid; | |
19d53484 | 79 | unsigned char mpc_bustype[6]; |
1da177e4 LT |
80 | }; |
81 | ||
82 | /* List of Bus Type string values, Intel MP Spec. */ | |
83 | #define BUSTYPE_EISA "EISA" | |
84 | #define BUSTYPE_ISA "ISA" | |
85 | #define BUSTYPE_INTERN "INTERN" /* Internal BUS */ | |
86 | #define BUSTYPE_MCA "MCA" | |
87 | #define BUSTYPE_VL "VL" /* Local bus */ | |
88 | #define BUSTYPE_PCI "PCI" | |
89 | #define BUSTYPE_PCMCIA "PCMCIA" | |
90 | #define BUSTYPE_CBUS "CBUS" | |
91 | #define BUSTYPE_CBUSII "CBUSII" | |
92 | #define BUSTYPE_FUTURE "FUTURE" | |
93 | #define BUSTYPE_MBI "MBI" | |
94 | #define BUSTYPE_MBII "MBII" | |
95 | #define BUSTYPE_MPI "MPI" | |
96 | #define BUSTYPE_MPSA "MPSA" | |
97 | #define BUSTYPE_NUBUS "NUBUS" | |
98 | #define BUSTYPE_TC "TC" | |
99 | #define BUSTYPE_VME "VME" | |
100 | #define BUSTYPE_XPRESS "XPRESS" | |
101 | ||
102 | struct mpc_config_ioapic | |
103 | { | |
104 | unsigned char mpc_type; | |
105 | unsigned char mpc_apicid; | |
106 | unsigned char mpc_apicver; | |
107 | unsigned char mpc_flags; | |
108 | #define MPC_APIC_USABLE 0x01 | |
109 | unsigned int mpc_apicaddr; | |
110 | }; | |
111 | ||
112 | struct mpc_config_intsrc | |
113 | { | |
114 | unsigned char mpc_type; | |
115 | unsigned char mpc_irqtype; | |
116 | unsigned short mpc_irqflag; | |
117 | unsigned char mpc_srcbus; | |
118 | unsigned char mpc_srcbusirq; | |
119 | unsigned char mpc_dstapic; | |
120 | unsigned char mpc_dstirq; | |
121 | }; | |
122 | ||
123 | enum mp_irq_source_types { | |
124 | mp_INT = 0, | |
125 | mp_NMI = 1, | |
126 | mp_SMI = 2, | |
127 | mp_ExtINT = 3 | |
128 | }; | |
129 | ||
130 | #define MP_IRQDIR_DEFAULT 0 | |
131 | #define MP_IRQDIR_HIGH 1 | |
132 | #define MP_IRQDIR_LOW 3 | |
133 | ||
134 | ||
135 | struct mpc_config_lintsrc | |
136 | { | |
137 | unsigned char mpc_type; | |
138 | unsigned char mpc_irqtype; | |
139 | unsigned short mpc_irqflag; | |
140 | unsigned char mpc_srcbusid; | |
141 | unsigned char mpc_srcbusirq; | |
142 | unsigned char mpc_destapic; | |
143 | #define MP_APIC_ALL 0xFF | |
144 | unsigned char mpc_destapiclint; | |
145 | }; | |
146 | ||
147 | /* | |
148 | * Default configurations | |
149 | * | |
150 | * 1 2 CPU ISA 82489DX | |
151 | * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining | |
152 | * 3 2 CPU EISA 82489DX | |
153 | * 4 2 CPU MCA 82489DX | |
154 | * 5 2 CPU ISA+PCI | |
155 | * 6 2 CPU EISA+PCI | |
156 | * 7 2 CPU MCA+PCI | |
157 | */ | |
158 | ||
159 | #define MAX_MP_BUSSES 256 | |
6004e1b7 JC |
160 | /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ |
161 | #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) | |
55f05ffa | 162 | extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 LT |
163 | extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; |
164 | ||
165 | extern unsigned int boot_cpu_physical_apicid; | |
166 | extern int smp_found_config; | |
167 | extern void find_smp_config (void); | |
168 | extern void get_smp_config (void); | |
169 | extern int nr_ioapics; | |
8893166f | 170 | extern unsigned char apic_version [MAX_APICS]; |
1da177e4 LT |
171 | extern int mp_irq_entries; |
172 | extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; | |
173 | extern int mpc_default_type; | |
174 | extern unsigned long mp_lapic_addr; | |
1da177e4 | 175 | |
888ba6c6 | 176 | #ifdef CONFIG_ACPI |
1da177e4 LT |
177 | extern void mp_register_lapic (u8 id, u8 enabled); |
178 | extern void mp_register_lapic_address (u64 address); | |
179 | ||
1da177e4 LT |
180 | extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base); |
181 | extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); | |
182 | extern void mp_config_acpi_legacy_irqs (void); | |
50eca3eb | 183 | extern int mp_register_gsi (u32 gsi, int triggering, int polarity); |
1da177e4 LT |
184 | #endif |
185 | ||
186 | extern int using_apic_timer; | |
187 | ||
188 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
189 | ||
190 | struct physid_mask | |
191 | { | |
192 | unsigned long mask[PHYSID_ARRAY_SIZE]; | |
193 | }; | |
194 | ||
195 | typedef struct physid_mask physid_mask_t; | |
196 | ||
197 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
198 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
199 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
200 | #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask) | |
201 | ||
202 | #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
203 | #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
204 | #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS) | |
205 | #define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS) | |
206 | #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS) | |
207 | #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS) | |
208 | #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS) | |
209 | #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) | |
210 | #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) | |
211 | #define physids_coerce(map) ((map).mask[0]) | |
212 | ||
213 | #define physids_promote(physids) \ | |
214 | ({ \ | |
215 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
216 | __physid_mask.mask[0] = physids; \ | |
217 | __physid_mask; \ | |
218 | }) | |
219 | ||
220 | #define physid_mask_of_physid(physid) \ | |
221 | ({ \ | |
222 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
223 | physid_set(physid, __physid_mask); \ | |
224 | __physid_mask; \ | |
225 | }) | |
226 | ||
227 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
228 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
229 | ||
230 | extern physid_mask_t phys_cpu_present_map; | |
231 | ||
232 | #endif | |
233 |