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1#ifndef __ASM_SMP_H
2#define __ASM_SMP_H
3
4/*
5 * We need the APIC definitions automatically as part of 'smp.h'
6 */
7#ifndef __ASSEMBLY__
8#include <linux/config.h>
9#include <linux/threads.h>
10#include <linux/cpumask.h>
11#include <linux/bitops.h>
12extern int disable_apic;
13#endif
14
15#ifdef CONFIG_X86_LOCAL_APIC
16#ifndef __ASSEMBLY__
17#include <asm/fixmap.h>
18#include <asm/mpspec.h>
19#ifdef CONFIG_X86_IO_APIC
20#include <asm/io_apic.h>
21#endif
22#include <asm/apic.h>
23#include <asm/thread_info.h>
24#endif
25#endif
26
27#ifdef CONFIG_SMP
28#ifndef ASSEMBLY
29
30#include <asm/pda.h>
31
32struct pt_regs;
33
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34extern cpumask_t cpu_present_mask;
35extern cpumask_t cpu_possible_map;
36extern cpumask_t cpu_online_map;
37extern cpumask_t cpu_callout_map;
38
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39/*
40 * Private routines/data
41 */
42
43extern void smp_alloc_memory(void);
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44extern volatile unsigned long smp_invalidate_needed;
45extern int pic_mode;
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46extern void lock_ipi_call_lock(void);
47extern void unlock_ipi_call_lock(void);
1da177e4 48extern int smp_num_siblings;
1da177e4 49extern void smp_send_reschedule(int cpu);
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50extern void zap_low_mappings(void);
51void smp_stop_cpu(void);
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52extern int smp_call_function_single(int cpuid, void (*func) (void *info),
53 void *info, int retry, int wait);
54
1da177e4 55extern cpumask_t cpu_sibling_map[NR_CPUS];
3dd9d514 56extern cpumask_t cpu_core_map[NR_CPUS];
1da177e4 57extern u8 phys_proc_id[NR_CPUS];
3dd9d514 58extern u8 cpu_core_id[NR_CPUS];
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59
60#define SMP_TRAMPOLINE_BASE 0x6000
61
62/*
63 * On x86 all CPUs are mapped 1:1 to the APIC space.
64 * This simplifies scheduling and IPI sending and
65 * compresses data structures.
66 */
67
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68static inline int num_booting_cpus(void)
69{
70 return cpus_weight(cpu_callout_map);
71}
72
39c715b7 73#define raw_smp_processor_id() read_pda(cpunumber)
1da177e4 74
9c0aa0f9 75static inline int hard_smp_processor_id(void)
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76{
77 /* we don't want to mark this access volatile - bad code generation */
78 return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
79}
80
a8ab26fe 81extern int safe_smp_processor_id(void);
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82extern int __cpu_disable(void);
83extern void __cpu_die(unsigned int cpu);
421c7ce6 84extern void prefill_possible_map(void);
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85
86#endif /* !ASSEMBLY */
87
88#define NO_PROC_ID 0xFF /* No processor magic marker */
89
90#endif
91
92#ifndef ASSEMBLY
93/*
94 * Some lowlevel functions might want to know about
95 * the real APIC ID <-> CPU # mapping.
96 */
97extern u8 x86_cpu_to_apicid[NR_CPUS]; /* physical ID */
98extern u8 x86_cpu_to_log_apicid[NR_CPUS];
99extern u8 bios_cpu_apicid[];
100
101static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
102{
103 return cpus_addr(cpumask)[0];
104}
105
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106static inline int cpu_present_to_apicid(int mps_cpu)
107{
108 if (mps_cpu < NR_CPUS)
109 return (int)bios_cpu_apicid[mps_cpu];
110 else
111 return BAD_APICID;
112}
113
114#endif /* !ASSEMBLY */
115
116#ifndef CONFIG_SMP
117#define stack_smp_processor_id() 0
118#define safe_smp_processor_id() 0
119#define cpu_logical_map(x) (x)
120#else
121#include <asm/thread_info.h>
122#define stack_smp_processor_id() \
123({ \
124 struct thread_info *ti; \
125 __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
126 ti->cpu; \
127})
128#endif
129
130#ifndef __ASSEMBLY__
131static __inline int logical_smp_processor_id(void)
132{
133 /* we don't want to mark this access volatile - bad code generation */
134 return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
135}
136#endif
137
138#endif
139