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1da177e4 LT |
1 | #ifndef __ASM_SPINLOCK_H |
2 | #define __ASM_SPINLOCK_H | |
3 | ||
4 | #include <asm/atomic.h> | |
5 | #include <asm/rwlock.h> | |
6 | #include <asm/page.h> | |
2bd0cfbd | 7 | #include <asm/processor.h> |
1da177e4 | 8 | |
1da177e4 LT |
9 | /* |
10 | * Your basic SMP spinlocks, allowing only a single CPU anywhere | |
fb1c8f93 | 11 | * |
1da177e4 LT |
12 | * Simple spin lock operations. There are two variants, one clears IRQ's |
13 | * on the local processor, one does not. | |
14 | * | |
15 | * We make no fairness assumptions. They have a cost. | |
fb1c8f93 IM |
16 | * |
17 | * (the type definitions are in asm/spinlock_types.h) | |
1da177e4 LT |
18 | */ |
19 | ||
8b059d23 AK |
20 | static inline int __raw_spin_is_locked(raw_spinlock_t *lock) |
21 | { | |
22 | return *(volatile signed int *)(&(lock)->slock) <= 0; | |
23 | } | |
1da177e4 | 24 | |
fb1c8f93 | 25 | static inline void __raw_spin_lock(raw_spinlock_t *lock) |
1da177e4 | 26 | { |
8b059d23 AK |
27 | asm volatile( |
28 | "\n1:\t" | |
29 | LOCK_PREFIX " ; decl %0\n\t" | |
30 | "jns 2f\n" | |
31 | "3:\n" | |
32 | "rep;nop\n\t" | |
33 | "cmpl $0,%0\n\t" | |
34 | "jle 3b\n\t" | |
35 | "jmp 1b\n" | |
36 | "2:\t" : "=m" (lock->slock) : : "memory"); | |
1da177e4 LT |
37 | } |
38 | ||
87e1652c AK |
39 | /* |
40 | * Same as __raw_spin_lock, but reenable interrupts during spinning. | |
41 | */ | |
42 | #ifndef CONFIG_PROVE_LOCKING | |
43 | static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) | |
44 | { | |
45 | asm volatile( | |
46 | "\n1:\t" | |
47 | LOCK_PREFIX " ; decl %0\n\t" | |
48 | "jns 5f\n" | |
49 | "testl $0x200, %1\n\t" /* interrupts were disabled? */ | |
50 | "jz 4f\n\t" | |
51 | "sti\n" | |
52 | "3:\t" | |
53 | "rep;nop\n\t" | |
54 | "cmpl $0, %0\n\t" | |
55 | "jle 3b\n\t" | |
56 | "cli\n\t" | |
57 | "jmp 1b\n" | |
58 | "4:\t" | |
59 | "rep;nop\n\t" | |
60 | "cmpl $0, %0\n\t" | |
61 | "jg 1b\n\t" | |
62 | "jmp 4b\n" | |
63 | "5:\n\t" | |
64 | : "+m" (lock->slock) : "r" ((unsigned)flags) : "memory"); | |
65 | } | |
66 | #endif | |
1da177e4 | 67 | |
fb1c8f93 | 68 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) |
1da177e4 | 69 | { |
485832a5 | 70 | int oldval; |
fb1c8f93 | 71 | |
8b059d23 | 72 | asm volatile( |
485832a5 | 73 | "xchgl %0,%1" |
fb1c8f93 | 74 | :"=q" (oldval), "=m" (lock->slock) |
1da177e4 | 75 | :"0" (0) : "memory"); |
fb1c8f93 | 76 | |
1da177e4 LT |
77 | return oldval > 0; |
78 | } | |
79 | ||
fb1c8f93 | 80 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) |
1da177e4 | 81 | { |
8b059d23 | 82 | asm volatile("movl $1,%0" :"=m" (lock->slock) :: "memory"); |
1da177e4 LT |
83 | } |
84 | ||
8b059d23 AK |
85 | static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) |
86 | { | |
87 | while (__raw_spin_is_locked(lock)) | |
88 | cpu_relax(); | |
89 | } | |
1da177e4 LT |
90 | |
91 | /* | |
92 | * Read-write spinlocks, allowing multiple readers | |
93 | * but only one writer. | |
94 | * | |
95 | * NOTE! it is quite common to have readers in interrupts | |
96 | * but no interrupt writers. For those circumstances we | |
97 | * can "mix" irq-safe locks - any writer needs to get a | |
98 | * irq-safe write-lock, but readers can get non-irqsafe | |
99 | * read-locks. | |
fb1c8f93 | 100 | * |
1da177e4 LT |
101 | * On x86, we implement read-write locks as a 32-bit counter |
102 | * with the high bit (sign) being the "contended" bit. | |
1da177e4 | 103 | */ |
1da177e4 | 104 | |
8b059d23 AK |
105 | static inline int __raw_read_can_lock(raw_rwlock_t *lock) |
106 | { | |
107 | return (int)(lock)->lock > 0; | |
108 | } | |
109 | ||
110 | static inline int __raw_write_can_lock(raw_rwlock_t *lock) | |
111 | { | |
112 | return (lock)->lock == RW_LOCK_BIAS; | |
113 | } | |
fb1c8f93 IM |
114 | |
115 | static inline void __raw_read_lock(raw_rwlock_t *rw) | |
1da177e4 | 116 | { |
8b059d23 AK |
117 | asm volatile(LOCK_PREFIX "subl $1,(%0)\n\t" |
118 | "jns 1f\n" | |
119 | "call __read_lock_failed\n" | |
120 | "1:\n" | |
121 | ::"D" (rw), "i" (RW_LOCK_BIAS) : "memory"); | |
1da177e4 LT |
122 | } |
123 | ||
fb1c8f93 | 124 | static inline void __raw_write_lock(raw_rwlock_t *rw) |
1da177e4 | 125 | { |
8b059d23 AK |
126 | asm volatile(LOCK_PREFIX "subl %1,(%0)\n\t" |
127 | "jz 1f\n" | |
128 | "\tcall __write_lock_failed\n\t" | |
129 | "1:\n" | |
130 | ::"D" (rw), "i" (RW_LOCK_BIAS) : "memory"); | |
1da177e4 LT |
131 | } |
132 | ||
fb1c8f93 | 133 | static inline int __raw_read_trylock(raw_rwlock_t *lock) |
1da177e4 LT |
134 | { |
135 | atomic_t *count = (atomic_t *)lock; | |
136 | atomic_dec(count); | |
137 | if (atomic_read(count) >= 0) | |
138 | return 1; | |
139 | atomic_inc(count); | |
140 | return 0; | |
141 | } | |
142 | ||
fb1c8f93 | 143 | static inline int __raw_write_trylock(raw_rwlock_t *lock) |
1da177e4 LT |
144 | { |
145 | atomic_t *count = (atomic_t *)lock; | |
146 | if (atomic_sub_and_test(RW_LOCK_BIAS, count)) | |
147 | return 1; | |
148 | atomic_add(RW_LOCK_BIAS, count); | |
149 | return 0; | |
150 | } | |
151 | ||
fb1c8f93 IM |
152 | static inline void __raw_read_unlock(raw_rwlock_t *rw) |
153 | { | |
841be8dd | 154 | asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory"); |
fb1c8f93 IM |
155 | } |
156 | ||
157 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | |
158 | { | |
841be8dd | 159 | asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0" |
fb1c8f93 IM |
160 | : "=m" (rw->lock) : : "memory"); |
161 | } | |
162 | ||
ef6edc97 MS |
163 | #define _raw_spin_relax(lock) cpu_relax() |
164 | #define _raw_read_relax(lock) cpu_relax() | |
165 | #define _raw_write_relax(lock) cpu_relax() | |
166 | ||
1da177e4 | 167 | #endif /* __ASM_SPINLOCK_H */ |