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1da177e4 LT |
1 | #ifndef _X8664_TLBFLUSH_H |
2 | #define _X8664_TLBFLUSH_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | #include <linux/mm.h> | |
6 | #include <asm/processor.h> | |
7 | ||
8 | #define __flush_tlb() \ | |
9 | do { \ | |
10 | unsigned long tmpreg; \ | |
11 | \ | |
12 | __asm__ __volatile__( \ | |
13 | "movq %%cr3, %0; # flush TLB \n" \ | |
14 | "movq %0, %%cr3; \n" \ | |
15 | : "=r" (tmpreg) \ | |
16 | :: "memory"); \ | |
17 | } while (0) | |
18 | ||
19 | /* | |
20 | * Global pages have to be flushed a bit differently. Not a real | |
21 | * performance problem because this does not happen often. | |
22 | */ | |
23 | #define __flush_tlb_global() \ | |
24 | do { \ | |
ffaa8bd6 | 25 | unsigned long tmpreg, cr4, cr4_orig; \ |
1da177e4 LT |
26 | \ |
27 | __asm__ __volatile__( \ | |
ffaa8bd6 AA |
28 | "movq %%cr4, %2; # turn off PGE \n" \ |
29 | "movq %2, %1; \n" \ | |
30 | "andq %3, %1; \n" \ | |
31 | "movq %1, %%cr4; \n" \ | |
1da177e4 LT |
32 | "movq %%cr3, %0; # flush TLB \n" \ |
33 | "movq %0, %%cr3; \n" \ | |
34 | "movq %2, %%cr4; # turn PGE back on \n" \ | |
ffaa8bd6 AA |
35 | : "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \ |
36 | : "i" (~X86_CR4_PGE) \ | |
1da177e4 LT |
37 | : "memory"); \ |
38 | } while (0) | |
39 | ||
40 | extern unsigned long pgkern_mask; | |
41 | ||
42 | #define __flush_tlb_all() __flush_tlb_global() | |
43 | ||
44 | #define __flush_tlb_one(addr) \ | |
45 | __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) | |
46 | ||
47 | ||
48 | /* | |
49 | * TLB flushing: | |
50 | * | |
51 | * - flush_tlb() flushes the current mm struct TLBs | |
52 | * - flush_tlb_all() flushes all processes TLBs | |
53 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
54 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
55 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
56 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | |
57 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | |
58 | * | |
d970a521 AK |
59 | * x86-64 can only flush individual pages or full VMs. For a range flush |
60 | * we always do the full VM. Might be worth trying if for a small | |
61 | * range a few INVLPGs in a row are a win. | |
1da177e4 LT |
62 | */ |
63 | ||
64 | #ifndef CONFIG_SMP | |
65 | ||
66 | #define flush_tlb() __flush_tlb() | |
67 | #define flush_tlb_all() __flush_tlb_all() | |
68 | #define local_flush_tlb() __flush_tlb() | |
69 | ||
70 | static inline void flush_tlb_mm(struct mm_struct *mm) | |
71 | { | |
72 | if (mm == current->active_mm) | |
73 | __flush_tlb(); | |
74 | } | |
75 | ||
76 | static inline void flush_tlb_page(struct vm_area_struct *vma, | |
77 | unsigned long addr) | |
78 | { | |
79 | if (vma->vm_mm == current->active_mm) | |
80 | __flush_tlb_one(addr); | |
81 | } | |
82 | ||
83 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
84 | unsigned long start, unsigned long end) | |
85 | { | |
86 | if (vma->vm_mm == current->active_mm) | |
87 | __flush_tlb(); | |
88 | } | |
89 | ||
90 | #else | |
91 | ||
92 | #include <asm/smp.h> | |
93 | ||
94 | #define local_flush_tlb() \ | |
95 | __flush_tlb() | |
96 | ||
97 | extern void flush_tlb_all(void); | |
98 | extern void flush_tlb_current_task(void); | |
99 | extern void flush_tlb_mm(struct mm_struct *); | |
100 | extern void flush_tlb_page(struct vm_area_struct *, unsigned long); | |
101 | ||
102 | #define flush_tlb() flush_tlb_current_task() | |
103 | ||
104 | static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) | |
105 | { | |
106 | flush_tlb_mm(vma->vm_mm); | |
107 | } | |
108 | ||
109 | #define TLBSTATE_OK 1 | |
110 | #define TLBSTATE_LAZY 2 | |
111 | ||
112 | #endif | |
113 | ||
114 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() | |
115 | ||
116 | static inline void flush_tlb_pgtables(struct mm_struct *mm, | |
117 | unsigned long start, unsigned long end) | |
118 | { | |
d970a521 AK |
119 | /* x86_64 does not keep any page table caches in a software TLB. |
120 | The CPUs do in their hardware TLBs, but they are handled | |
121 | by the normal TLB flushing algorithms. */ | |
1da177e4 LT |
122 | } |
123 | ||
124 | #endif /* _X8664_TLBFLUSH_H */ |