[mirror_ubuntu-zesty-kernel.git] / include / asm-x86_64 / tlbflush.h

#ifndef _X8664_TLBFLUSH_H
#define _X8664_TLBFLUSH_H

#include <linux/mm.h>
#include <asm/processor.h>

#define __flush_tlb()							\
	do {								\
		unsigned long tmpreg;					\
									\
		__asm__ __volatile__(					\
			"movq %%cr3, %0;  # flush TLB \n"		\
			"movq %0, %%cr3;              \n"		\
			: "=r" (tmpreg)					\
			:: "memory");					\
	} while (0)

/*
 * Global pages have to be flushed a bit differently. Not a real
 * performance problem because this does not happen often.
 */
#define __flush_tlb_global()						\
	do {								\
		unsigned long tmpreg, cr4, cr4_orig;			\
									\
		__asm__ __volatile__(					\
			"movq %%cr4, %2;  # turn off PGE     \n"	\
			"movq %2, %1;                        \n"	\
			"andq %3, %1;                        \n"	\
			"movq %1, %%cr4;                     \n"	\
			"movq %%cr3, %0;  # flush TLB        \n"	\
			"movq %0, %%cr3;                     \n"	\
			"movq %2, %%cr4;  # turn PGE back on \n"	\
			: "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig)	\
			: "i" (~X86_CR4_PGE)				\
			: "memory");					\
	} while (0)

extern unsigned long pgkern_mask;

#define __flush_tlb_all() __flush_tlb_global()

#define __flush_tlb_one(addr) \
	__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))


/*
 * TLB flushing:
 *
 *  - flush_tlb() flushes the current mm struct TLBs
 *  - flush_tlb_all() flushes all processes TLBs
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
 *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
 *
 * x86-64 can only flush individual pages or full VMs. For a range flush
 * we always do the full VM. Might be worth trying if for a small
 * range a few INVLPGs in a row are a win.
 */

#ifndef CONFIG_SMP

#define flush_tlb() __flush_tlb()
#define flush_tlb_all() __flush_tlb_all()
#define local_flush_tlb() __flush_tlb()

static inline void flush_tlb_mm(struct mm_struct *mm)
{
	if (mm == current->active_mm)
		__flush_tlb();
}

static inline void flush_tlb_page(struct vm_area_struct *vma,
	unsigned long addr)
{
	if (vma->vm_mm == current->active_mm)
		__flush_tlb_one(addr);
}

static inline void flush_tlb_range(struct vm_area_struct *vma,
	unsigned long start, unsigned long end)
{
	if (vma->vm_mm == current->active_mm)
		__flush_tlb();
}

#else

#include <asm/smp.h>

#define local_flush_tlb() \
	__flush_tlb()

extern void flush_tlb_all(void);
extern void flush_tlb_current_task(void);
extern void flush_tlb_mm(struct mm_struct *);
extern void flush_tlb_page(struct vm_area_struct *, unsigned long);

#define flush_tlb()	flush_tlb_current_task()

static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
{
	flush_tlb_mm(vma->vm_mm);
}

#define TLBSTATE_OK	1
#define TLBSTATE_LAZY	2

/* Roughly an IPI every 20MB with 4k pages for freeing page table
   ranges. Cost is about 42k of memory for each CPU. */
#define ARCH_FREE_PTE_NR 5350	

#endif

#define flush_tlb_kernel_range(start, end) flush_tlb_all()

static inline void flush_tlb_pgtables(struct mm_struct *mm,
				      unsigned long start, unsigned long end)
{
	/* x86_64 does not keep any page table caches in a software TLB.
	   The CPUs do in their hardware TLBs, but they are handled
	   by the normal TLB flushing algorithms. */
}

#endif /* _X8664_TLBFLUSH_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _X8664_TLBFLUSH_H
	2	#define _X8664_TLBFLUSH_H
	3
1da177e4 LT	4	#include <linux/mm.h>
	5	#include <asm/processor.h>
	6
	7	#define __flush_tlb() \
	8	do { \
	9	unsigned long tmpreg; \
	10	\
	11	__asm__ __volatile__( \
	12	"movq %%cr3, %0; # flush TLB \n" \
	13	"movq %0, %%cr3; \n" \
	14	: "=r" (tmpreg) \
	15	:: "memory"); \
	16	} while (0)
	17
	18	/*
	19	* Global pages have to be flushed a bit differently. Not a real
	20	* performance problem because this does not happen often.
	21	*/
	22	#define __flush_tlb_global() \
	23	do { \
ffaa8bd6	24	unsigned long tmpreg, cr4, cr4_orig; \
1da177e4 LT	25	\
1da177e4 LT	26	__asm__ __volatile__( \
ffaa8bd6 AA	27	"movq %%cr4, %2; # turn off PGE \n" \
	28	"movq %2, %1; \n" \
	29	"andq %3, %1; \n" \
	30	"movq %1, %%cr4; \n" \
1da177e4 LT	31	"movq %%cr3, %0; # flush TLB \n" \
	32	"movq %0, %%cr3; \n" \
	33	"movq %2, %%cr4; # turn PGE back on \n" \
ffaa8bd6 AA	34	: "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
ffaa8bd6 AA	35	: "i" (~X86_CR4_PGE) \
1da177e4 LT	36	: "memory"); \
	37	} while (0)
	38
	39	extern unsigned long pgkern_mask;
	40
	41	#define __flush_tlb_all() __flush_tlb_global()
	42
	43	#define __flush_tlb_one(addr) \
	44	__asm__ __volatile__("invlpg %0": :"m" ((char ) addr))
	45
	46
	47	/*
	48	* TLB flushing:
	49	*
	50	* - flush_tlb() flushes the current mm struct TLBs
	51	* - flush_tlb_all() flushes all processes TLBs
	52	* - flush_tlb_mm(mm) flushes the specified mm context TLB's
	53	* - flush_tlb_page(vma, vmaddr) flushes one page
	54	* - flush_tlb_range(vma, start, end) flushes a range of pages
	55	* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
	56	* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
	57	*
d970a521 AK	58	* x86-64 can only flush individual pages or full VMs. For a range flush
	59	* we always do the full VM. Might be worth trying if for a small
	60	* range a few INVLPGs in a row are a win.
1da177e4 LT	61	*/
	62
	63	#ifndef CONFIG_SMP
	64
	65	#define flush_tlb() __flush_tlb()
	66	#define flush_tlb_all() __flush_tlb_all()
	67	#define local_flush_tlb() __flush_tlb()
	68
	69	static inline void flush_tlb_mm(struct mm_struct *mm)
	70	{
	71	if (mm == current->active_mm)
	72	__flush_tlb();
	73	}
	74
	75	static inline void flush_tlb_page(struct vm_area_struct *vma,
	76	unsigned long addr)
	77	{
	78	if (vma->vm_mm == current->active_mm)
	79	__flush_tlb_one(addr);
	80	}
	81
	82	static inline void flush_tlb_range(struct vm_area_struct *vma,
	83	unsigned long start, unsigned long end)
	84	{
	85	if (vma->vm_mm == current->active_mm)
	86	__flush_tlb();
	87	}
	88
	89	#else
	90
	91	#include <asm/smp.h>
	92
	93	#define local_flush_tlb() \
	94	__flush_tlb()
	95
	96	extern void flush_tlb_all(void);
	97	extern void flush_tlb_current_task(void);
	98	extern void flush_tlb_mm(struct mm_struct *);
	99	extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
	100
	101	#define flush_tlb() flush_tlb_current_task()
	102
	103	static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
	104	{
	105	flush_tlb_mm(vma->vm_mm);
	106	}
	107
	108	#define TLBSTATE_OK 1
	109	#define TLBSTATE_LAZY 2
	110
2b4a0815 AK	111	/* Roughly an IPI every 20MB with 4k pages for freeing page table
	112	ranges. Cost is about 42k of memory for each CPU. */
	113	#define ARCH_FREE_PTE_NR 5350
	114
1da177e4 LT	115	#endif
	116
	117	#define flush_tlb_kernel_range(start, end) flush_tlb_all()
	118
	119	static inline void flush_tlb_pgtables(struct mm_struct *mm,
	120	unsigned long start, unsigned long end)
	121	{
d970a521 AK	122	/* x86_64 does not keep any page table caches in a software TLB.
	123	The CPUs do in their hardware TLBs, but they are handled
	124	by the normal TLB flushing algorithms. */
1da177e4 LT	125	}
	126
	127	#endif /* _X8664_TLBFLUSH_H */