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a3d9a352 FZ |
1 | #ifndef BLOCK_NVME_H |
2 | #define BLOCK_NVME_H | |
3 | ||
73064edf JD |
4 | #include "hw/registerfields.h" |
5 | ||
e989738f | 6 | typedef struct QEMU_PACKED NvmeBar { |
a3d9a352 FZ |
7 | uint64_t cap; |
8 | uint32_t vs; | |
9 | uint32_t intms; | |
10 | uint32_t intmc; | |
11 | uint32_t cc; | |
9a31c615 | 12 | uint8_t rsvd24[4]; |
a3d9a352 | 13 | uint32_t csts; |
a316aa50 | 14 | uint32_t nssr; |
a3d9a352 FZ |
15 | uint32_t aqa; |
16 | uint64_t asq; | |
17 | uint64_t acq; | |
18 | uint32_t cmbloc; | |
19 | uint32_t cmbsz; | |
f4319477 PK |
20 | uint32_t bpinfo; |
21 | uint32_t bprsel; | |
22 | uint64_t bpmbl; | |
23 | uint64_t cmbmsc; | |
24 | uint32_t cmbsts; | |
25 | uint8_t rsvd92[3492]; | |
6cf94132 AJ |
26 | uint32_t pmrcap; |
27 | uint32_t pmrctl; | |
28 | uint32_t pmrsts; | |
29 | uint32_t pmrebs; | |
30 | uint32_t pmrswtp; | |
5d45edbe KJ |
31 | uint32_t pmrmscl; |
32 | uint32_t pmrmscu; | |
f4319477 | 33 | uint8_t css[484]; |
a3d9a352 FZ |
34 | } NvmeBar; |
35 | ||
a316aa50 KJ |
36 | enum NvmeBarRegs { |
37 | NVME_REG_CAP = offsetof(NvmeBar, cap), | |
38 | NVME_REG_VS = offsetof(NvmeBar, vs), | |
39 | NVME_REG_INTMS = offsetof(NvmeBar, intms), | |
40 | NVME_REG_INTMC = offsetof(NvmeBar, intmc), | |
41 | NVME_REG_CC = offsetof(NvmeBar, cc), | |
42 | NVME_REG_CSTS = offsetof(NvmeBar, csts), | |
43 | NVME_REG_NSSR = offsetof(NvmeBar, nssr), | |
44 | NVME_REG_AQA = offsetof(NvmeBar, aqa), | |
45 | NVME_REG_ASQ = offsetof(NvmeBar, asq), | |
46 | NVME_REG_ACQ = offsetof(NvmeBar, acq), | |
47 | NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc), | |
48 | NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz), | |
49 | NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo), | |
50 | NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel), | |
51 | NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl), | |
52 | NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc), | |
53 | NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts), | |
54 | NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap), | |
55 | NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl), | |
56 | NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts), | |
57 | NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs), | |
58 | NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp), | |
59 | NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl), | |
60 | NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu), | |
61 | }; | |
62 | ||
771dbc3a KJ |
63 | typedef struct QEMU_PACKED NvmeEndGrpLog { |
64 | uint8_t critical_warning; | |
65 | uint8_t rsvd[2]; | |
66 | uint8_t avail_spare; | |
67 | uint8_t avail_spare_thres; | |
68 | uint8_t percet_used; | |
69 | uint8_t rsvd1[26]; | |
70 | uint64_t end_estimate[2]; | |
71 | uint64_t data_units_read[2]; | |
72 | uint64_t data_units_written[2]; | |
73 | uint64_t media_units_written[2]; | |
74 | uint64_t host_read_commands[2]; | |
75 | uint64_t host_write_commands[2]; | |
76 | uint64_t media_integrity_errors[2]; | |
77 | uint64_t no_err_info_log_entries[2]; | |
78 | uint8_t rsvd2[352]; | |
79 | } NvmeEndGrpLog; | |
80 | ||
a3d9a352 FZ |
81 | enum NvmeCapShift { |
82 | CAP_MQES_SHIFT = 0, | |
83 | CAP_CQR_SHIFT = 16, | |
84 | CAP_AMS_SHIFT = 17, | |
85 | CAP_TO_SHIFT = 24, | |
86 | CAP_DSTRD_SHIFT = 32, | |
407d22eb | 87 | CAP_NSSRS_SHIFT = 36, |
a3d9a352 FZ |
88 | CAP_CSS_SHIFT = 37, |
89 | CAP_MPSMIN_SHIFT = 48, | |
90 | CAP_MPSMAX_SHIFT = 52, | |
8e9e8b48 KJ |
91 | CAP_PMRS_SHIFT = 56, |
92 | CAP_CMBS_SHIFT = 57, | |
a3d9a352 FZ |
93 | }; |
94 | ||
95 | enum NvmeCapMask { | |
96 | CAP_MQES_MASK = 0xffff, | |
97 | CAP_CQR_MASK = 0x1, | |
98 | CAP_AMS_MASK = 0x3, | |
99 | CAP_TO_MASK = 0xff, | |
100 | CAP_DSTRD_MASK = 0xf, | |
101 | CAP_NSSRS_MASK = 0x1, | |
102 | CAP_CSS_MASK = 0xff, | |
103 | CAP_MPSMIN_MASK = 0xf, | |
104 | CAP_MPSMAX_MASK = 0xf, | |
8e9e8b48 KJ |
105 | CAP_PMRS_MASK = 0x1, |
106 | CAP_CMBS_MASK = 0x1, | |
a3d9a352 FZ |
107 | }; |
108 | ||
109 | #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) | |
110 | #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) | |
111 | #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) | |
112 | #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) | |
113 | #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) | |
114 | #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) | |
115 | #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) | |
116 | #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) | |
117 | #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) | |
8e9e8b48 | 118 | #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) |
f4319477 | 119 | #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) |
a3d9a352 | 120 | |
43f76aac DK |
121 | #define NVME_CAP_SET_MQES(cap, val) \ |
122 | ((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT) | |
123 | #define NVME_CAP_SET_CQR(cap, val) \ | |
124 | ((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT) | |
125 | #define NVME_CAP_SET_AMS(cap, val) \ | |
126 | ((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT) | |
127 | #define NVME_CAP_SET_TO(cap, val) \ | |
128 | ((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT) | |
129 | #define NVME_CAP_SET_DSTRD(cap, val) \ | |
130 | ((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT) | |
131 | #define NVME_CAP_SET_NSSRS(cap, val) \ | |
132 | ((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT) | |
133 | #define NVME_CAP_SET_CSS(cap, val) \ | |
134 | ((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT) | |
135 | #define NVME_CAP_SET_MPSMIN(cap, val) \ | |
136 | ((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT) | |
137 | #define NVME_CAP_SET_MPSMAX(cap, val) \ | |
138 | ((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT) | |
139 | #define NVME_CAP_SET_PMRS(cap, val) \ | |
140 | ((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT) | |
141 | #define NVME_CAP_SET_CMBS(cap, val) \ | |
142 | ((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT) | |
a3d9a352 | 143 | |
492f9a8d | 144 | enum NvmeCapCss { |
8c5cea85 | 145 | NVME_CAP_CSS_NVM = 1 << 0, |
141354d5 | 146 | NVME_CAP_CSS_CSI_SUPP = 1 << 6, |
8c5cea85 | 147 | NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, |
492f9a8d KB |
148 | }; |
149 | ||
a3d9a352 FZ |
150 | enum NvmeCcShift { |
151 | CC_EN_SHIFT = 0, | |
152 | CC_CSS_SHIFT = 4, | |
153 | CC_MPS_SHIFT = 7, | |
154 | CC_AMS_SHIFT = 11, | |
155 | CC_SHN_SHIFT = 14, | |
156 | CC_IOSQES_SHIFT = 16, | |
157 | CC_IOCQES_SHIFT = 20, | |
158 | }; | |
159 | ||
160 | enum NvmeCcMask { | |
161 | CC_EN_MASK = 0x1, | |
162 | CC_CSS_MASK = 0x7, | |
163 | CC_MPS_MASK = 0xf, | |
164 | CC_AMS_MASK = 0x7, | |
165 | CC_SHN_MASK = 0x3, | |
166 | CC_IOSQES_MASK = 0xf, | |
167 | CC_IOCQES_MASK = 0xf, | |
168 | }; | |
169 | ||
170 | #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) | |
171 | #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) | |
172 | #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) | |
173 | #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) | |
174 | #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) | |
175 | #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) | |
176 | #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) | |
177 | ||
1b48e461 KJ |
178 | enum NvmeCcCss { |
179 | NVME_CC_CSS_NVM = 0x0, | |
141354d5 | 180 | NVME_CC_CSS_CSI = 0x6, |
1b48e461 KJ |
181 | NVME_CC_CSS_ADMIN_ONLY = 0x7, |
182 | }; | |
183 | ||
141354d5 NC |
184 | #define NVME_SET_CC_EN(cc, val) \ |
185 | (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) | |
186 | #define NVME_SET_CC_CSS(cc, val) \ | |
187 | (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) | |
188 | #define NVME_SET_CC_MPS(cc, val) \ | |
189 | (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) | |
190 | #define NVME_SET_CC_AMS(cc, val) \ | |
191 | (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) | |
192 | #define NVME_SET_CC_SHN(cc, val) \ | |
193 | (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) | |
194 | #define NVME_SET_CC_IOSQES(cc, val) \ | |
195 | (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) | |
196 | #define NVME_SET_CC_IOCQES(cc, val) \ | |
197 | (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) | |
198 | ||
a3d9a352 FZ |
199 | enum NvmeCstsShift { |
200 | CSTS_RDY_SHIFT = 0, | |
201 | CSTS_CFS_SHIFT = 1, | |
202 | CSTS_SHST_SHIFT = 2, | |
203 | CSTS_NSSRO_SHIFT = 4, | |
204 | }; | |
205 | ||
206 | enum NvmeCstsMask { | |
207 | CSTS_RDY_MASK = 0x1, | |
208 | CSTS_CFS_MASK = 0x1, | |
209 | CSTS_SHST_MASK = 0x3, | |
210 | CSTS_NSSRO_MASK = 0x1, | |
211 | }; | |
212 | ||
213 | enum NvmeCsts { | |
214 | NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, | |
215 | NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, | |
216 | NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, | |
217 | NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, | |
218 | NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, | |
219 | NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, | |
220 | }; | |
221 | ||
222 | #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) | |
223 | #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) | |
224 | #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) | |
225 | #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) | |
226 | ||
227 | enum NvmeAqaShift { | |
228 | AQA_ASQS_SHIFT = 0, | |
229 | AQA_ACQS_SHIFT = 16, | |
230 | }; | |
231 | ||
232 | enum NvmeAqaMask { | |
233 | AQA_ASQS_MASK = 0xfff, | |
234 | AQA_ACQS_MASK = 0xfff, | |
235 | }; | |
236 | ||
237 | #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) | |
238 | #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) | |
239 | ||
240 | enum NvmeCmblocShift { | |
f4319477 PK |
241 | CMBLOC_BIR_SHIFT = 0, |
242 | CMBLOC_CQMMS_SHIFT = 3, | |
243 | CMBLOC_CQPDS_SHIFT = 4, | |
244 | CMBLOC_CDPMLS_SHIFT = 5, | |
245 | CMBLOC_CDPCILS_SHIFT = 6, | |
246 | CMBLOC_CDMMMS_SHIFT = 7, | |
247 | CMBLOC_CQDA_SHIFT = 8, | |
248 | CMBLOC_OFST_SHIFT = 12, | |
a3d9a352 FZ |
249 | }; |
250 | ||
251 | enum NvmeCmblocMask { | |
f4319477 PK |
252 | CMBLOC_BIR_MASK = 0x7, |
253 | CMBLOC_CQMMS_MASK = 0x1, | |
254 | CMBLOC_CQPDS_MASK = 0x1, | |
255 | CMBLOC_CDPMLS_MASK = 0x1, | |
256 | CMBLOC_CDPCILS_MASK = 0x1, | |
257 | CMBLOC_CDMMMS_MASK = 0x1, | |
258 | CMBLOC_CQDA_MASK = 0x1, | |
259 | CMBLOC_OFST_MASK = 0xfffff, | |
a3d9a352 FZ |
260 | }; |
261 | ||
f4319477 PK |
262 | #define NVME_CMBLOC_BIR(cmbloc) \ |
263 | ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) | |
264 | #define NVME_CMBLOC_CQMMS(cmbloc) \ | |
265 | ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) | |
266 | #define NVME_CMBLOC_CQPDS(cmbloc) \ | |
267 | ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) | |
268 | #define NVME_CMBLOC_CDPMLS(cmbloc) \ | |
269 | ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) | |
270 | #define NVME_CMBLOC_CDPCILS(cmbloc) \ | |
271 | ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) | |
272 | #define NVME_CMBLOC_CDMMMS(cmbloc) \ | |
273 | ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) | |
274 | #define NVME_CMBLOC_CQDA(cmbloc) \ | |
275 | ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) | |
276 | #define NVME_CMBLOC_OFST(cmbloc) \ | |
277 | ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) | |
a3d9a352 | 278 | |
f4319477 | 279 | #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ |
a3d9a352 | 280 | (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) |
f4319477 PK |
281 | #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ |
282 | (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) | |
283 | #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ | |
284 | (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) | |
285 | #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ | |
286 | (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) | |
287 | #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ | |
288 | (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) | |
289 | #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ | |
290 | (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) | |
291 | #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ | |
292 | (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) | |
a3d9a352 FZ |
293 | #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ |
294 | (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) | |
295 | ||
f4319477 PK |
296 | #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ |
297 | (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) | |
298 | ||
a3d9a352 FZ |
299 | enum NvmeCmbszShift { |
300 | CMBSZ_SQS_SHIFT = 0, | |
301 | CMBSZ_CQS_SHIFT = 1, | |
302 | CMBSZ_LISTS_SHIFT = 2, | |
303 | CMBSZ_RDS_SHIFT = 3, | |
304 | CMBSZ_WDS_SHIFT = 4, | |
305 | CMBSZ_SZU_SHIFT = 8, | |
306 | CMBSZ_SZ_SHIFT = 12, | |
307 | }; | |
308 | ||
309 | enum NvmeCmbszMask { | |
310 | CMBSZ_SQS_MASK = 0x1, | |
311 | CMBSZ_CQS_MASK = 0x1, | |
312 | CMBSZ_LISTS_MASK = 0x1, | |
313 | CMBSZ_RDS_MASK = 0x1, | |
314 | CMBSZ_WDS_MASK = 0x1, | |
315 | CMBSZ_SZU_MASK = 0xf, | |
316 | CMBSZ_SZ_MASK = 0xfffff, | |
317 | }; | |
318 | ||
319 | #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) | |
320 | #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) | |
321 | #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) | |
322 | #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) | |
323 | #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) | |
324 | #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) | |
325 | #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) | |
326 | ||
327 | #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ | |
328 | (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) | |
329 | #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ | |
330 | (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) | |
331 | #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ | |
332 | (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) | |
333 | #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ | |
334 | (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) | |
335 | #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ | |
336 | (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) | |
337 | #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ | |
338 | (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) | |
339 | #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ | |
340 | (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) | |
341 | ||
342 | #define NVME_CMBSZ_GETSIZE(cmbsz) \ | |
343 | (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) | |
344 | ||
f4319477 PK |
345 | enum NvmeCmbmscShift { |
346 | CMBMSC_CRE_SHIFT = 0, | |
347 | CMBMSC_CMSE_SHIFT = 1, | |
348 | CMBMSC_CBA_SHIFT = 12, | |
349 | }; | |
350 | ||
351 | enum NvmeCmbmscMask { | |
352 | CMBMSC_CRE_MASK = 0x1, | |
353 | CMBMSC_CMSE_MASK = 0x1, | |
354 | CMBMSC_CBA_MASK = ((1ULL << 52) - 1), | |
355 | }; | |
356 | ||
357 | #define NVME_CMBMSC_CRE(cmbmsc) \ | |
358 | ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) | |
359 | #define NVME_CMBMSC_CMSE(cmbmsc) \ | |
360 | ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) | |
361 | #define NVME_CMBMSC_CBA(cmbmsc) \ | |
362 | ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) | |
363 | ||
364 | ||
365 | #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ | |
366 | (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) | |
367 | #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ | |
368 | (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) | |
369 | #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ | |
370 | (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) | |
371 | ||
372 | enum NvmeCmbstsShift { | |
373 | CMBSTS_CBAI_SHIFT = 0, | |
374 | }; | |
375 | enum NvmeCmbstsMask { | |
376 | CMBSTS_CBAI_MASK = 0x1, | |
377 | }; | |
378 | ||
379 | #define NVME_CMBSTS_CBAI(cmbsts) \ | |
380 | ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) | |
381 | ||
382 | #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ | |
383 | (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) | |
384 | ||
6cf94132 AJ |
385 | enum NvmePmrcapShift { |
386 | PMRCAP_RDS_SHIFT = 3, | |
387 | PMRCAP_WDS_SHIFT = 4, | |
388 | PMRCAP_BIR_SHIFT = 5, | |
389 | PMRCAP_PMRTU_SHIFT = 8, | |
390 | PMRCAP_PMRWBM_SHIFT = 10, | |
391 | PMRCAP_PMRTO_SHIFT = 16, | |
392 | PMRCAP_CMSS_SHIFT = 24, | |
393 | }; | |
394 | ||
395 | enum NvmePmrcapMask { | |
396 | PMRCAP_RDS_MASK = 0x1, | |
397 | PMRCAP_WDS_MASK = 0x1, | |
398 | PMRCAP_BIR_MASK = 0x7, | |
399 | PMRCAP_PMRTU_MASK = 0x3, | |
400 | PMRCAP_PMRWBM_MASK = 0xf, | |
401 | PMRCAP_PMRTO_MASK = 0xff, | |
402 | PMRCAP_CMSS_MASK = 0x1, | |
403 | }; | |
404 | ||
405 | #define NVME_PMRCAP_RDS(pmrcap) \ | |
406 | ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) | |
407 | #define NVME_PMRCAP_WDS(pmrcap) \ | |
408 | ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) | |
409 | #define NVME_PMRCAP_BIR(pmrcap) \ | |
410 | ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) | |
411 | #define NVME_PMRCAP_PMRTU(pmrcap) \ | |
412 | ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) | |
413 | #define NVME_PMRCAP_PMRWBM(pmrcap) \ | |
414 | ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) | |
415 | #define NVME_PMRCAP_PMRTO(pmrcap) \ | |
416 | ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) | |
417 | #define NVME_PMRCAP_CMSS(pmrcap) \ | |
418 | ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) | |
419 | ||
420 | #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ | |
421 | (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) | |
422 | #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ | |
423 | (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) | |
424 | #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ | |
425 | (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) | |
426 | #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ | |
427 | (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) | |
428 | #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ | |
429 | (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) | |
430 | #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ | |
431 | (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) | |
432 | #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ | |
433 | (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) | |
434 | ||
435 | enum NvmePmrctlShift { | |
436 | PMRCTL_EN_SHIFT = 0, | |
437 | }; | |
438 | ||
439 | enum NvmePmrctlMask { | |
440 | PMRCTL_EN_MASK = 0x1, | |
441 | }; | |
442 | ||
443 | #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) | |
444 | ||
445 | #define NVME_PMRCTL_SET_EN(pmrctl, val) \ | |
446 | (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) | |
447 | ||
448 | enum NvmePmrstsShift { | |
449 | PMRSTS_ERR_SHIFT = 0, | |
450 | PMRSTS_NRDY_SHIFT = 8, | |
451 | PMRSTS_HSTS_SHIFT = 9, | |
452 | PMRSTS_CBAI_SHIFT = 12, | |
453 | }; | |
454 | ||
455 | enum NvmePmrstsMask { | |
456 | PMRSTS_ERR_MASK = 0xff, | |
457 | PMRSTS_NRDY_MASK = 0x1, | |
458 | PMRSTS_HSTS_MASK = 0x7, | |
459 | PMRSTS_CBAI_MASK = 0x1, | |
460 | }; | |
461 | ||
462 | #define NVME_PMRSTS_ERR(pmrsts) \ | |
463 | ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) | |
464 | #define NVME_PMRSTS_NRDY(pmrsts) \ | |
465 | ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) | |
466 | #define NVME_PMRSTS_HSTS(pmrsts) \ | |
467 | ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) | |
468 | #define NVME_PMRSTS_CBAI(pmrsts) \ | |
469 | ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) | |
470 | ||
471 | #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ | |
472 | (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) | |
473 | #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ | |
474 | (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) | |
475 | #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ | |
476 | (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) | |
477 | #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ | |
478 | (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) | |
479 | ||
480 | enum NvmePmrebsShift { | |
481 | PMREBS_PMRSZU_SHIFT = 0, | |
482 | PMREBS_RBB_SHIFT = 4, | |
483 | PMREBS_PMRWBZ_SHIFT = 8, | |
484 | }; | |
485 | ||
486 | enum NvmePmrebsMask { | |
487 | PMREBS_PMRSZU_MASK = 0xf, | |
488 | PMREBS_RBB_MASK = 0x1, | |
489 | PMREBS_PMRWBZ_MASK = 0xffffff, | |
490 | }; | |
491 | ||
492 | #define NVME_PMREBS_PMRSZU(pmrebs) \ | |
493 | ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) | |
494 | #define NVME_PMREBS_RBB(pmrebs) \ | |
495 | ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) | |
496 | #define NVME_PMREBS_PMRWBZ(pmrebs) \ | |
497 | ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) | |
498 | ||
499 | #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ | |
500 | (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) | |
501 | #define NVME_PMREBS_SET_RBB(pmrebs, val) \ | |
502 | (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) | |
503 | #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ | |
504 | (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) | |
505 | ||
506 | enum NvmePmrswtpShift { | |
507 | PMRSWTP_PMRSWTU_SHIFT = 0, | |
508 | PMRSWTP_PMRSWTV_SHIFT = 8, | |
509 | }; | |
510 | ||
511 | enum NvmePmrswtpMask { | |
512 | PMRSWTP_PMRSWTU_MASK = 0xf, | |
513 | PMRSWTP_PMRSWTV_MASK = 0xffffff, | |
514 | }; | |
515 | ||
516 | #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ | |
517 | ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) | |
518 | #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ | |
519 | ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) | |
520 | ||
521 | #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ | |
522 | (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) | |
523 | #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ | |
524 | (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) | |
525 | ||
5d45edbe KJ |
526 | enum NvmePmrmsclShift { |
527 | PMRMSCL_CMSE_SHIFT = 1, | |
528 | PMRMSCL_CBA_SHIFT = 12, | |
6cf94132 AJ |
529 | }; |
530 | ||
5d45edbe KJ |
531 | enum NvmePmrmsclMask { |
532 | PMRMSCL_CMSE_MASK = 0x1, | |
533 | PMRMSCL_CBA_MASK = 0xfffff, | |
6cf94132 AJ |
534 | }; |
535 | ||
5d45edbe KJ |
536 | #define NVME_PMRMSCL_CMSE(pmrmscl) \ |
537 | ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) | |
538 | #define NVME_PMRMSCL_CBA(pmrmscl) \ | |
539 | ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) | |
6cf94132 | 540 | |
5d45edbe KJ |
541 | #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ |
542 | (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) | |
543 | #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ | |
544 | (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) | |
6cf94132 | 545 | |
c26f2173 KJ |
546 | enum NvmeSglDescriptorType { |
547 | NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, | |
548 | NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, | |
549 | NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, | |
550 | NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, | |
551 | NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, | |
552 | ||
553 | NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, | |
554 | }; | |
555 | ||
556 | enum NvmeSglDescriptorSubtype { | |
557 | NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, | |
558 | }; | |
559 | ||
560 | typedef struct QEMU_PACKED NvmeSglDescriptor { | |
561 | uint64_t addr; | |
562 | uint32_t len; | |
563 | uint8_t rsvd[3]; | |
564 | uint8_t type; | |
565 | } NvmeSglDescriptor; | |
566 | ||
567 | #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) | |
568 | #define NVME_SGL_SUBTYPE(type) (type & 0xf) | |
569 | ||
570 | typedef union NvmeCmdDptr { | |
571 | struct { | |
572 | uint64_t prp1; | |
573 | uint64_t prp2; | |
574 | }; | |
575 | ||
576 | NvmeSglDescriptor sgl; | |
577 | } NvmeCmdDptr; | |
578 | ||
579 | enum NvmePsdt { | |
cba0a8a3 KJ |
580 | NVME_PSDT_PRP = 0x0, |
581 | NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, | |
582 | NVME_PSDT_SGL_MPTR_SGL = 0x2, | |
c26f2173 KJ |
583 | }; |
584 | ||
e989738f | 585 | typedef struct QEMU_PACKED NvmeCmd { |
a3d9a352 | 586 | uint8_t opcode; |
c26f2173 | 587 | uint8_t flags; |
a3d9a352 FZ |
588 | uint16_t cid; |
589 | uint32_t nsid; | |
590 | uint64_t res1; | |
591 | uint64_t mptr; | |
c26f2173 | 592 | NvmeCmdDptr dptr; |
a3d9a352 FZ |
593 | uint32_t cdw10; |
594 | uint32_t cdw11; | |
595 | uint32_t cdw12; | |
596 | uint32_t cdw13; | |
597 | uint32_t cdw14; | |
598 | uint32_t cdw15; | |
599 | } NvmeCmd; | |
600 | ||
c26f2173 KJ |
601 | #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) |
602 | #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) | |
603 | ||
a3d9a352 FZ |
604 | enum NvmeAdminCommands { |
605 | NVME_ADM_CMD_DELETE_SQ = 0x00, | |
606 | NVME_ADM_CMD_CREATE_SQ = 0x01, | |
607 | NVME_ADM_CMD_GET_LOG_PAGE = 0x02, | |
608 | NVME_ADM_CMD_DELETE_CQ = 0x04, | |
609 | NVME_ADM_CMD_CREATE_CQ = 0x05, | |
610 | NVME_ADM_CMD_IDENTIFY = 0x06, | |
611 | NVME_ADM_CMD_ABORT = 0x08, | |
612 | NVME_ADM_CMD_SET_FEATURES = 0x09, | |
613 | NVME_ADM_CMD_GET_FEATURES = 0x0a, | |
614 | NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, | |
615 | NVME_ADM_CMD_ACTIVATE_FW = 0x10, | |
616 | NVME_ADM_CMD_DOWNLOAD_FW = 0x11, | |
645ce1a7 | 617 | NVME_ADM_CMD_NS_ATTACHMENT = 0x15, |
e181d3da | 618 | NVME_ADM_CMD_DIRECTIVE_SEND = 0x19, |
11871f53 | 619 | NVME_ADM_CMD_VIRT_MNGMT = 0x1c, |
e181d3da | 620 | NVME_ADM_CMD_DIRECTIVE_RECV = 0x1a, |
3f7fe8de | 621 | NVME_ADM_CMD_DBBUF_CONFIG = 0x7c, |
a3d9a352 FZ |
622 | NVME_ADM_CMD_FORMAT_NVM = 0x80, |
623 | NVME_ADM_CMD_SECURITY_SEND = 0x81, | |
624 | NVME_ADM_CMD_SECURITY_RECV = 0x82, | |
625 | }; | |
626 | ||
627 | enum NvmeIoCommands { | |
628 | NVME_CMD_FLUSH = 0x00, | |
629 | NVME_CMD_WRITE = 0x01, | |
630 | NVME_CMD_READ = 0x02, | |
631 | NVME_CMD_WRITE_UNCOR = 0x04, | |
632 | NVME_CMD_COMPARE = 0x05, | |
69265150 | 633 | NVME_CMD_WRITE_ZEROES = 0x08, |
a3d9a352 | 634 | NVME_CMD_DSM = 0x09, |
3e1da158 | 635 | NVME_CMD_VERIFY = 0x0c, |
73064edf | 636 | NVME_CMD_IO_MGMT_RECV = 0x12, |
3862efff | 637 | NVME_CMD_COPY = 0x19, |
73064edf | 638 | NVME_CMD_IO_MGMT_SEND = 0x1d, |
e9ba46ee DF |
639 | NVME_CMD_ZONE_MGMT_SEND = 0x79, |
640 | NVME_CMD_ZONE_MGMT_RECV = 0x7a, | |
641 | NVME_CMD_ZONE_APPEND = 0x7d, | |
a3d9a352 FZ |
642 | }; |
643 | ||
e989738f | 644 | typedef struct QEMU_PACKED NvmeDeleteQ { |
a3d9a352 FZ |
645 | uint8_t opcode; |
646 | uint8_t flags; | |
647 | uint16_t cid; | |
648 | uint32_t rsvd1[9]; | |
649 | uint16_t qid; | |
650 | uint16_t rsvd10; | |
651 | uint32_t rsvd11[5]; | |
652 | } NvmeDeleteQ; | |
653 | ||
e989738f | 654 | typedef struct QEMU_PACKED NvmeCreateCq { |
a3d9a352 FZ |
655 | uint8_t opcode; |
656 | uint8_t flags; | |
657 | uint16_t cid; | |
658 | uint32_t rsvd1[5]; | |
659 | uint64_t prp1; | |
660 | uint64_t rsvd8; | |
661 | uint16_t cqid; | |
662 | uint16_t qsize; | |
663 | uint16_t cq_flags; | |
664 | uint16_t irq_vector; | |
665 | uint32_t rsvd12[4]; | |
666 | } NvmeCreateCq; | |
667 | ||
668 | #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) | |
669 | #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) | |
670 | ||
54248d4d PMD |
671 | enum NvmeFlagsCq { |
672 | NVME_CQ_PC = 1, | |
673 | NVME_CQ_IEN = 2, | |
674 | }; | |
675 | ||
e989738f | 676 | typedef struct QEMU_PACKED NvmeCreateSq { |
a3d9a352 FZ |
677 | uint8_t opcode; |
678 | uint8_t flags; | |
679 | uint16_t cid; | |
680 | uint32_t rsvd1[5]; | |
681 | uint64_t prp1; | |
682 | uint64_t rsvd8; | |
683 | uint16_t sqid; | |
684 | uint16_t qsize; | |
685 | uint16_t sq_flags; | |
686 | uint16_t cqid; | |
687 | uint32_t rsvd12[4]; | |
688 | } NvmeCreateSq; | |
689 | ||
690 | #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) | |
691 | #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) | |
692 | ||
54248d4d PMD |
693 | enum NvmeFlagsSq { |
694 | NVME_SQ_PC = 1, | |
695 | ||
696 | NVME_SQ_PRIO_URGENT = 0, | |
697 | NVME_SQ_PRIO_HIGH = 1, | |
698 | NVME_SQ_PRIO_NORMAL = 2, | |
699 | NVME_SQ_PRIO_LOW = 3, | |
a3d9a352 FZ |
700 | }; |
701 | ||
e989738f | 702 | typedef struct QEMU_PACKED NvmeIdentify { |
a3d9a352 FZ |
703 | uint8_t opcode; |
704 | uint8_t flags; | |
705 | uint16_t cid; | |
706 | uint32_t nsid; | |
707 | uint64_t rsvd2[2]; | |
708 | uint64_t prp1; | |
709 | uint64_t prp2; | |
141354d5 NC |
710 | uint8_t cns; |
711 | uint8_t rsvd10; | |
712 | uint16_t ctrlid; | |
713 | uint16_t nvmsetid; | |
714 | uint8_t rsvd11; | |
715 | uint8_t csi; | |
716 | uint32_t rsvd12[4]; | |
a3d9a352 FZ |
717 | } NvmeIdentify; |
718 | ||
e989738f | 719 | typedef struct QEMU_PACKED NvmeRwCmd { |
a3d9a352 FZ |
720 | uint8_t opcode; |
721 | uint8_t flags; | |
722 | uint16_t cid; | |
723 | uint32_t nsid; | |
44219b60 NN |
724 | uint32_t cdw2; |
725 | uint32_t cdw3; | |
a3d9a352 | 726 | uint64_t mptr; |
c26f2173 | 727 | NvmeCmdDptr dptr; |
a3d9a352 FZ |
728 | uint64_t slba; |
729 | uint16_t nlb; | |
730 | uint16_t control; | |
73064edf JD |
731 | uint8_t dsmgmt; |
732 | uint8_t rsvd; | |
733 | uint16_t dspec; | |
a3d9a352 FZ |
734 | uint32_t reftag; |
735 | uint16_t apptag; | |
736 | uint16_t appmask; | |
737 | } NvmeRwCmd; | |
738 | ||
739 | enum { | |
740 | NVME_RW_LR = 1 << 15, | |
741 | NVME_RW_FUA = 1 << 14, | |
742 | NVME_RW_DSM_FREQ_UNSPEC = 0, | |
743 | NVME_RW_DSM_FREQ_TYPICAL = 1, | |
744 | NVME_RW_DSM_FREQ_RARE = 2, | |
745 | NVME_RW_DSM_FREQ_READS = 3, | |
746 | NVME_RW_DSM_FREQ_WRITES = 4, | |
747 | NVME_RW_DSM_FREQ_RW = 5, | |
748 | NVME_RW_DSM_FREQ_ONCE = 6, | |
749 | NVME_RW_DSM_FREQ_PREFETCH = 7, | |
750 | NVME_RW_DSM_FREQ_TEMP = 8, | |
751 | NVME_RW_DSM_LATENCY_NONE = 0 << 4, | |
752 | NVME_RW_DSM_LATENCY_IDLE = 1 << 4, | |
753 | NVME_RW_DSM_LATENCY_NORM = 2 << 4, | |
754 | NVME_RW_DSM_LATENCY_LOW = 3 << 4, | |
755 | NVME_RW_DSM_SEQ_REQ = 1 << 6, | |
756 | NVME_RW_DSM_COMPRESSED = 1 << 7, | |
146f720c | 757 | NVME_RW_PIREMAP = 1 << 9, |
a3d9a352 FZ |
758 | NVME_RW_PRINFO_PRACT = 1 << 13, |
759 | NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, | |
760 | NVME_RW_PRINFO_PRCHK_APP = 1 << 11, | |
761 | NVME_RW_PRINFO_PRCHK_REF = 1 << 10, | |
146f720c | 762 | NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, |
a3d9a352 FZ |
763 | }; |
764 | ||
146f720c KJ |
765 | #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) |
766 | ||
2a132309 KJ |
767 | enum { |
768 | NVME_PRINFO_PRACT = 1 << 3, | |
769 | NVME_PRINFO_PRCHK_GUARD = 1 << 2, | |
770 | NVME_PRINFO_PRCHK_APP = 1 << 1, | |
771 | NVME_PRINFO_PRCHK_REF = 1 << 0, | |
772 | NVME_PRINFO_PRCHK_MASK = 7 << 0, | |
773 | }; | |
774 | ||
e989738f | 775 | typedef struct QEMU_PACKED NvmeDsmCmd { |
a3d9a352 FZ |
776 | uint8_t opcode; |
777 | uint8_t flags; | |
778 | uint16_t cid; | |
779 | uint32_t nsid; | |
780 | uint64_t rsvd2[2]; | |
c26f2173 | 781 | NvmeCmdDptr dptr; |
a3d9a352 FZ |
782 | uint32_t nr; |
783 | uint32_t attributes; | |
784 | uint32_t rsvd12[4]; | |
785 | } NvmeDsmCmd; | |
786 | ||
787 | enum { | |
788 | NVME_DSMGMT_IDR = 1 << 0, | |
789 | NVME_DSMGMT_IDW = 1 << 1, | |
790 | NVME_DSMGMT_AD = 1 << 2, | |
791 | }; | |
792 | ||
e989738f | 793 | typedef struct QEMU_PACKED NvmeDsmRange { |
a3d9a352 FZ |
794 | uint32_t cattr; |
795 | uint32_t nlb; | |
796 | uint64_t slba; | |
797 | } NvmeDsmRange; | |
798 | ||
3862efff KJ |
799 | enum { |
800 | NVME_COPY_FORMAT_0 = 0x0, | |
44219b60 | 801 | NVME_COPY_FORMAT_1 = 0x1, |
3862efff KJ |
802 | }; |
803 | ||
804 | typedef struct QEMU_PACKED NvmeCopyCmd { | |
805 | uint8_t opcode; | |
806 | uint8_t flags; | |
807 | uint16_t cid; | |
808 | uint32_t nsid; | |
44219b60 NN |
809 | uint32_t cdw2; |
810 | uint32_t cdw3; | |
811 | uint32_t rsvd2[2]; | |
3862efff KJ |
812 | NvmeCmdDptr dptr; |
813 | uint64_t sdlba; | |
814 | uint8_t nr; | |
815 | uint8_t control[3]; | |
816 | uint16_t rsvd13; | |
817 | uint16_t dspec; | |
818 | uint32_t reftag; | |
819 | uint16_t apptag; | |
820 | uint16_t appmask; | |
821 | } NvmeCopyCmd; | |
822 | ||
44219b60 | 823 | typedef struct QEMU_PACKED NvmeCopySourceRangeFormat0 { |
3862efff KJ |
824 | uint8_t rsvd0[8]; |
825 | uint64_t slba; | |
826 | uint16_t nlb; | |
827 | uint8_t rsvd18[6]; | |
828 | uint32_t reftag; | |
829 | uint16_t apptag; | |
830 | uint16_t appmask; | |
44219b60 NN |
831 | } NvmeCopySourceRangeFormat0; |
832 | ||
833 | typedef struct QEMU_PACKED NvmeCopySourceRangeFormat1 { | |
834 | uint8_t rsvd0[8]; | |
835 | uint64_t slba; | |
836 | uint16_t nlb; | |
837 | uint8_t rsvd18[8]; | |
838 | uint8_t sr[10]; | |
839 | uint16_t apptag; | |
840 | uint16_t appmask; | |
841 | } NvmeCopySourceRangeFormat1; | |
3862efff | 842 | |
a3d9a352 FZ |
843 | enum NvmeAsyncEventRequest { |
844 | NVME_AER_TYPE_ERROR = 0, | |
845 | NVME_AER_TYPE_SMART = 1, | |
f432fdfa | 846 | NVME_AER_TYPE_NOTICE = 2, |
a3d9a352 FZ |
847 | NVME_AER_TYPE_IO_SPECIFIC = 6, |
848 | NVME_AER_TYPE_VENDOR_SPECIFIC = 7, | |
5d5a5330 KJ |
849 | NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, |
850 | NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, | |
a3d9a352 FZ |
851 | NVME_AER_INFO_ERR_DIAG_FAIL = 2, |
852 | NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, | |
853 | NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, | |
854 | NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, | |
855 | NVME_AER_INFO_SMART_RELIABILITY = 0, | |
856 | NVME_AER_INFO_SMART_TEMP_THRESH = 1, | |
857 | NVME_AER_INFO_SMART_SPARE_THRESH = 2, | |
f432fdfa | 858 | NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, |
a3d9a352 FZ |
859 | }; |
860 | ||
e989738f | 861 | typedef struct QEMU_PACKED NvmeAerResult { |
a3d9a352 FZ |
862 | uint8_t event_type; |
863 | uint8_t event_info; | |
864 | uint8_t log_page; | |
865 | uint8_t resv; | |
866 | } NvmeAerResult; | |
867 | ||
e9ba46ee DF |
868 | typedef struct QEMU_PACKED NvmeZonedResult { |
869 | uint64_t slba; | |
870 | } NvmeZonedResult; | |
871 | ||
e989738f | 872 | typedef struct QEMU_PACKED NvmeCqe { |
a3d9a352 | 873 | uint32_t result; |
e9ba46ee | 874 | uint32_t dw1; |
a3d9a352 FZ |
875 | uint16_t sq_head; |
876 | uint16_t sq_id; | |
877 | uint16_t cid; | |
878 | uint16_t status; | |
879 | } NvmeCqe; | |
880 | ||
881 | enum NvmeStatusCodes { | |
882 | NVME_SUCCESS = 0x0000, | |
883 | NVME_INVALID_OPCODE = 0x0001, | |
884 | NVME_INVALID_FIELD = 0x0002, | |
885 | NVME_CID_CONFLICT = 0x0003, | |
886 | NVME_DATA_TRAS_ERROR = 0x0004, | |
887 | NVME_POWER_LOSS_ABORT = 0x0005, | |
888 | NVME_INTERNAL_DEV_ERROR = 0x0006, | |
889 | NVME_CMD_ABORT_REQ = 0x0007, | |
890 | NVME_CMD_ABORT_SQ_DEL = 0x0008, | |
891 | NVME_CMD_ABORT_FAILED_FUSE = 0x0009, | |
892 | NVME_CMD_ABORT_MISSING_FUSE = 0x000a, | |
893 | NVME_INVALID_NSID = 0x000b, | |
894 | NVME_CMD_SEQ_ERROR = 0x000c, | |
c26f2173 KJ |
895 | NVME_INVALID_SGL_SEG_DESCR = 0x000d, |
896 | NVME_INVALID_NUM_SGL_DESCRS = 0x000e, | |
897 | NVME_DATA_SGL_LEN_INVALID = 0x000f, | |
898 | NVME_MD_SGL_LEN_INVALID = 0x0010, | |
899 | NVME_SGL_DESCR_TYPE_INVALID = 0x0011, | |
900 | NVME_INVALID_USE_OF_CMB = 0x0012, | |
28fee5b5 | 901 | NVME_INVALID_PRP_OFFSET = 0x0013, |
141354d5 | 902 | NVME_CMD_SET_CMB_REJECTED = 0x002b, |
e9ba46ee | 903 | NVME_INVALID_CMD_SET = 0x002c, |
73064edf JD |
904 | NVME_FDP_DISABLED = 0x0029, |
905 | NVME_INVALID_PHID_LIST = 0x002a, | |
a3d9a352 FZ |
906 | NVME_LBA_RANGE = 0x0080, |
907 | NVME_CAP_EXCEEDED = 0x0081, | |
908 | NVME_NS_NOT_READY = 0x0082, | |
909 | NVME_NS_RESV_CONFLICT = 0x0083, | |
dc04d25e | 910 | NVME_FORMAT_IN_PROGRESS = 0x0084, |
a3d9a352 FZ |
911 | NVME_INVALID_CQID = 0x0100, |
912 | NVME_INVALID_QID = 0x0101, | |
913 | NVME_MAX_QSIZE_EXCEEDED = 0x0102, | |
914 | NVME_ACL_EXCEEDED = 0x0103, | |
915 | NVME_RESERVED = 0x0104, | |
916 | NVME_AER_LIMIT_EXCEEDED = 0x0105, | |
917 | NVME_INVALID_FW_SLOT = 0x0106, | |
918 | NVME_INVALID_FW_IMAGE = 0x0107, | |
919 | NVME_INVALID_IRQ_VECTOR = 0x0108, | |
920 | NVME_INVALID_LOG_ID = 0x0109, | |
921 | NVME_INVALID_FORMAT = 0x010a, | |
922 | NVME_FW_REQ_RESET = 0x010b, | |
923 | NVME_INVALID_QUEUE_DEL = 0x010c, | |
924 | NVME_FID_NOT_SAVEABLE = 0x010d, | |
1302e48e | 925 | NVME_FEAT_NOT_CHANGEABLE = 0x010e, |
7c46310d | 926 | NVME_FEAT_NOT_NS_SPEC = 0x010f, |
a3d9a352 | 927 | NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, |
645ce1a7 | 928 | NVME_NS_ALREADY_ATTACHED = 0x0118, |
e5489356 | 929 | NVME_NS_PRIVATE = 0x0119, |
312c3531 GA |
930 | NVME_NS_NOT_ATTACHED = 0x011a, |
931 | NVME_NS_CTRL_LIST_INVALID = 0x011c, | |
11871f53 ŁG |
932 | NVME_INVALID_CTRL_ID = 0x011f, |
933 | NVME_INVALID_SEC_CTRL_STATE = 0x0120, | |
934 | NVME_INVALID_NUM_RESOURCES = 0x0121, | |
935 | NVME_INVALID_RESOURCE_ID = 0x0122, | |
a3d9a352 FZ |
936 | NVME_CONFLICTING_ATTRS = 0x0180, |
937 | NVME_INVALID_PROT_INFO = 0x0181, | |
938 | NVME_WRITE_TO_RO = 0x0182, | |
3862efff | 939 | NVME_CMD_SIZE_LIMIT = 0x0183, |
e321b4cd KJ |
940 | NVME_INVALID_ZONE_OP = 0x01b6, |
941 | NVME_NOZRWA = 0x01b7, | |
e9ba46ee DF |
942 | NVME_ZONE_BOUNDARY_ERROR = 0x01b8, |
943 | NVME_ZONE_FULL = 0x01b9, | |
944 | NVME_ZONE_READ_ONLY = 0x01ba, | |
945 | NVME_ZONE_OFFLINE = 0x01bb, | |
946 | NVME_ZONE_INVALID_WRITE = 0x01bc, | |
947 | NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, | |
948 | NVME_ZONE_TOO_MANY_OPEN = 0x01be, | |
949 | NVME_ZONE_INVAL_TRANSITION = 0x01bf, | |
a3d9a352 FZ |
950 | NVME_WRITE_FAULT = 0x0280, |
951 | NVME_UNRECOVERED_READ = 0x0281, | |
952 | NVME_E2E_GUARD_ERROR = 0x0282, | |
953 | NVME_E2E_APP_ERROR = 0x0283, | |
954 | NVME_E2E_REF_ERROR = 0x0284, | |
955 | NVME_CMP_FAILURE = 0x0285, | |
956 | NVME_ACCESS_DENIED = 0x0286, | |
54064e51 | 957 | NVME_DULB = 0x0287, |
44219b60 | 958 | NVME_E2E_STORAGE_TAG_ERROR = 0x0288, |
a3d9a352 FZ |
959 | NVME_MORE = 0x2000, |
960 | NVME_DNR = 0x4000, | |
961 | NVME_NO_COMPLETE = 0xffff, | |
962 | }; | |
963 | ||
e989738f | 964 | typedef struct QEMU_PACKED NvmeFwSlotInfoLog { |
a3d9a352 FZ |
965 | uint8_t afi; |
966 | uint8_t reserved1[7]; | |
967 | uint8_t frs1[8]; | |
968 | uint8_t frs2[8]; | |
969 | uint8_t frs3[8]; | |
970 | uint8_t frs4[8]; | |
971 | uint8_t frs5[8]; | |
972 | uint8_t frs6[8]; | |
973 | uint8_t frs7[8]; | |
974 | uint8_t reserved2[448]; | |
975 | } NvmeFwSlotInfoLog; | |
976 | ||
e989738f | 977 | typedef struct QEMU_PACKED NvmeErrorLog { |
a3d9a352 FZ |
978 | uint64_t error_count; |
979 | uint16_t sqid; | |
980 | uint16_t cid; | |
981 | uint16_t status_field; | |
982 | uint16_t param_error_location; | |
983 | uint64_t lba; | |
984 | uint32_t nsid; | |
985 | uint8_t vs; | |
986 | uint8_t resv[35]; | |
987 | } NvmeErrorLog; | |
988 | ||
e989738f | 989 | typedef struct QEMU_PACKED NvmeSmartLog { |
a3d9a352 | 990 | uint8_t critical_warning; |
94a7897c | 991 | uint16_t temperature; |
a3d9a352 FZ |
992 | uint8_t available_spare; |
993 | uint8_t available_spare_threshold; | |
994 | uint8_t percentage_used; | |
995 | uint8_t reserved1[26]; | |
996 | uint64_t data_units_read[2]; | |
997 | uint64_t data_units_written[2]; | |
998 | uint64_t host_read_commands[2]; | |
999 | uint64_t host_write_commands[2]; | |
1000 | uint64_t controller_busy_time[2]; | |
1001 | uint64_t power_cycles[2]; | |
1002 | uint64_t power_on_hours[2]; | |
1003 | uint64_t unsafe_shutdowns[2]; | |
1004 | uint64_t media_errors[2]; | |
1005 | uint64_t number_of_error_log_entries[2]; | |
1006 | uint8_t reserved2[320]; | |
1007 | } NvmeSmartLog; | |
1008 | ||
c62720f1 | 1009 | #define NVME_SMART_WARN_MAX 6 |
a3d9a352 FZ |
1010 | enum NvmeSmartWarn { |
1011 | NVME_SMART_SPARE = 1 << 0, | |
1012 | NVME_SMART_TEMPERATURE = 1 << 1, | |
1013 | NVME_SMART_RELIABILITY = 1 << 2, | |
1014 | NVME_SMART_MEDIA_READ_ONLY = 1 << 3, | |
1015 | NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, | |
c6d1b5c1 | 1016 | NVME_SMART_PMR_UNRELIABLE = 1 << 5, |
a3d9a352 FZ |
1017 | }; |
1018 | ||
62e8faa4 DF |
1019 | typedef struct NvmeEffectsLog { |
1020 | uint32_t acs[256]; | |
1021 | uint32_t iocs[256]; | |
1022 | uint8_t resv[2048]; | |
1023 | } NvmeEffectsLog; | |
1024 | ||
1025 | enum { | |
1026 | NVME_CMD_EFF_CSUPP = 1 << 0, | |
1027 | NVME_CMD_EFF_LBCC = 1 << 1, | |
1028 | NVME_CMD_EFF_NCC = 1 << 2, | |
1029 | NVME_CMD_EFF_NIC = 1 << 3, | |
1030 | NVME_CMD_EFF_CCC = 1 << 4, | |
1031 | NVME_CMD_EFF_CSE_MASK = 3 << 16, | |
1032 | NVME_CMD_EFF_UUID_SEL = 1 << 19, | |
1033 | }; | |
1034 | ||
c26f2173 | 1035 | enum NvmeLogIdentifier { |
771dbc3a KJ |
1036 | NVME_LOG_ERROR_INFO = 0x01, |
1037 | NVME_LOG_SMART_INFO = 0x02, | |
1038 | NVME_LOG_FW_SLOT_INFO = 0x03, | |
1039 | NVME_LOG_CHANGED_NSLIST = 0x04, | |
1040 | NVME_LOG_CMD_EFFECTS = 0x05, | |
1041 | NVME_LOG_ENDGRP = 0x09, | |
73064edf JD |
1042 | NVME_LOG_FDP_CONFS = 0x20, |
1043 | NVME_LOG_FDP_RUH_USAGE = 0x21, | |
1044 | NVME_LOG_FDP_STATS = 0x22, | |
1045 | NVME_LOG_FDP_EVENTS = 0x23, | |
a3d9a352 FZ |
1046 | }; |
1047 | ||
e989738f | 1048 | typedef struct QEMU_PACKED NvmePSD { |
a3d9a352 FZ |
1049 | uint16_t mp; |
1050 | uint16_t reserved; | |
1051 | uint32_t enlat; | |
1052 | uint32_t exlat; | |
1053 | uint8_t rrt; | |
1054 | uint8_t rrl; | |
1055 | uint8_t rwt; | |
1056 | uint8_t rwl; | |
1057 | uint8_t resv[16]; | |
1058 | } NvmePSD; | |
1059 | ||
645ce1a7 | 1060 | #define NVME_CONTROLLER_LIST_SIZE 2048 |
3e829fd4 KJ |
1061 | #define NVME_IDENTIFY_DATA_SIZE 4096 |
1062 | ||
141354d5 | 1063 | enum NvmeIdCns { |
922e6f4e NC |
1064 | NVME_ID_CNS_NS = 0x00, |
1065 | NVME_ID_CNS_CTRL = 0x01, | |
1066 | NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, | |
1067 | NVME_ID_CNS_NS_DESCR_LIST = 0x03, | |
1068 | NVME_ID_CNS_CS_NS = 0x05, | |
1069 | NVME_ID_CNS_CS_CTRL = 0x06, | |
1070 | NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, | |
1071 | NVME_ID_CNS_NS_PRESENT_LIST = 0x10, | |
1072 | NVME_ID_CNS_NS_PRESENT = 0x11, | |
23fb7dfe | 1073 | NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, |
5f4eb94d | 1074 | NVME_ID_CNS_CTRL_LIST = 0x13, |
5e6f963f | 1075 | NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14, |
99f48ae7 | 1076 | NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15, |
922e6f4e NC |
1077 | NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, |
1078 | NVME_ID_CNS_CS_NS_PRESENT = 0x1b, | |
1079 | NVME_ID_CNS_IO_COMMAND_SET = 0x1c, | |
3e829fd4 KJ |
1080 | }; |
1081 | ||
e989738f | 1082 | typedef struct QEMU_PACKED NvmeIdCtrl { |
a3d9a352 FZ |
1083 | uint16_t vid; |
1084 | uint16_t ssvid; | |
1085 | uint8_t sn[20]; | |
1086 | uint8_t mn[40]; | |
1087 | uint8_t fr[8]; | |
1088 | uint8_t rab; | |
1089 | uint8_t ieee[3]; | |
1090 | uint8_t cmic; | |
1091 | uint8_t mdts; | |
c26f2173 KJ |
1092 | uint16_t cntlid; |
1093 | uint32_t ver; | |
1094 | uint32_t rtd3r; | |
1095 | uint32_t rtd3e; | |
1096 | uint32_t oaes; | |
1097 | uint32_t ctratt; | |
c2a3640d KJ |
1098 | uint8_t rsvd100[11]; |
1099 | uint8_t cntrltype; | |
c26f2173 KJ |
1100 | uint8_t fguid[16]; |
1101 | uint8_t rsvd128[128]; | |
a3d9a352 FZ |
1102 | uint16_t oacs; |
1103 | uint8_t acl; | |
1104 | uint8_t aerl; | |
1105 | uint8_t frmw; | |
1106 | uint8_t lpa; | |
1107 | uint8_t elpe; | |
1108 | uint8_t npss; | |
c26f2173 KJ |
1109 | uint8_t avscc; |
1110 | uint8_t apsta; | |
1111 | uint16_t wctemp; | |
1112 | uint16_t cctemp; | |
1113 | uint16_t mtfa; | |
1114 | uint32_t hmpre; | |
1115 | uint32_t hmmin; | |
1116 | uint8_t tnvmcap[16]; | |
1117 | uint8_t unvmcap[16]; | |
1118 | uint32_t rpmbs; | |
1119 | uint16_t edstt; | |
1120 | uint8_t dsto; | |
1121 | uint8_t fwug; | |
1122 | uint16_t kas; | |
1123 | uint16_t hctma; | |
1124 | uint16_t mntmt; | |
1125 | uint16_t mxtmt; | |
1126 | uint32_t sanicap; | |
771dbc3a KJ |
1127 | uint8_t rsvd332[6]; |
1128 | uint16_t nsetidmax; | |
1129 | uint16_t endgidmax; | |
1130 | uint8_t rsvd342[170]; | |
a3d9a352 FZ |
1131 | uint8_t sqes; |
1132 | uint8_t cqes; | |
c26f2173 | 1133 | uint16_t maxcmd; |
a3d9a352 FZ |
1134 | uint32_t nn; |
1135 | uint16_t oncs; | |
1136 | uint16_t fuses; | |
1137 | uint8_t fna; | |
1138 | uint8_t vwc; | |
1139 | uint16_t awun; | |
1140 | uint16_t awupf; | |
c26f2173 KJ |
1141 | uint8_t nvscc; |
1142 | uint8_t rsvd531; | |
1143 | uint16_t acwu; | |
3862efff | 1144 | uint16_t ocfs; |
c26f2173 KJ |
1145 | uint32_t sgls; |
1146 | uint8_t rsvd540[228]; | |
1147 | uint8_t subnqn[256]; | |
1148 | uint8_t rsvd1024[1024]; | |
a3d9a352 FZ |
1149 | NvmePSD psd[32]; |
1150 | uint8_t vs[1024]; | |
1151 | } NvmeIdCtrl; | |
1152 | ||
e9ba46ee DF |
1153 | typedef struct NvmeIdCtrlZoned { |
1154 | uint8_t zasl; | |
1155 | uint8_t rsvd1[4095]; | |
1156 | } NvmeIdCtrlZoned; | |
1157 | ||
67ce28a1 GA |
1158 | typedef struct NvmeIdCtrlNvm { |
1159 | uint8_t vsl; | |
1160 | uint8_t wzsl; | |
1161 | uint8_t wusl; | |
1162 | uint8_t dmrl; | |
1163 | uint32_t dmrsl; | |
1164 | uint64_t dmsl; | |
1165 | uint8_t rsvd16[4080]; | |
1166 | } NvmeIdCtrlNvm; | |
1167 | ||
f432fdfa MI |
1168 | enum NvmeIdCtrlOaes { |
1169 | NVME_OAES_NS_ATTR = 1 << 8, | |
1170 | }; | |
1171 | ||
763c05df | 1172 | enum NvmeIdCtrlCtratt { |
771dbc3a | 1173 | NVME_CTRATT_ENDGRPS = 1 << 4, |
763c05df | 1174 | NVME_CTRATT_ELBAS = 1 << 15, |
73064edf | 1175 | NVME_CTRATT_FDPS = 1 << 19, |
763c05df NN |
1176 | }; |
1177 | ||
a3d9a352 | 1178 | enum NvmeIdCtrlOacs { |
e181d3da GA |
1179 | NVME_OACS_SECURITY = 1 << 0, |
1180 | NVME_OACS_FORMAT = 1 << 1, | |
1181 | NVME_OACS_FW = 1 << 2, | |
1182 | NVME_OACS_NS_MGMT = 1 << 3, | |
1183 | NVME_OACS_DIRECTIVES = 1 << 5, | |
1184 | NVME_OACS_DBBUF = 1 << 8, | |
a3d9a352 FZ |
1185 | }; |
1186 | ||
1187 | enum NvmeIdCtrlOncs { | |
1188 | NVME_ONCS_COMPARE = 1 << 0, | |
1189 | NVME_ONCS_WRITE_UNCORR = 1 << 1, | |
1190 | NVME_ONCS_DSM = 1 << 2, | |
69265150 | 1191 | NVME_ONCS_WRITE_ZEROES = 1 << 3, |
a3d9a352 FZ |
1192 | NVME_ONCS_FEATURES = 1 << 4, |
1193 | NVME_ONCS_RESRVATIONS = 1 << 5, | |
3036a626 | 1194 | NVME_ONCS_TIMESTAMP = 1 << 6, |
3e1da158 | 1195 | NVME_ONCS_VERIFY = 1 << 7, |
3862efff KJ |
1196 | NVME_ONCS_COPY = 1 << 8, |
1197 | }; | |
1198 | ||
1199 | enum NvmeIdCtrlOcfs { | |
44219b60 NN |
1200 | NVME_OCFS_COPY_FORMAT_0 = 1 << NVME_COPY_FORMAT_0, |
1201 | NVME_OCFS_COPY_FORMAT_1 = 1 << NVME_COPY_FORMAT_1, | |
a3d9a352 FZ |
1202 | }; |
1203 | ||
c9497328 GA |
1204 | enum NvmeIdctrlVwc { |
1205 | NVME_VWC_PRESENT = 1 << 0, | |
1206 | NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, | |
1207 | NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, | |
1208 | NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, | |
1209 | NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, | |
1210 | }; | |
1211 | ||
42a42e46 KJ |
1212 | enum NvmeIdCtrlFrmw { |
1213 | NVME_FRMW_SLOT1_RO = 1 << 0, | |
1214 | }; | |
1215 | ||
94a7897c | 1216 | enum NvmeIdCtrlLpa { |
2fbbecc5 | 1217 | NVME_LPA_NS_SMART = 1 << 0, |
62e8faa4 | 1218 | NVME_LPA_CSE = 1 << 1, |
94a7897c KJ |
1219 | NVME_LPA_EXTENDED = 1 << 2, |
1220 | }; | |
1221 | ||
66b7e9be MI |
1222 | enum NvmeIdCtrlCmic { |
1223 | NVME_CMIC_MULTI_CTRL = 1 << 1, | |
1224 | }; | |
1225 | ||
07a3dfa7 NN |
1226 | enum NvmeNsAttachmentOperation { |
1227 | NVME_NS_ATTACHMENT_ATTACH = 0x0, | |
1228 | NVME_NS_ATTACHMENT_DETACH = 0x1, | |
1229 | }; | |
1230 | ||
a3d9a352 FZ |
1231 | #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) |
1232 | #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) | |
1233 | #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) | |
1234 | #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) | |
1235 | ||
c26f2173 KJ |
1236 | #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) |
1237 | #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) | |
1238 | #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) | |
1239 | #define NVME_CTRL_SGLS_KEYED (0x1 << 2) | |
1240 | #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) | |
1241 | #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) | |
1242 | #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) | |
1243 | #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) | |
1244 | #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) | |
1245 | ||
a3d9a352 | 1246 | #define NVME_ARB_AB(arb) (arb & 0x7) |
1302e48e | 1247 | #define NVME_ARB_AB_NOLIMIT 0x7 |
a3d9a352 FZ |
1248 | #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) |
1249 | #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) | |
1250 | #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) | |
1251 | ||
1252 | #define NVME_INTC_THR(intc) (intc & 0xff) | |
1253 | #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) | |
1254 | ||
1302e48e KJ |
1255 | #define NVME_INTVC_NOCOALESCING (0x1 << 16) |
1256 | ||
c26f2173 KJ |
1257 | #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) |
1258 | #define NVME_TEMP_THSEL_OVER 0x0 | |
1259 | #define NVME_TEMP_THSEL_UNDER 0x1 | |
1260 | ||
1261 | #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) | |
1262 | #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 | |
1263 | ||
1264 | #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) | |
1265 | ||
5d5a5330 KJ |
1266 | #define NVME_AEC_SMART(aec) (aec & 0xff) |
1267 | #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) | |
1268 | #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) | |
771dbc3a | 1269 | #define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1) |
5d5a5330 | 1270 | |
54064e51 KJ |
1271 | #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) |
1272 | #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) | |
1273 | ||
a3d9a352 FZ |
1274 | enum NvmeFeatureIds { |
1275 | NVME_ARBITRATION = 0x1, | |
1276 | NVME_POWER_MANAGEMENT = 0x2, | |
1277 | NVME_LBA_RANGE_TYPE = 0x3, | |
1278 | NVME_TEMPERATURE_THRESHOLD = 0x4, | |
1279 | NVME_ERROR_RECOVERY = 0x5, | |
1280 | NVME_VOLATILE_WRITE_CACHE = 0x6, | |
1281 | NVME_NUMBER_OF_QUEUES = 0x7, | |
1282 | NVME_INTERRUPT_COALESCING = 0x8, | |
1283 | NVME_INTERRUPT_VECTOR_CONF = 0x9, | |
1284 | NVME_WRITE_ATOMICITY = 0xa, | |
1285 | NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, | |
3036a626 | 1286 | NVME_TIMESTAMP = 0xe, |
d0c0697b | 1287 | NVME_HOST_BEHAVIOR_SUPPORT = 0x16, |
141354d5 | 1288 | NVME_COMMAND_SET_PROFILE = 0x19, |
73064edf JD |
1289 | NVME_FDP_MODE = 0x1d, |
1290 | NVME_FDP_EVENTS = 0x1e, | |
1302e48e KJ |
1291 | NVME_SOFTWARE_PROGRESS_MARKER = 0x80, |
1292 | NVME_FID_MAX = 0x100, | |
a3d9a352 FZ |
1293 | }; |
1294 | ||
7c46310d KJ |
1295 | typedef enum NvmeFeatureCap { |
1296 | NVME_FEAT_CAP_SAVE = 1 << 0, | |
1297 | NVME_FEAT_CAP_NS = 1 << 1, | |
1298 | NVME_FEAT_CAP_CHANGE = 1 << 2, | |
1299 | } NvmeFeatureCap; | |
1300 | ||
1301 | typedef enum NvmeGetFeatureSelect { | |
1302 | NVME_GETFEAT_SELECT_CURRENT = 0x0, | |
1303 | NVME_GETFEAT_SELECT_DEFAULT = 0x1, | |
1304 | NVME_GETFEAT_SELECT_SAVED = 0x2, | |
1305 | NVME_GETFEAT_SELECT_CAP = 0x3, | |
1306 | } NvmeGetFeatureSelect; | |
1307 | ||
1302e48e KJ |
1308 | #define NVME_GETSETFEAT_FID_MASK 0xff |
1309 | #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) | |
1310 | ||
7c46310d KJ |
1311 | #define NVME_GETFEAT_SELECT_SHIFT 8 |
1312 | #define NVME_GETFEAT_SELECT_MASK 0x7 | |
1313 | #define NVME_GETFEAT_SELECT(dw10) \ | |
1314 | ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) | |
1315 | ||
1316 | #define NVME_SETFEAT_SAVE_SHIFT 31 | |
1317 | #define NVME_SETFEAT_SAVE_MASK 0x1 | |
1318 | #define NVME_SETFEAT_SAVE(dw10) \ | |
1319 | ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) | |
1320 | ||
e989738f | 1321 | typedef struct QEMU_PACKED NvmeRangeType { |
a3d9a352 FZ |
1322 | uint8_t type; |
1323 | uint8_t attributes; | |
1324 | uint8_t rsvd2[14]; | |
1325 | uint64_t slba; | |
1326 | uint64_t nlb; | |
1327 | uint8_t guid[16]; | |
1328 | uint8_t rsvd48[16]; | |
1329 | } NvmeRangeType; | |
1330 | ||
d0c0697b NN |
1331 | typedef struct NvmeHostBehaviorSupport { |
1332 | uint8_t acre; | |
1333 | uint8_t etdas; | |
1334 | uint8_t lbafee; | |
1335 | uint8_t rsvd3[509]; | |
1336 | } NvmeHostBehaviorSupport; | |
1337 | ||
e989738f | 1338 | typedef struct QEMU_PACKED NvmeLBAF { |
a3d9a352 FZ |
1339 | uint16_t ms; |
1340 | uint8_t ds; | |
1341 | uint8_t rp; | |
1342 | } NvmeLBAF; | |
1343 | ||
e9ba46ee DF |
1344 | typedef struct QEMU_PACKED NvmeLBAFE { |
1345 | uint64_t zsze; | |
1346 | uint8_t zdes; | |
1347 | uint8_t rsvd9[7]; | |
1348 | } NvmeLBAFE; | |
1349 | ||
7c46310d | 1350 | #define NVME_NSID_BROADCAST 0xffffffff |
44219b60 | 1351 | #define NVME_MAX_NLBAF 64 |
7c46310d | 1352 | |
e989738f | 1353 | typedef struct QEMU_PACKED NvmeIdNs { |
a3d9a352 FZ |
1354 | uint64_t nsze; |
1355 | uint64_t ncap; | |
1356 | uint64_t nuse; | |
1357 | uint8_t nsfeat; | |
1358 | uint8_t nlbaf; | |
1359 | uint8_t flbas; | |
1360 | uint8_t mc; | |
1361 | uint8_t dpc; | |
1362 | uint8_t dps; | |
e0dd95e3 ML |
1363 | uint8_t nmic; |
1364 | uint8_t rescap; | |
1365 | uint8_t fpi; | |
1366 | uint8_t dlfeat; | |
c26f2173 KJ |
1367 | uint16_t nawun; |
1368 | uint16_t nawupf; | |
1369 | uint16_t nacwu; | |
1370 | uint16_t nabsn; | |
1371 | uint16_t nabo; | |
1372 | uint16_t nabspf; | |
1373 | uint16_t noiob; | |
1374 | uint8_t nvmcap[16]; | |
6fd704a5 KJ |
1375 | uint16_t npwg; |
1376 | uint16_t npwa; | |
1377 | uint16_t npdg; | |
1378 | uint16_t npda; | |
1379 | uint16_t nows; | |
3862efff KJ |
1380 | uint16_t mssrl; |
1381 | uint32_t mcl; | |
1382 | uint8_t msrc; | |
771dbc3a KJ |
1383 | uint8_t rsvd81[18]; |
1384 | uint8_t nsattr; | |
1385 | uint16_t nvmsetid; | |
1386 | uint16_t endgid; | |
c26f2173 KJ |
1387 | uint8_t nguid[16]; |
1388 | uint64_t eui64; | |
44219b60 | 1389 | NvmeLBAF lbaf[NVME_MAX_NLBAF]; |
a3d9a352 FZ |
1390 | uint8_t vs[3712]; |
1391 | } NvmeIdNs; | |
1392 | ||
44219b60 NN |
1393 | #define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3) |
1394 | ||
1395 | typedef struct QEMU_PACKED NvmeIdNsNvm { | |
1396 | uint64_t lbstm; | |
1397 | uint8_t pic; | |
1398 | uint8_t rsvd9[3]; | |
1399 | uint32_t elbaf[NVME_MAX_NLBAF]; | |
1400 | uint8_t rsvd268[3828]; | |
1401 | } NvmeIdNsNvm; | |
1402 | ||
c26f2173 KJ |
1403 | typedef struct QEMU_PACKED NvmeIdNsDescr { |
1404 | uint8_t nidt; | |
1405 | uint8_t nidl; | |
1406 | uint8_t rsvd2[2]; | |
1407 | } NvmeIdNsDescr; | |
1408 | ||
141354d5 NC |
1409 | enum NvmeNsIdentifierLength { |
1410 | NVME_NIDL_EUI64 = 8, | |
1411 | NVME_NIDL_NGUID = 16, | |
1412 | NVME_NIDL_UUID = 16, | |
1413 | NVME_NIDL_CSI = 1, | |
c26f2173 KJ |
1414 | }; |
1415 | ||
1416 | enum NvmeNsIdentifierType { | |
141354d5 NC |
1417 | NVME_NIDT_EUI64 = 0x01, |
1418 | NVME_NIDT_NGUID = 0x02, | |
1419 | NVME_NIDT_UUID = 0x03, | |
1420 | NVME_NIDT_CSI = 0x04, | |
1421 | }; | |
1422 | ||
adc36b8d MI |
1423 | enum NvmeIdNsNmic { |
1424 | NVME_NMIC_NS_SHARED = 1 << 0, | |
1425 | }; | |
1426 | ||
141354d5 NC |
1427 | enum NvmeCsi { |
1428 | NVME_CSI_NVM = 0x00, | |
e9ba46ee | 1429 | NVME_CSI_ZONED = 0x02, |
c26f2173 | 1430 | }; |
e0dd95e3 | 1431 | |
141354d5 NC |
1432 | #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) |
1433 | ||
e9ba46ee DF |
1434 | typedef struct QEMU_PACKED NvmeIdNsZoned { |
1435 | uint16_t zoc; | |
1436 | uint16_t ozcs; | |
1437 | uint32_t mar; | |
1438 | uint32_t mor; | |
1439 | uint32_t rrl; | |
1440 | uint32_t frl; | |
e321b4cd KJ |
1441 | uint8_t rsvd12[24]; |
1442 | uint32_t numzrwa; | |
1443 | uint16_t zrwafg; | |
1444 | uint16_t zrwas; | |
1445 | uint8_t zrwacap; | |
1446 | uint8_t rsvd53[2763]; | |
e9ba46ee DF |
1447 | NvmeLBAFE lbafe[16]; |
1448 | uint8_t rsvd3072[768]; | |
1449 | uint8_t vs[256]; | |
1450 | } NvmeIdNsZoned; | |
1451 | ||
25872031 KJ |
1452 | enum NvmeIdNsZonedOzcs { |
1453 | NVME_ID_NS_ZONED_OZCS_RAZB = 1 << 0, | |
e321b4cd KJ |
1454 | NVME_ID_NS_ZONED_OZCS_ZRWASUP = 1 << 1, |
1455 | }; | |
1456 | ||
1457 | enum NvmeIdNsZonedZrwacap { | |
1458 | NVME_ID_NS_ZONED_ZRWACAP_EXPFLUSHSUP = 1 << 0, | |
25872031 KJ |
1459 | }; |
1460 | ||
e0dd95e3 ML |
1461 | /*Deallocate Logical Block Features*/ |
1462 | #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) | |
1463 | #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) | |
1464 | ||
1465 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) | |
1466 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 | |
1467 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 | |
1468 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 | |
1469 | ||
1470 | ||
a3d9a352 | 1471 | #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) |
54064e51 | 1472 | #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) |
a3d9a352 FZ |
1473 | #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) |
1474 | #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) | |
1475 | #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) | |
1476 | #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) | |
1477 | #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) | |
1478 | #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) | |
1479 | #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) | |
1480 | #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) | |
1481 | #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) | |
1482 | #define NVME_ID_NS_DPC_TYPE_MASK 0x7 | |
1483 | ||
1484 | enum NvmeIdNsDps { | |
146f720c KJ |
1485 | NVME_ID_NS_DPS_TYPE_NONE = 0, |
1486 | NVME_ID_NS_DPS_TYPE_1 = 1, | |
1487 | NVME_ID_NS_DPS_TYPE_2 = 2, | |
1488 | NVME_ID_NS_DPS_TYPE_3 = 3, | |
1489 | NVME_ID_NS_DPS_TYPE_MASK = 0x7, | |
1490 | NVME_ID_NS_DPS_FIRST_EIGHT = 8, | |
a3d9a352 FZ |
1491 | }; |
1492 | ||
18de1526 GA |
1493 | enum NvmeIdNsFlbas { |
1494 | NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, | |
1495 | }; | |
1496 | ||
1497 | enum NvmeIdNsMc { | |
1498 | NVME_ID_NS_MC_EXTENDED = 1 << 0, | |
1499 | NVME_ID_NS_MC_SEPARATE = 1 << 1, | |
1500 | }; | |
1501 | ||
146f720c KJ |
1502 | #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) |
1503 | ||
44219b60 NN |
1504 | enum NvmePIFormat { |
1505 | NVME_PI_GUARD_16 = 0, | |
1506 | NVME_PI_GUARD_64 = 2, | |
1507 | }; | |
1508 | ||
1509 | typedef union NvmeDifTuple { | |
1510 | struct { | |
1511 | uint16_t guard; | |
1512 | uint16_t apptag; | |
1513 | uint32_t reftag; | |
1514 | } g16; | |
1515 | ||
1516 | struct { | |
1517 | uint64_t guard; | |
1518 | uint16_t apptag; | |
1519 | uint8_t sr[6]; | |
1520 | } g64; | |
146f720c KJ |
1521 | } NvmeDifTuple; |
1522 | ||
e9ba46ee DF |
1523 | enum NvmeZoneAttr { |
1524 | NVME_ZA_FINISHED_BY_CTLR = 1 << 0, | |
1525 | NVME_ZA_FINISH_RECOMMENDED = 1 << 1, | |
1526 | NVME_ZA_RESET_RECOMMENDED = 1 << 2, | |
e321b4cd | 1527 | NVME_ZA_ZRWA_VALID = 1 << 3, |
e9ba46ee DF |
1528 | NVME_ZA_ZD_EXT_VALID = 1 << 7, |
1529 | }; | |
1530 | ||
1531 | typedef struct QEMU_PACKED NvmeZoneReportHeader { | |
1532 | uint64_t nr_zones; | |
1533 | uint8_t rsvd[56]; | |
1534 | } NvmeZoneReportHeader; | |
1535 | ||
1536 | enum NvmeZoneReceiveAction { | |
1537 | NVME_ZONE_REPORT = 0, | |
1538 | NVME_ZONE_REPORT_EXTENDED = 1, | |
1539 | }; | |
1540 | ||
1541 | enum NvmeZoneReportType { | |
1542 | NVME_ZONE_REPORT_ALL = 0, | |
1543 | NVME_ZONE_REPORT_EMPTY = 1, | |
1544 | NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, | |
1545 | NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, | |
1546 | NVME_ZONE_REPORT_CLOSED = 4, | |
1547 | NVME_ZONE_REPORT_FULL = 5, | |
1548 | NVME_ZONE_REPORT_READ_ONLY = 6, | |
1549 | NVME_ZONE_REPORT_OFFLINE = 7, | |
1550 | }; | |
1551 | ||
1552 | enum NvmeZoneType { | |
1553 | NVME_ZONE_TYPE_RESERVED = 0x00, | |
1554 | NVME_ZONE_TYPE_SEQ_WRITE = 0x02, | |
1555 | }; | |
1556 | ||
6190d92f KJ |
1557 | typedef struct QEMU_PACKED NvmeZoneSendCmd { |
1558 | uint8_t opcode; | |
1559 | uint8_t flags; | |
1560 | uint16_t cid; | |
1561 | uint32_t nsid; | |
1562 | uint32_t rsvd8[4]; | |
1563 | NvmeCmdDptr dptr; | |
1564 | uint64_t slba; | |
1565 | uint32_t rsvd48; | |
1566 | uint8_t zsa; | |
1567 | uint8_t zsflags; | |
1568 | uint8_t rsvd54[2]; | |
1569 | uint32_t rsvd56[2]; | |
1570 | } NvmeZoneSendCmd; | |
1571 | ||
e9ba46ee DF |
1572 | enum NvmeZoneSendAction { |
1573 | NVME_ZONE_ACTION_RSD = 0x00, | |
1574 | NVME_ZONE_ACTION_CLOSE = 0x01, | |
1575 | NVME_ZONE_ACTION_FINISH = 0x02, | |
1576 | NVME_ZONE_ACTION_OPEN = 0x03, | |
1577 | NVME_ZONE_ACTION_RESET = 0x04, | |
1578 | NVME_ZONE_ACTION_OFFLINE = 0x05, | |
1579 | NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, | |
e321b4cd | 1580 | NVME_ZONE_ACTION_ZRWA_FLUSH = 0x11, |
e9ba46ee DF |
1581 | }; |
1582 | ||
6190d92f KJ |
1583 | enum { |
1584 | NVME_ZSFLAG_SELECT_ALL = 1 << 0, | |
e321b4cd | 1585 | NVME_ZSFLAG_ZRWA_ALLOC = 1 << 1, |
6190d92f KJ |
1586 | }; |
1587 | ||
e9ba46ee DF |
1588 | typedef struct QEMU_PACKED NvmeZoneDescr { |
1589 | uint8_t zt; | |
1590 | uint8_t zs; | |
1591 | uint8_t za; | |
1592 | uint8_t rsvd3[5]; | |
1593 | uint64_t zcap; | |
1594 | uint64_t zslba; | |
1595 | uint64_t wp; | |
1596 | uint8_t rsvd32[32]; | |
1597 | } NvmeZoneDescr; | |
1598 | ||
b05fde28 | 1599 | typedef enum NvmeZoneState { |
e9ba46ee DF |
1600 | NVME_ZONE_STATE_RESERVED = 0x00, |
1601 | NVME_ZONE_STATE_EMPTY = 0x01, | |
1602 | NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, | |
1603 | NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, | |
1604 | NVME_ZONE_STATE_CLOSED = 0x04, | |
312c3531 GA |
1605 | NVME_ZONE_STATE_READ_ONLY = 0x0d, |
1606 | NVME_ZONE_STATE_FULL = 0x0e, | |
1607 | NVME_ZONE_STATE_OFFLINE = 0x0f, | |
b05fde28 | 1608 | } NvmeZoneState; |
e9ba46ee | 1609 | |
5e6f963f LM |
1610 | typedef struct QEMU_PACKED NvmePriCtrlCap { |
1611 | uint16_t cntlid; | |
1612 | uint16_t portid; | |
1613 | uint8_t crt; | |
1614 | uint8_t rsvd5[27]; | |
1615 | uint32_t vqfrt; | |
1616 | uint32_t vqrfa; | |
1617 | uint16_t vqrfap; | |
1618 | uint16_t vqprt; | |
1619 | uint16_t vqfrsm; | |
1620 | uint16_t vqgran; | |
1621 | uint8_t rsvd48[16]; | |
1622 | uint32_t vifrt; | |
1623 | uint32_t virfa; | |
1624 | uint16_t virfap; | |
1625 | uint16_t viprt; | |
1626 | uint16_t vifrsm; | |
1627 | uint16_t vigran; | |
1628 | uint8_t rsvd80[4016]; | |
1629 | } NvmePriCtrlCap; | |
1630 | ||
746d42b1 ŁG |
1631 | typedef enum NvmePriCtrlCapCrt { |
1632 | NVME_CRT_VQ = 1 << 0, | |
1633 | NVME_CRT_VI = 1 << 1, | |
1634 | } NvmePriCtrlCapCrt; | |
1635 | ||
99f48ae7 LM |
1636 | typedef struct QEMU_PACKED NvmeSecCtrlEntry { |
1637 | uint16_t scid; | |
1638 | uint16_t pcid; | |
1639 | uint8_t scs; | |
1640 | uint8_t rsvd5[3]; | |
1641 | uint16_t vfn; | |
1642 | uint16_t nvq; | |
1643 | uint16_t nvi; | |
1644 | uint8_t rsvd14[18]; | |
1645 | } NvmeSecCtrlEntry; | |
1646 | ||
1647 | typedef struct QEMU_PACKED NvmeSecCtrlList { | |
1648 | uint8_t numcntl; | |
1649 | uint8_t rsvd1[31]; | |
1650 | NvmeSecCtrlEntry sec[127]; | |
1651 | } NvmeSecCtrlList; | |
1652 | ||
11871f53 ŁG |
1653 | typedef enum NvmeVirtMngmtAction { |
1654 | NVME_VIRT_MNGMT_ACTION_PRM_ALLOC = 0x01, | |
1655 | NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE = 0x07, | |
1656 | NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN = 0x08, | |
1657 | NVME_VIRT_MNGMT_ACTION_SEC_ONLINE = 0x09, | |
1658 | } NvmeVirtMngmtAction; | |
1659 | ||
1660 | typedef enum NvmeVirtualResourceType { | |
1661 | NVME_VIRT_RES_QUEUE = 0x00, | |
1662 | NVME_VIRT_RES_INTERRUPT = 0x01, | |
1663 | } NvmeVirtualResourceType; | |
1664 | ||
e181d3da GA |
1665 | typedef struct NvmeDirectiveIdentify { |
1666 | uint8_t supported; | |
1667 | uint8_t unused1[31]; | |
1668 | uint8_t enabled; | |
1669 | uint8_t unused33[31]; | |
73064edf JD |
1670 | uint8_t persistent; |
1671 | uint8_t unused65[31]; | |
1672 | uint8_t rsvd64[4000]; | |
e181d3da GA |
1673 | } NvmeDirectiveIdentify; |
1674 | ||
e181d3da | 1675 | enum NvmeDirectiveTypes { |
73064edf JD |
1676 | NVME_DIRECTIVE_IDENTIFY = 0x0, |
1677 | NVME_DIRECTIVE_DATA_PLACEMENT = 0x2, | |
e181d3da GA |
1678 | }; |
1679 | ||
1680 | enum NvmeDirectiveOperations { | |
1681 | NVME_DIRECTIVE_RETURN_PARAMS = 0x1, | |
1682 | }; | |
1683 | ||
73064edf JD |
1684 | typedef struct QEMU_PACKED NvmeFdpConfsHdr { |
1685 | uint16_t num_confs; | |
1686 | uint8_t version; | |
1687 | uint8_t rsvd3; | |
1688 | uint32_t size; | |
1689 | uint8_t rsvd8[8]; | |
1690 | } NvmeFdpConfsHdr; | |
1691 | ||
1692 | REG8(FDPA, 0x0) | |
1693 | FIELD(FDPA, RGIF, 0, 4) | |
1694 | FIELD(FDPA, VWC, 4, 1) | |
1695 | FIELD(FDPA, VALID, 7, 1); | |
1696 | ||
1697 | typedef struct QEMU_PACKED NvmeFdpDescrHdr { | |
1698 | uint16_t descr_size; | |
1699 | uint8_t fdpa; | |
1700 | uint8_t vss; | |
1701 | uint32_t nrg; | |
1702 | uint16_t nruh; | |
1703 | uint16_t maxpids; | |
1704 | uint32_t nnss; | |
1705 | uint64_t runs; | |
1706 | uint32_t erutl; | |
1707 | uint8_t rsvd28[36]; | |
1708 | } NvmeFdpDescrHdr; | |
1709 | ||
1710 | enum NvmeRuhType { | |
1711 | NVME_RUHT_INITIALLY_ISOLATED = 1, | |
1712 | NVME_RUHT_PERSISTENTLY_ISOLATED = 2, | |
1713 | }; | |
1714 | ||
1715 | typedef struct QEMU_PACKED NvmeRuhDescr { | |
1716 | uint8_t ruht; | |
1717 | uint8_t rsvd1[3]; | |
1718 | } NvmeRuhDescr; | |
1719 | ||
1720 | typedef struct QEMU_PACKED NvmeRuhuLog { | |
1721 | uint16_t nruh; | |
1722 | uint8_t rsvd2[6]; | |
1723 | } NvmeRuhuLog; | |
1724 | ||
1725 | enum NvmeRuhAttributes { | |
1726 | NVME_RUHA_UNUSED = 0, | |
1727 | NVME_RUHA_HOST = 1, | |
1728 | NVME_RUHA_CTRL = 2, | |
1729 | }; | |
1730 | ||
1731 | typedef struct QEMU_PACKED NvmeRuhuDescr { | |
1732 | uint8_t ruha; | |
1733 | uint8_t rsvd1[7]; | |
1734 | } NvmeRuhuDescr; | |
1735 | ||
1736 | typedef struct QEMU_PACKED NvmeFdpStatsLog { | |
1737 | uint64_t hbmw[2]; | |
1738 | uint64_t mbmw[2]; | |
1739 | uint64_t mbe[2]; | |
1740 | uint8_t rsvd48[16]; | |
1741 | } NvmeFdpStatsLog; | |
1742 | ||
1743 | typedef struct QEMU_PACKED NvmeFdpEventsLog { | |
1744 | uint32_t num_events; | |
1745 | uint8_t rsvd4[60]; | |
1746 | } NvmeFdpEventsLog; | |
1747 | ||
1748 | enum NvmeFdpEventType { | |
1749 | FDP_EVT_RU_NOT_FULLY_WRITTEN = 0x0, | |
1750 | FDP_EVT_RU_ATL_EXCEEDED = 0x1, | |
1751 | FDP_EVT_CTRL_RESET_RUH = 0x2, | |
1752 | FDP_EVT_INVALID_PID = 0x3, | |
1753 | FDP_EVT_MEDIA_REALLOC = 0x80, | |
1754 | FDP_EVT_RUH_IMPLICIT_RU_CHANGE = 0x81, | |
1755 | }; | |
1756 | ||
1757 | enum NvmeFdpEventFlags { | |
1758 | FDPEF_PIV = 1 << 0, | |
1759 | FDPEF_NSIDV = 1 << 1, | |
1760 | FDPEF_LV = 1 << 2, | |
1761 | }; | |
1762 | ||
1763 | typedef struct QEMU_PACKED NvmeFdpEvent { | |
1764 | uint8_t type; | |
1765 | uint8_t flags; | |
1766 | uint16_t pid; | |
1767 | uint64_t timestamp; | |
1768 | uint32_t nsid; | |
1769 | uint64_t type_specific[2]; | |
1770 | uint16_t rgid; | |
1771 | uint8_t ruhid; | |
1772 | uint8_t rsvd35[5]; | |
1773 | uint64_t vendor[3]; | |
1774 | } NvmeFdpEvent; | |
1775 | ||
1776 | typedef struct QEMU_PACKED NvmePhidList { | |
1777 | uint16_t nnruhd; | |
1778 | uint8_t rsvd2[6]; | |
1779 | } NvmePhidList; | |
1780 | ||
1781 | typedef struct QEMU_PACKED NvmePhidDescr { | |
1782 | uint8_t ruht; | |
1783 | uint8_t rsvd1; | |
1784 | uint16_t ruhid; | |
1785 | } NvmePhidDescr; | |
1786 | ||
1787 | REG32(FEAT_FDP, 0x0) | |
1788 | FIELD(FEAT_FDP, FDPE, 0, 1) | |
1789 | FIELD(FEAT_FDP, CONF_NDX, 8, 8); | |
1790 | ||
1791 | typedef struct QEMU_PACKED NvmeFdpEventDescr { | |
1792 | uint8_t evt; | |
1793 | uint8_t evta; | |
1794 | } NvmeFdpEventDescr; | |
1795 | ||
1796 | REG32(NVME_IOMR, 0x0) | |
1797 | FIELD(NVME_IOMR, MO, 0, 8) | |
1798 | FIELD(NVME_IOMR, MOS, 16, 16); | |
1799 | ||
1800 | enum NvmeIomr2Mo { | |
1801 | NVME_IOMR_MO_NOP = 0x0, | |
1802 | NVME_IOMR_MO_RUH_STATUS = 0x1, | |
1803 | NVME_IOMR_MO_VENDOR_SPECIFIC = 0x255, | |
1804 | }; | |
1805 | ||
1806 | typedef struct QEMU_PACKED NvmeRuhStatus { | |
1807 | uint8_t rsvd0[14]; | |
1808 | uint16_t nruhsd; | |
1809 | } NvmeRuhStatus; | |
1810 | ||
1811 | typedef struct QEMU_PACKED NvmeRuhStatusDescr { | |
1812 | uint16_t pid; | |
1813 | uint16_t ruhid; | |
1814 | uint32_t earutr; | |
1815 | uint64_t ruamw; | |
1816 | uint8_t rsvd16[16]; | |
1817 | } NvmeRuhStatusDescr; | |
1818 | ||
1819 | REG32(NVME_IOMS, 0x0) | |
1820 | FIELD(NVME_IOMS, MO, 0, 8) | |
1821 | FIELD(NVME_IOMS, MOS, 16, 16); | |
1822 | ||
1823 | enum NvmeIoms2Mo { | |
1824 | NVME_IOMS_MO_NOP = 0x0, | |
1825 | NVME_IOMS_MO_RUH_UPDATE = 0x1, | |
1826 | }; | |
1827 | ||
a3d9a352 FZ |
1828 | static inline void _nvme_check_size(void) |
1829 | { | |
74e18435 | 1830 | QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); |
a3d9a352 | 1831 | QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); |
e9ba46ee | 1832 | QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); |
a3d9a352 FZ |
1833 | QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); |
1834 | QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); | |
44219b60 NN |
1835 | QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat0) != 32); |
1836 | QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat1) != 40); | |
a3d9a352 FZ |
1837 | QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); |
1838 | QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); | |
1839 | QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); | |
1840 | QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); | |
1841 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); | |
1842 | QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); | |
1843 | QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); | |
3862efff | 1844 | QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); |
a3d9a352 | 1845 | QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); |
d0c0697b | 1846 | QEMU_BUILD_BUG_ON(sizeof(NvmeHostBehaviorSupport) != 512); |
a3d9a352 FZ |
1847 | QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); |
1848 | QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); | |
1849 | QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); | |
62e8faa4 | 1850 | QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); |
a3d9a352 | 1851 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); |
e9ba46ee | 1852 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); |
67ce28a1 | 1853 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); |
e9ba46ee DF |
1854 | QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); |
1855 | QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); | |
a3d9a352 | 1856 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); |
44219b60 | 1857 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096); |
e9ba46ee | 1858 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); |
c26f2173 KJ |
1859 | QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); |
1860 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); | |
e9ba46ee | 1861 | QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); |
44219b60 | 1862 | QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16); |
5e6f963f | 1863 | QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096); |
99f48ae7 LM |
1864 | QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32); |
1865 | QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096); | |
771dbc3a | 1866 | QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512); |
e181d3da | 1867 | QEMU_BUILD_BUG_ON(sizeof(NvmeDirectiveIdentify) != 4096); |
a3d9a352 FZ |
1868 | } |
1869 | #endif |