[mirror_ubuntu-artful-kernel.git] / include / drm / bridge / dw_hdmi.h

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __DW_HDMI__
#define __DW_HDMI__

#include <drm/drmP.h>

struct dw_hdmi;

/**
 * DOC: Supported input formats and encodings
 *
 * Depending on the Hardware configuration of the Controller IP, it supports
 * a subset of the following input formats and encodings on its internal
 * 48bit bus.
 *
 * +----------------------+----------------------------------+------------------------------+
 * | Format Name          | Format Code                      | Encodings                    |
 * +----------------------+----------------------------------+------------------------------+
 * | RGB 4:4:4 8bit       | ``MEDIA_BUS_FMT_RGB888_1X24``    | ``V4L2_YCBCR_ENC_DEFAULT``   |
 * +----------------------+----------------------------------+------------------------------+
 * | RGB 4:4:4 10bits     | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
 * +----------------------+----------------------------------+------------------------------+
 * | RGB 4:4:4 12bits     | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
 * +----------------------+----------------------------------+------------------------------+
 * | RGB 4:4:4 16bits     | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:4:4 8bit     | ``MEDIA_BUS_FMT_YUV8_1X24``      | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:4:4 10bits   | ``MEDIA_BUS_FMT_YUV10_1X30``     | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:4:4 12bits   | ``MEDIA_BUS_FMT_YUV12_1X36``     | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:4:4 16bits   | ``MEDIA_BUS_FMT_YUV16_1X48``     | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:2 8bit     | ``MEDIA_BUS_FMT_UYVY8_1X16``     | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:2 10bits   | ``MEDIA_BUS_FMT_UYVY10_1X20``    | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:2 12bits   | ``MEDIA_BUS_FMT_UYVY12_1X24``    | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:0 8bit     | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:0 10bits   | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:0 12bits   | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 * | YCbCr 4:2:0 16bits   | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601``       |
 * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
 * +----------------------+----------------------------------+------------------------------+
 */

enum {
	DW_HDMI_RES_8,
	DW_HDMI_RES_10,
	DW_HDMI_RES_12,
	DW_HDMI_RES_MAX,
};

enum dw_hdmi_phy_type {
	DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
	DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
	DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
	DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
	DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
	DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
	DW_HDMI_PHY_VENDOR_PHY = 0xfe,
};

struct dw_hdmi_mpll_config {
	unsigned long mpixelclock;
	struct {
		u16 cpce;
		u16 gmp;
	} res[DW_HDMI_RES_MAX];
};

struct dw_hdmi_curr_ctrl {
	unsigned long mpixelclock;
	u16 curr[DW_HDMI_RES_MAX];
};

struct dw_hdmi_phy_config {
	unsigned long mpixelclock;
	u16 sym_ctr;    /*clock symbol and transmitter control*/
	u16 term;       /*transmission termination value*/
	u16 vlev_ctr;   /* voltage level control */
};

struct dw_hdmi_phy_ops {
	int (*init)(struct dw_hdmi *hdmi, void *data,
		    struct drm_display_mode *mode);
	void (*disable)(struct dw_hdmi *hdmi, void *data);
	enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
	void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
			   bool force, bool disabled, bool rxsense);
	void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
};

struct dw_hdmi_plat_data {
	struct regmap *regm;
	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
					   const struct drm_display_mode *mode);
	unsigned long input_bus_format;
	unsigned long input_bus_encoding;

	/* Vendor PHY support */
	const struct dw_hdmi_phy_ops *phy_ops;
	const char *phy_name;
	void *phy_data;

	/* Synopsys PHY support */
	const struct dw_hdmi_mpll_config *mpll_cfg;
	const struct dw_hdmi_curr_ctrl *cur_ctr;
	const struct dw_hdmi_phy_config *phy_config;
	int (*configure_phy)(struct dw_hdmi *hdmi,
			     const struct dw_hdmi_plat_data *pdata,
			     unsigned long mpixelclock);
};

int dw_hdmi_probe(struct platform_device *pdev,
		  const struct dw_hdmi_plat_data *plat_data);
void dw_hdmi_remove(struct platform_device *pdev);
void dw_hdmi_unbind(struct device *dev);
int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
		 const struct dw_hdmi_plat_data *plat_data);

void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense);

void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);

/* PHY configuration */
void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
			   unsigned char addr);

#endif /* __IMX_HDMI_H__ */
Commit	Line	Data
b21f4b65 AY	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#ifndef __DW_HDMI__
	11	#define __DW_HDMI__
	12
	13	#include <drm/drmP.h>
	14
b5814fff RK	15	struct dw_hdmi;
b5814fff RK	16
def23aa7 NA	17	/**
	18	* DOC: Supported input formats and encodings
	19	*
	20	* Depending on the Hardware configuration of the Controller IP, it supports
	21	* a subset of the following input formats and encodings on its internal
	22	* 48bit bus.
	23	*
	24	* +----------------------+----------------------------------+------------------------------+
38cb266a	25	* \| Format Name \| Format Code \| Encodings \|
def23aa7	26	* +----------------------+----------------------------------+------------------------------+
38cb266a	27	* \| RGB 4:4:4 8bit \| ``MEDIA_BUS_FMT_RGB888_1X24`` \| ``V4L2_YCBCR_ENC_DEFAULT`` \|
def23aa7	28	* +----------------------+----------------------------------+------------------------------+
38cb266a	29	* \| RGB 4:4:4 10bits \| ``MEDIA_BUS_FMT_RGB101010_1X30`` \| ``V4L2_YCBCR_ENC_DEFAULT`` \|
def23aa7	30	* +----------------------+----------------------------------+------------------------------+
38cb266a	31	* \| RGB 4:4:4 12bits \| ``MEDIA_BUS_FMT_RGB121212_1X36`` \| ``V4L2_YCBCR_ENC_DEFAULT`` \|
def23aa7	32	* +----------------------+----------------------------------+------------------------------+
38cb266a	33	* \| RGB 4:4:4 16bits \| ``MEDIA_BUS_FMT_RGB161616_1X48`` \| ``V4L2_YCBCR_ENC_DEFAULT`` \|
def23aa7	34	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	35	* \| YCbCr 4:4:4 8bit \| ``MEDIA_BUS_FMT_YUV8_1X24`` \| ``V4L2_YCBCR_ENC_601`` \|
	36	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
	37	* \| \| \| or ``V4L2_YCBCR_ENC_XV601`` \|
	38	* \| \| \| or ``V4L2_YCBCR_ENC_XV709`` \|
def23aa7	39	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	40	* \| YCbCr 4:4:4 10bits \| ``MEDIA_BUS_FMT_YUV10_1X30`` \| ``V4L2_YCBCR_ENC_601`` \|
	41	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
	42	* \| \| \| or ``V4L2_YCBCR_ENC_XV601`` \|
	43	* \| \| \| or ``V4L2_YCBCR_ENC_XV709`` \|
def23aa7	44	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	45	* \| YCbCr 4:4:4 12bits \| ``MEDIA_BUS_FMT_YUV12_1X36`` \| ``V4L2_YCBCR_ENC_601`` \|
	46	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
	47	* \| \| \| or ``V4L2_YCBCR_ENC_XV601`` \|
	48	* \| \| \| or ``V4L2_YCBCR_ENC_XV709`` \|
def23aa7	49	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	50	* \| YCbCr 4:4:4 16bits \| ``MEDIA_BUS_FMT_YUV16_1X48`` \| ``V4L2_YCBCR_ENC_601`` \|
	51	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
	52	* \| \| \| or ``V4L2_YCBCR_ENC_XV601`` \|
	53	* \| \| \| or ``V4L2_YCBCR_ENC_XV709`` \|
def23aa7	54	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	55	* \| YCbCr 4:2:2 8bit \| ``MEDIA_BUS_FMT_UYVY8_1X16`` \| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	56	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7	57	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	58	* \| YCbCr 4:2:2 10bits \| ``MEDIA_BUS_FMT_UYVY10_1X20`` \| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	59	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7	60	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	61	* \| YCbCr 4:2:2 12bits \| ``MEDIA_BUS_FMT_UYVY12_1X24`` \| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	62	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7	63	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	64	* \| YCbCr 4:2:0 8bit \| ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` \| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	65	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7	66	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	67	* \| YCbCr 4:2:0 10bits \| ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``\| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	68	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7	69	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	70	* \| YCbCr 4:2:0 12bits \| ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``\| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	71	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7	72	* +----------------------+----------------------------------+------------------------------+
38cb266a JC	73	* \| YCbCr 4:2:0 16bits \| ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``\| ``V4L2_YCBCR_ENC_601`` \|
38cb266a JC	74	* \| \| \| or ``V4L2_YCBCR_ENC_709`` \|
def23aa7 NA	75	* +----------------------+----------------------------------+------------------------------+
	76	*/
	77
b21f4b65 AY	78	enum {
	79	DW_HDMI_RES_8,
	80	DW_HDMI_RES_10,
	81	DW_HDMI_RES_12,
	82	DW_HDMI_RES_MAX,
	83	};
	84
faba6c3c LP	85	enum dw_hdmi_phy_type {
	86	DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
	87	DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
	88	DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
	89	DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
	90	DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
	91	DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
	92	DW_HDMI_PHY_VENDOR_PHY = 0xfe,
	93	};
	94
b21f4b65 AY	95	struct dw_hdmi_mpll_config {
	96	unsigned long mpixelclock;
	97	struct {
	98	u16 cpce;
	99	u16 gmp;
	100	} res[DW_HDMI_RES_MAX];
	101	};
	102
	103	struct dw_hdmi_curr_ctrl {
	104	unsigned long mpixelclock;
	105	u16 curr[DW_HDMI_RES_MAX];
	106	};
	107
034705a4	108	struct dw_hdmi_phy_config {
b21f4b65 AY	109	unsigned long mpixelclock;
	110	u16 sym_ctr; /clock symbol and transmitter control/
	111	u16 term; /transmission termination value/
034705a4	112	u16 vlev_ctr; /* voltage level control */
b21f4b65 AY	113	};
b21f4b65 AY	114
f1585f6e LP	115	struct dw_hdmi_phy_ops {
	116	int (init)(struct dw_hdmi hdmi, void *data,
	117	struct drm_display_mode *mode);
	118	void (disable)(struct dw_hdmi hdmi, void *data);
	119	enum drm_connector_status (read_hpd)(struct dw_hdmi hdmi, void *data);
386d3299 NA	120	void (update_hpd)(struct dw_hdmi hdmi, void *data,
	121	bool force, bool disabled, bool rxsense);
	122	void (setup_hpd)(struct dw_hdmi hdmi, void *data);
f1585f6e LP	123	};
f1585f6e LP	124
b21f4b65	125	struct dw_hdmi_plat_data {
80e2f979	126	struct regmap *regm;
f1585f6e	127	enum drm_mode_status (mode_valid)(struct drm_connector connector,
b0febde7	128	const struct drm_display_mode *mode);
def23aa7 NA	129	unsigned long input_bus_format;
def23aa7 NA	130	unsigned long input_bus_encoding;
f1585f6e LP	131
	132	/* Vendor PHY support */
	133	const struct dw_hdmi_phy_ops *phy_ops;
	134	const char *phy_name;
	135	void *phy_data;
	136
	137	/* Synopsys PHY support */
b21f4b65 AY	138	const struct dw_hdmi_mpll_config *mpll_cfg;
b21f4b65 AY	139	const struct dw_hdmi_curr_ctrl *cur_ctr;
034705a4	140	const struct dw_hdmi_phy_config *phy_config;
2ef9dfed KB	141	int (configure_phy)(struct dw_hdmi hdmi,
	142	const struct dw_hdmi_plat_data *pdata,
	143	unsigned long mpixelclock);
b21f4b65 AY	144	};
b21f4b65 AY	145
69497eb9 LP	146	int dw_hdmi_probe(struct platform_device *pdev,
	147	const struct dw_hdmi_plat_data *plat_data);
	148	void dw_hdmi_remove(struct platform_device *pdev);
ecaa98f1	149	void dw_hdmi_unbind(struct device *dev);
c608119d	150	int dw_hdmi_bind(struct platform_device pdev, struct drm_encoder encoder,
b21f4b65	151	const struct dw_hdmi_plat_data *plat_data);
b5814fff	152
386d3299 NA	153	void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense);
386d3299 NA	154
b5814fff	155	void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
b90120a9 RK	156	void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
b90120a9 RK	157	void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
b5814fff	158
2ef9dfed KB	159	/* PHY configuration */
	160	void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
	161	unsigned char addr);
	162
b21f4b65	163	#endif /* __IMX_HDMI_H__ */