projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 00c635e5 AH |
1 | /* |
| 2 | * Defines for Mobile High-Definition Link (MHL) interface | |
| 3 | * | |
| 4 | * Copyright (C) 2015, Samsung Electronics, Co., Ltd. | |
| 5 | * Andrzej Hajda <a.hajda@samsung.com> | |
| 6 | * | |
| 7 | * Based on MHL driver for Android devices. | |
| 8 | * Copyright (C) 2013-2014 Silicon Image, Inc. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef __MHL_H__ | |
| 16 | #define __MHL_H__ | |
| 17 | ||
| 981b3f37 AH |
18 | #include <linux/types.h> |
| 19 | ||
| 00c635e5 AH |
20 | /* Device Capabilities Registers */ |
| 21 | enum { | |
| 22 | MHL_DCAP_DEV_STATE, | |
| 23 | MHL_DCAP_MHL_VERSION, | |
| 24 | MHL_DCAP_CAT, | |
| 25 | MHL_DCAP_ADOPTER_ID_H, | |
| 26 | MHL_DCAP_ADOPTER_ID_L, | |
| 27 | MHL_DCAP_VID_LINK_MODE, | |
| 28 | MHL_DCAP_AUD_LINK_MODE, | |
| 29 | MHL_DCAP_VIDEO_TYPE, | |
| 30 | MHL_DCAP_LOG_DEV_MAP, | |
| 31 | MHL_DCAP_BANDWIDTH, | |
| 32 | MHL_DCAP_FEATURE_FLAG, | |
| 33 | MHL_DCAP_DEVICE_ID_H, | |
| 34 | MHL_DCAP_DEVICE_ID_L, | |
| 35 | MHL_DCAP_SCRATCHPAD_SIZE, | |
| 36 | MHL_DCAP_INT_STAT_SIZE, | |
| 37 | MHL_DCAP_RESERVED, | |
| 38 | MHL_DCAP_SIZE | |
| 39 | }; | |
| 40 | ||
| 41 | #define MHL_DCAP_CAT_SINK 0x01 | |
| 42 | #define MHL_DCAP_CAT_SOURCE 0x02 | |
| 43 | #define MHL_DCAP_CAT_POWER 0x10 | |
| 44 | #define MHL_DCAP_CAT_PLIM(x) ((x) << 5) | |
| 45 | ||
| 46 | #define MHL_DCAP_VID_LINK_RGB444 0x01 | |
| 47 | #define MHL_DCAP_VID_LINK_YCBCR444 0x02 | |
| 48 | #define MHL_DCAP_VID_LINK_YCBCR422 0x04 | |
| 49 | #define MHL_DCAP_VID_LINK_PPIXEL 0x08 | |
| 50 | #define MHL_DCAP_VID_LINK_ISLANDS 0x10 | |
| 51 | #define MHL_DCAP_VID_LINK_VGA 0x20 | |
| 52 | #define MHL_DCAP_VID_LINK_16BPP 0x40 | |
| 53 | ||
| 54 | #define MHL_DCAP_AUD_LINK_2CH 0x01 | |
| 55 | #define MHL_DCAP_AUD_LINK_8CH 0x02 | |
| 56 | ||
| 57 | #define MHL_DCAP_VT_GRAPHICS 0x00 | |
| 58 | #define MHL_DCAP_VT_PHOTO 0x02 | |
| 59 | #define MHL_DCAP_VT_CINEMA 0x04 | |
| 60 | #define MHL_DCAP_VT_GAMES 0x08 | |
| 61 | #define MHL_DCAP_SUPP_VT 0x80 | |
| 62 | ||
| 63 | #define MHL_DCAP_LD_DISPLAY 0x01 | |
| 64 | #define MHL_DCAP_LD_VIDEO 0x02 | |
| 65 | #define MHL_DCAP_LD_AUDIO 0x04 | |
| 66 | #define MHL_DCAP_LD_MEDIA 0x08 | |
| 67 | #define MHL_DCAP_LD_TUNER 0x10 | |
| 68 | #define MHL_DCAP_LD_RECORD 0x20 | |
| 69 | #define MHL_DCAP_LD_SPEAKER 0x40 | |
| 70 | #define MHL_DCAP_LD_GUI 0x80 | |
| 71 | #define MHL_DCAP_LD_ALL 0xFF | |
| 72 | ||
| 73 | #define MHL_DCAP_FEATURE_RCP_SUPPORT 0x01 | |
| 74 | #define MHL_DCAP_FEATURE_RAP_SUPPORT 0x02 | |
| 75 | #define MHL_DCAP_FEATURE_SP_SUPPORT 0x04 | |
| 76 | #define MHL_DCAP_FEATURE_UCP_SEND_SUPPOR 0x08 | |
| 77 | #define MHL_DCAP_FEATURE_UCP_RECV_SUPPORT 0x10 | |
| 78 | #define MHL_DCAP_FEATURE_RBP_SUPPORT 0x40 | |
| 79 | ||
| 80 | /* Extended Device Capabilities Registers */ | |
| 81 | enum { | |
| 82 | MHL_XDC_ECBUS_SPEEDS, | |
| 83 | MHL_XDC_TMDS_SPEEDS, | |
| 84 | MHL_XDC_ECBUS_ROLES, | |
| 85 | MHL_XDC_LOG_DEV_MAPX, | |
| 86 | MHL_XDC_SIZE | |
| 87 | }; | |
| 88 | ||
| 89 | #define MHL_XDC_ECBUS_S_075 0x01 | |
| 90 | #define MHL_XDC_ECBUS_S_8BIT 0x02 | |
| 91 | #define MHL_XDC_ECBUS_S_12BIT 0x04 | |
| 92 | #define MHL_XDC_ECBUS_D_150 0x10 | |
| 93 | #define MHL_XDC_ECBUS_D_8BIT 0x20 | |
| 94 | ||
| 95 | #define MHL_XDC_TMDS_000 0x00 | |
| 96 | #define MHL_XDC_TMDS_150 0x01 | |
| 97 | #define MHL_XDC_TMDS_300 0x02 | |
| 98 | #define MHL_XDC_TMDS_600 0x04 | |
| 99 | ||
| 100 | /* MHL_XDC_ECBUS_ROLES flags */ | |
| 101 | #define MHL_XDC_DEV_HOST 0x01 | |
| 102 | #define MHL_XDC_DEV_DEVICE 0x02 | |
| 103 | #define MHL_XDC_DEV_CHARGER 0x04 | |
| 104 | #define MHL_XDC_HID_HOST 0x08 | |
| 105 | #define MHL_XDC_HID_DEVICE 0x10 | |
| 106 | ||
| 107 | /* MHL_XDC_LOG_DEV_MAPX flags */ | |
| 108 | #define MHL_XDC_LD_PHONE 0x01 | |
| 109 | ||
| 110 | /* Device Status Registers */ | |
| 111 | enum { | |
| 112 | MHL_DST_CONNECTED_RDY, | |
| 113 | MHL_DST_LINK_MODE, | |
| 114 | MHL_DST_VERSION, | |
| 115 | MHL_DST_SIZE | |
| 116 | }; | |
| 117 | ||
| 118 | /* Offset of DEVSTAT registers */ | |
| 119 | #define MHL_DST_OFFSET 0x30 | |
| 120 | #define MHL_DST_REG(name) (MHL_DST_OFFSET + MHL_DST_##name) | |
| 121 | ||
| 122 | #define MHL_DST_CONN_DCAP_RDY 0x01 | |
| 123 | #define MHL_DST_CONN_XDEVCAPP_SUPP 0x02 | |
| 124 | #define MHL_DST_CONN_POW_STAT 0x04 | |
| 125 | #define MHL_DST_CONN_PLIM_STAT_MASK 0x38 | |
| 126 | ||
| 127 | #define MHL_DST_LM_CLK_MODE_MASK 0x07 | |
| 128 | #define MHL_DST_LM_CLK_MODE_PACKED_PIXEL 0x02 | |
| 129 | #define MHL_DST_LM_CLK_MODE_NORMAL 0x03 | |
| 130 | #define MHL_DST_LM_PATH_EN_MASK 0x08 | |
| 131 | #define MHL_DST_LM_PATH_ENABLED 0x08 | |
| 132 | #define MHL_DST_LM_PATH_DISABLED 0x00 | |
| 133 | #define MHL_DST_LM_MUTED_MASK 0x10 | |
| 134 | ||
| 135 | /* Extended Device Status Registers */ | |
| 136 | enum { | |
| 137 | MHL_XDS_CURR_ECBUS_MODE, | |
| 138 | MHL_XDS_AVLINK_MODE_STATUS, | |
| 139 | MHL_XDS_AVLINK_MODE_CONTROL, | |
| 140 | MHL_XDS_MULTI_SINK_STATUS, | |
| 141 | MHL_XDS_SIZE | |
| 142 | }; | |
| 143 | ||
| 144 | /* Offset of XDEVSTAT registers */ | |
| 145 | #define MHL_XDS_OFFSET 0x90 | |
| 146 | #define MHL_XDS_REG(name) (MHL_XDS_OFFSET + MHL_XDS_##name) | |
| 147 | ||
| 148 | /* MHL_XDS_REG_CURR_ECBUS_MODE flags */ | |
| 149 | #define MHL_XDS_SLOT_MODE_8BIT 0x00 | |
| 150 | #define MHL_XDS_SLOT_MODE_6BIT 0x01 | |
| 151 | #define MHL_XDS_ECBUS_S 0x04 | |
| 152 | #define MHL_XDS_ECBUS_D 0x08 | |
| 153 | ||
| 154 | #define MHL_XDS_LINK_CLOCK_75MHZ 0x00 | |
| 155 | #define MHL_XDS_LINK_CLOCK_150MHZ 0x10 | |
| 156 | #define MHL_XDS_LINK_CLOCK_300MHZ 0x20 | |
| 157 | #define MHL_XDS_LINK_CLOCK_600MHZ 0x30 | |
| 158 | ||
| 159 | #define MHL_XDS_LINK_STATUS_NO_SIGNAL 0x00 | |
| 160 | #define MHL_XDS_LINK_STATUS_CRU_LOCKED 0x01 | |
| 161 | #define MHL_XDS_LINK_STATUS_TMDS_NORMAL 0x02 | |
| 162 | #define MHL_XDS_LINK_STATUS_TMDS_RESERVED 0x03 | |
| 163 | ||
| 164 | #define MHL_XDS_LINK_RATE_1_5_GBPS 0x00 | |
| 165 | #define MHL_XDS_LINK_RATE_3_0_GBPS 0x01 | |
| 166 | #define MHL_XDS_LINK_RATE_6_0_GBPS 0x02 | |
| 167 | #define MHL_XDS_ATT_CAPABLE 0x08 | |
| 168 | ||
| 169 | #define MHL_XDS_SINK_STATUS_1_HPD_LOW 0x00 | |
| 170 | #define MHL_XDS_SINK_STATUS_1_HPD_HIGH 0x01 | |
| 171 | #define MHL_XDS_SINK_STATUS_2_HPD_LOW 0x00 | |
| 172 | #define MHL_XDS_SINK_STATUS_2_HPD_HIGH 0x04 | |
| 173 | #define MHL_XDS_SINK_STATUS_3_HPD_LOW 0x00 | |
| 174 | #define MHL_XDS_SINK_STATUS_3_HPD_HIGH 0x10 | |
| 175 | #define MHL_XDS_SINK_STATUS_4_HPD_LOW 0x00 | |
| 176 | #define MHL_XDS_SINK_STATUS_4_HPD_HIGH 0x40 | |
| 177 | ||
| 178 | /* Interrupt Registers */ | |
| 179 | enum { | |
| 180 | MHL_INT_RCHANGE, | |
| 181 | MHL_INT_DCHANGE, | |
| 182 | MHL_INT_SIZE | |
| 183 | }; | |
| 184 | ||
| 185 | /* Offset of DEVSTAT registers */ | |
| 186 | #define MHL_INT_OFFSET 0x20 | |
| 187 | #define MHL_INT_REG(name) (MHL_INT_OFFSET + MHL_INT_##name) | |
| 188 | ||
| 189 | #define MHL_INT_RC_DCAP_CHG 0x01 | |
| 190 | #define MHL_INT_RC_DSCR_CHG 0x02 | |
| 191 | #define MHL_INT_RC_REQ_WRT 0x04 | |
| 192 | #define MHL_INT_RC_GRT_WRT 0x08 | |
| 193 | #define MHL_INT_RC_3D_REQ 0x10 | |
| 194 | #define MHL_INT_RC_FEAT_REQ 0x20 | |
| 195 | #define MHL_INT_RC_FEAT_COMPLETE 0x40 | |
| 196 | ||
| 197 | #define MHL_INT_DC_EDID_CHG 0x02 | |
| 198 | ||
| 199 | enum { | |
| 200 | MHL_ACK = 0x33, /* Command or Data byte acknowledge */ | |
| 201 | MHL_NACK = 0x34, /* Command or Data byte not acknowledge */ | |
| 202 | MHL_ABORT = 0x35, /* Transaction abort */ | |
| 203 | MHL_WRITE_STAT = 0xe0, /* Write one status register */ | |
| 204 | MHL_SET_INT = 0x60, /* Write one interrupt register */ | |
| 205 | MHL_READ_DEVCAP_REG = 0x61, /* Read one register */ | |
| 206 | MHL_GET_STATE = 0x62, /* Read CBUS revision level from follower */ | |
| 207 | MHL_GET_VENDOR_ID = 0x63, /* Read vendor ID value from follower */ | |
| 208 | MHL_SET_HPD = 0x64, /* Set Hot Plug Detect in follower */ | |
| 209 | MHL_CLR_HPD = 0x65, /* Clear Hot Plug Detect in follower */ | |
| 210 | MHL_SET_CAP_ID = 0x66, /* Set Capture ID for downstream device */ | |
| 211 | MHL_GET_CAP_ID = 0x67, /* Get Capture ID from downstream device */ | |
| 212 | MHL_MSC_MSG = 0x68, /* VS command to send RCP sub-commands */ | |
| 213 | MHL_GET_SC1_ERRORCODE = 0x69, /* Get Vendor-Specific error code */ | |
| 214 | MHL_GET_DDC_ERRORCODE = 0x6A, /* Get DDC channel command error code */ | |
| 215 | MHL_GET_MSC_ERRORCODE = 0x6B, /* Get MSC command error code */ | |
| 216 | MHL_WRITE_BURST = 0x6C, /* Write 1-16 bytes to responder's scratchpad */ | |
| 217 | MHL_GET_SC3_ERRORCODE = 0x6D, /* Get channel 3 command error code */ | |
| 218 | MHL_WRITE_XSTAT = 0x70, /* Write one extended status register */ | |
| 219 | MHL_READ_XDEVCAP_REG = 0x71, /* Read one extended devcap register */ | |
| 220 | /* let the rest of these float, they are software specific */ | |
| 221 | MHL_READ_EDID_BLOCK, | |
| 222 | MHL_SEND_3D_REQ_OR_FEAT_REQ, | |
| 223 | MHL_READ_DEVCAP, | |
| 224 | MHL_READ_XDEVCAP | |
| 225 | }; | |
| 226 | ||
| 227 | /* MSC message types */ | |
| 228 | enum { | |
| 229 | MHL_MSC_MSG_RCP = 0x10, /* RCP sub-command */ | |
| 230 | MHL_MSC_MSG_RCPK = 0x11, /* RCP Acknowledge sub-command */ | |
| 231 | MHL_MSC_MSG_RCPE = 0x12, /* RCP Error sub-command */ | |
| 232 | MHL_MSC_MSG_RAP = 0x20, /* Mode Change Warning sub-command */ | |
| 233 | MHL_MSC_MSG_RAPK = 0x21, /* MCW Acknowledge sub-command */ | |
| 234 | MHL_MSC_MSG_RBP = 0x22, /* Remote Button Protocol sub-command */ | |
| 235 | MHL_MSC_MSG_RBPK = 0x23, /* RBP Acknowledge sub-command */ | |
| 236 | MHL_MSC_MSG_RBPE = 0x24, /* RBP Error sub-command */ | |
| 237 | MHL_MSC_MSG_UCP = 0x30, /* UCP sub-command */ | |
| 238 | MHL_MSC_MSG_UCPK = 0x31, /* UCP Acknowledge sub-command */ | |
| 239 | MHL_MSC_MSG_UCPE = 0x32, /* UCP Error sub-command */ | |
| 240 | MHL_MSC_MSG_RUSB = 0x40, /* Request USB host role */ | |
| 241 | MHL_MSC_MSG_RUSBK = 0x41, /* Acknowledge request for USB host role */ | |
| 242 | MHL_MSC_MSG_RHID = 0x42, /* Request HID host role */ | |
| 243 | MHL_MSC_MSG_RHIDK = 0x43, /* Acknowledge request for HID host role */ | |
| 244 | MHL_MSC_MSG_ATT = 0x50, /* Request attention sub-command */ | |
| 245 | MHL_MSC_MSG_ATTK = 0x51, /* ATT Acknowledge sub-command */ | |
| 246 | MHL_MSC_MSG_BIST_TRIGGER = 0x60, | |
| 247 | MHL_MSC_MSG_BIST_REQUEST_STAT = 0x61, | |
| 248 | MHL_MSC_MSG_BIST_READY = 0x62, | |
| 249 | MHL_MSC_MSG_BIST_STOP = 0x63, | |
| 250 | }; | |
| 251 | ||
| 252 | /* RAP action codes */ | |
| 253 | #define MHL_RAP_POLL 0x00 /* Just do an ack */ | |
| 254 | #define MHL_RAP_CONTENT_ON 0x10 /* Turn content stream ON */ | |
| 255 | #define MHL_RAP_CONTENT_OFF 0x11 /* Turn content stream OFF */ | |
| 256 | #define MHL_RAP_CBUS_MODE_DOWN 0x20 | |
| 257 | #define MHL_RAP_CBUS_MODE_UP 0x21 | |
| 258 | ||
| 259 | /* RAPK status codes */ | |
| 260 | #define MHL_RAPK_NO_ERR 0x00 /* RAP action recognized & supported */ | |
| 261 | #define MHL_RAPK_UNRECOGNIZED 0x01 /* Unknown RAP action code received */ | |
| 262 | #define MHL_RAPK_UNSUPPORTED 0x02 /* Rcvd RAP action code not supported */ | |
| 263 | #define MHL_RAPK_BUSY 0x03 /* Responder too busy to respond */ | |
| 264 | ||
| 265 | /* | |
| 266 | * Error status codes for RCPE messages | |
| 267 | */ | |
| 268 | /* No error. (Not allowed in RCPE messages) */ | |
| 269 | #define MHL_RCPE_STATUS_NO_ERROR 0x00 | |
| 270 | /* Unsupported/unrecognized key code */ | |
| 271 | #define MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01 | |
| 272 | /* Responder busy. Initiator may retry message */ | |
| 273 | #define MHL_RCPE_STATUS_BUSY 0x02 | |
| 274 | ||
| 275 | /* | |
| 276 | * Error status codes for RBPE messages | |
| 277 | */ | |
| 278 | /* No error. (Not allowed in RBPE messages) */ | |
| 279 | #define MHL_RBPE_STATUS_NO_ERROR 0x00 | |
| 280 | /* Unsupported/unrecognized button code */ | |
| 281 | #define MHL_RBPE_STATUS_INEFFECTIVE_BUTTON_CODE 0x01 | |
| 282 | /* Responder busy. Initiator may retry message */ | |
| 283 | #define MHL_RBPE_STATUS_BUSY 0x02 | |
| 284 | ||
| 285 | /* | |
| 286 | * Error status codes for UCPE messages | |
| 287 | */ | |
| 288 | /* No error. (Not allowed in UCPE messages) */ | |
| 289 | #define MHL_UCPE_STATUS_NO_ERROR 0x00 | |
| 290 | /* Unsupported/unrecognized key code */ | |
| 291 | #define MHL_UCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01 | |
| 292 | ||
| 981b3f37 AH |
293 | enum mhl_burst_id { |
| 294 | MHL_BURST_ID_3D_VIC = 0x10, | |
| 295 | MHL_BURST_ID_3D_DTD = 0x11, | |
| 296 | MHL_BURST_ID_HEV_VIC = 0x20, | |
| 297 | MHL_BURST_ID_HEV_DTDA = 0x21, | |
| 298 | MHL_BURST_ID_HEV_DTDB = 0x22, | |
| 299 | MHL_BURST_ID_VC_ASSIGN = 0x38, | |
| 300 | MHL_BURST_ID_VC_CONFIRM = 0x39, | |
| 301 | MHL_BURST_ID_AUD_DELAY = 0x40, | |
| 302 | MHL_BURST_ID_ADT_BURSTID = 0x41, | |
| 303 | MHL_BURST_ID_BIST_SETUP = 0x51, | |
| 304 | MHL_BURST_ID_BIST_RETURN_STAT = 0x52, | |
| 305 | MHL_BURST_ID_EMSC_SUPPORT = 0x61, | |
| 306 | MHL_BURST_ID_HID_PAYLOAD = 0x62, | |
| 307 | MHL_BURST_ID_BLK_RCV_BUFFER_INFO = 0x63, | |
| 308 | MHL_BURST_ID_BITS_PER_PIXEL_FMT = 0x64, | |
| 309 | }; | |
| 310 | ||
| 311 | struct mhl_burst_blk_rcv_buffer_info { | |
| 312 | __be16 id; | |
| 313 | __le16 size; | |
| 314 | } __packed; | |
| 315 | ||
| 316 | struct mhl3_burst_header { | |
| 317 | __be16 id; | |
| 318 | u8 checksum; | |
| 319 | u8 total_entries; | |
| 320 | u8 sequence_index; | |
| 321 | } __packed; | |
| 322 | ||
| 323 | struct mhl_burst_bits_per_pixel_fmt { | |
| 324 | struct mhl3_burst_header hdr; | |
| 325 | u8 num_entries; | |
| 326 | struct { | |
| 327 | u8 stream_id; | |
| 328 | u8 pixel_format; | |
| 329 | } __packed desc[0]; | |
| 330 | } __packed; | |
| 331 | ||
| 332 | struct mhl_burst_emsc_support { | |
| 333 | struct mhl3_burst_header hdr; | |
| 334 | u8 num_entries; | |
| 335 | __be16 burst_id[0]; | |
| 336 | } __packed; | |
| 337 | ||
| 338 | struct mhl_burst_audio_descr { | |
| 339 | struct mhl3_burst_header hdr; | |
| 340 | u8 flags; | |
| 341 | u8 short_desc[9]; | |
| 342 | } __packed; | |
| 343 | ||
| be1cd6fe AH |
344 | /* |
| 345 | * MHL3 infoframe related definitions | |
| 346 | */ | |
| 347 | ||
| 348 | #define MHL3_IEEE_OUI 0x7ca61d | |
| 349 | #define MHL3_INFOFRAME_SIZE 15 | |
| 350 | ||
| 351 | enum mhl3_video_format { | |
| 352 | MHL3_VIDEO_FORMAT_NONE, | |
| 353 | MHL3_VIDEO_FORMAT_3D, | |
| 354 | MHL3_VIDEO_FORMAT_MULTI_VIEW, | |
| 355 | MHL3_VIDEO_FORMAT_DUAL_3D | |
| 356 | }; | |
| 357 | ||
| 358 | enum mhl3_3d_format_type { | |
| 359 | MHL3_3D_FORMAT_TYPE_FS, /* frame sequential */ | |
| 360 | MHL3_3D_FORMAT_TYPE_TB, /* top-bottom */ | |
| 361 | MHL3_3D_FORMAT_TYPE_LR, /* left-right */ | |
| 362 | MHL3_3D_FORMAT_TYPE_FS_TB, /* frame sequential, top-bottom */ | |
| 363 | MHL3_3D_FORMAT_TYPE_FS_LR, /* frame sequential, left-right */ | |
| 364 | MHL3_3D_FORMAT_TYPE_TB_LR /* top-bottom, left-right */ | |
| 365 | }; | |
| 366 | ||
| 367 | struct mhl3_infoframe { | |
| 368 | unsigned char version; | |
| 369 | enum mhl3_video_format video_format; | |
| 370 | enum mhl3_3d_format_type format_type; | |
| 371 | bool sep_audio; | |
| 372 | int hev_format; | |
| 373 | int av_delay; | |
| 374 | }; | |
| 375 | ||
| 00c635e5 | 376 | #endif /* __MHL_H__ */ |