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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
ab2c0672 DA |
23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ | |
a4fc5ed6 | 25 | |
9f0e7ff4 JB |
26 | #include <linux/types.h> |
27 | #include <linux/i2c.h> | |
28 | ||
a4fc5ed6 KP |
29 | /* From the VESA DisplayPort spec */ |
30 | ||
31 | #define AUX_NATIVE_WRITE 0x8 | |
32 | #define AUX_NATIVE_READ 0x9 | |
33 | #define AUX_I2C_WRITE 0x0 | |
34 | #define AUX_I2C_READ 0x1 | |
35 | #define AUX_I2C_STATUS 0x2 | |
36 | #define AUX_I2C_MOT 0x4 | |
37 | ||
38 | #define AUX_NATIVE_REPLY_ACK (0x0 << 4) | |
39 | #define AUX_NATIVE_REPLY_NACK (0x1 << 4) | |
40 | #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) | |
41 | #define AUX_NATIVE_REPLY_MASK (0x3 << 4) | |
42 | ||
43 | #define AUX_I2C_REPLY_ACK (0x0 << 6) | |
44 | #define AUX_I2C_REPLY_NACK (0x1 << 6) | |
45 | #define AUX_I2C_REPLY_DEFER (0x2 << 6) | |
46 | #define AUX_I2C_REPLY_MASK (0x3 << 6) | |
47 | ||
48 | /* AUX CH addresses */ | |
5801ead6 AD |
49 | /* DPCD */ |
50 | #define DP_DPCD_REV 0x000 | |
746c1aa4 | 51 | |
5801ead6 AD |
52 | #define DP_MAX_LINK_RATE 0x001 |
53 | ||
54 | #define DP_MAX_LANE_COUNT 0x002 | |
55 | # define DP_MAX_LANE_COUNT_MASK 0x1f | |
428c4b51 | 56 | # define DP_TPS3_SUPPORTED (1 << 6) |
5801ead6 AD |
57 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
58 | ||
59 | #define DP_MAX_DOWNSPREAD 0x003 | |
60 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) | |
61 | ||
62 | #define DP_NORP 0x004 | |
63 | ||
64 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 | |
65 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) | |
66 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 | |
67 | /* 00b = DisplayPort */ | |
68 | /* 01b = Analog */ | |
69 | /* 10b = TMDS or HDMI */ | |
70 | /* 11b = Other */ | |
71 | # define DP_FORMAT_CONVERSION (1 << 3) | |
e89861df | 72 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) |
5801ead6 AD |
73 | |
74 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 | |
75 | ||
de44d971 | 76 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
e89861df AJ |
77 | # define DP_PORT_COUNT_MASK 0x0f |
78 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) | |
79 | # define DP_OUI_SUPPORT (1 << 7) | |
80 | ||
81 | #define DP_I2C_SPEED_CAP 0x00c | |
82 | # define DP_I2C_SPEED_1K 0x01 | |
83 | # define DP_I2C_SPEED_5K 0x02 | |
84 | # define DP_I2C_SPEED_10K 0x04 | |
85 | # define DP_I2C_SPEED_100K 0x08 | |
86 | # define DP_I2C_SPEED_400K 0x10 | |
87 | # define DP_I2C_SPEED_1M 0x20 | |
de44d971 | 88 | |
00dfb8df | 89 | #define DP_EDP_CONFIGURATION_CAP 0x00d |
428c4b51 AD |
90 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
91 | ||
e89861df AJ |
92 | /* Multiple stream transport */ |
93 | #define DP_MSTM_CAP 0x021 | |
94 | # define DP_MST_CAP (1 << 0) | |
95 | ||
b73fe58c BW |
96 | #define DP_PSR_SUPPORT 0x070 |
97 | # define DP_PSR_IS_SUPPORTED 1 | |
98 | #define DP_PSR_CAPS 0x071 | |
99 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 | |
100 | # define DP_PSR_SETUP_TIME_330 (0 << 1) | |
101 | # define DP_PSR_SETUP_TIME_275 (1 << 1) | |
102 | # define DP_PSR_SETUP_TIME_220 (2 << 1) | |
103 | # define DP_PSR_SETUP_TIME_165 (3 << 1) | |
104 | # define DP_PSR_SETUP_TIME_110 (4 << 1) | |
105 | # define DP_PSR_SETUP_TIME_55 (5 << 1) | |
106 | # define DP_PSR_SETUP_TIME_0 (6 << 1) | |
107 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) | |
108 | # define DP_PSR_SETUP_TIME_SHIFT 1 | |
109 | ||
e89861df AJ |
110 | /* |
111 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts | |
112 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, | |
113 | * each port's descriptor is one byte wide. If it was set, each port's is | |
114 | * four bytes wide, starting with the one byte from the base info. As of | |
115 | * DP interop v1.1a only VGA defines additional detail. | |
116 | */ | |
117 | ||
118 | /* offset 0 */ | |
119 | #define DP_DOWNSTREAM_PORT_0 0x80 | |
120 | # define DP_DS_PORT_TYPE_MASK (7 << 0) | |
121 | # define DP_DS_PORT_TYPE_DP 0 | |
122 | # define DP_DS_PORT_TYPE_VGA 1 | |
123 | # define DP_DS_PORT_TYPE_DVI 2 | |
124 | # define DP_DS_PORT_TYPE_HDMI 3 | |
125 | # define DP_DS_PORT_TYPE_NON_EDID 4 | |
126 | # define DP_DS_PORT_HPD (1 << 3) | |
127 | /* offset 1 for VGA is maximum megapixels per second / 8 */ | |
128 | /* offset 2 */ | |
129 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) | |
130 | # define DP_DS_VGA_8BPC 0 | |
131 | # define DP_DS_VGA_10BPC 1 | |
132 | # define DP_DS_VGA_12BPC 2 | |
133 | # define DP_DS_VGA_16BPC 3 | |
134 | ||
5801ead6 AD |
135 | /* link configuration */ |
136 | #define DP_LINK_BW_SET 0x100 | |
a4fc5ed6 KP |
137 | # define DP_LINK_BW_1_62 0x06 |
138 | # define DP_LINK_BW_2_7 0x0a | |
428c4b51 | 139 | # define DP_LINK_BW_5_4 0x14 |
a4fc5ed6 | 140 | |
5801ead6 | 141 | #define DP_LANE_COUNT_SET 0x101 |
a4fc5ed6 KP |
142 | # define DP_LANE_COUNT_MASK 0x0f |
143 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) | |
144 | ||
5801ead6 | 145 | #define DP_TRAINING_PATTERN_SET 0x102 |
a4fc5ed6 KP |
146 | # define DP_TRAINING_PATTERN_DISABLE 0 |
147 | # define DP_TRAINING_PATTERN_1 1 | |
148 | # define DP_TRAINING_PATTERN_2 2 | |
428c4b51 | 149 | # define DP_TRAINING_PATTERN_3 3 |
a4fc5ed6 KP |
150 | # define DP_TRAINING_PATTERN_MASK 0x3 |
151 | ||
152 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) | |
153 | # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) | |
154 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) | |
155 | # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) | |
156 | # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) | |
157 | ||
158 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) | |
159 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) | |
160 | ||
161 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) | |
162 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) | |
163 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) | |
164 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) | |
165 | ||
166 | #define DP_TRAINING_LANE0_SET 0x103 | |
167 | #define DP_TRAINING_LANE1_SET 0x104 | |
168 | #define DP_TRAINING_LANE2_SET 0x105 | |
169 | #define DP_TRAINING_LANE3_SET 0x106 | |
170 | ||
171 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 | |
172 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 | |
173 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) | |
174 | # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) | |
175 | # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) | |
176 | # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) | |
177 | # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) | |
178 | ||
179 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) | |
180 | # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) | |
181 | # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) | |
182 | # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) | |
183 | # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) | |
184 | ||
185 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 | |
186 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) | |
187 | ||
188 | #define DP_DOWNSPREAD_CTRL 0x107 | |
189 | # define DP_SPREAD_AMP_0_5 (1 << 4) | |
e89861df | 190 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) |
a4fc5ed6 KP |
191 | |
192 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 | |
193 | # define DP_SET_ANSI_8B10B (1 << 0) | |
194 | ||
e89861df AJ |
195 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 |
196 | /* bitmask as for DP_I2C_SPEED_CAP */ | |
197 | ||
198 | #define DP_EDP_CONFIGURATION_SET 0x10a | |
199 | ||
200 | #define DP_MSTM_CTRL 0x111 | |
201 | # define DP_MST_EN (1 << 0) | |
202 | # define DP_UP_REQ_EN (1 << 1) | |
203 | # define DP_UPSTREAM_IS_SRC (1 << 2) | |
204 | ||
b73fe58c BW |
205 | #define DP_PSR_EN_CFG 0x170 |
206 | # define DP_PSR_ENABLE (1 << 0) | |
207 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) | |
208 | # define DP_PSR_CRC_VERIFICATION (1 << 2) | |
209 | # define DP_PSR_FRAME_CAPTURE (1 << 3) | |
210 | ||
e89861df AJ |
211 | #define DP_SINK_COUNT 0x200 |
212 | # define DP_SINK_COUNT_MASK (31 << 0) | |
213 | # define DP_SINK_CP_READY (1 << 6) | |
214 | ||
a60f0e38 JB |
215 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
216 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) | |
217 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) | |
218 | # define DP_CP_IRQ (1 << 2) | |
219 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) | |
220 | ||
a4fc5ed6 KP |
221 | #define DP_LANE0_1_STATUS 0x202 |
222 | #define DP_LANE2_3_STATUS 0x203 | |
a4fc5ed6 KP |
223 | # define DP_LANE_CR_DONE (1 << 0) |
224 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) | |
225 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) | |
226 | ||
5801ead6 AD |
227 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
228 | DP_LANE_CHANNEL_EQ_DONE | \ | |
229 | DP_LANE_SYMBOL_LOCKED) | |
230 | ||
a4fc5ed6 KP |
231 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
232 | ||
233 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) | |
234 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) | |
235 | #define DP_LINK_STATUS_UPDATED (1 << 7) | |
236 | ||
237 | #define DP_SINK_STATUS 0x205 | |
238 | ||
239 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) | |
240 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) | |
241 | ||
242 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 | |
243 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 | |
5801ead6 AD |
244 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
245 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 | |
246 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c | |
247 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 | |
248 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 | |
249 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 | |
250 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 | |
251 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 | |
a4fc5ed6 | 252 | |
a60f0e38 JB |
253 | #define DP_TEST_REQUEST 0x218 |
254 | # define DP_TEST_LINK_TRAINING (1 << 0) | |
255 | # define DP_TEST_LINK_PATTERN (1 << 1) | |
256 | # define DP_TEST_LINK_EDID_READ (1 << 2) | |
257 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ | |
258 | ||
259 | #define DP_TEST_LINK_RATE 0x219 | |
260 | # define DP_LINK_RATE_162 (0x6) | |
261 | # define DP_LINK_RATE_27 (0xa) | |
262 | ||
263 | #define DP_TEST_LANE_COUNT 0x220 | |
264 | ||
265 | #define DP_TEST_PATTERN 0x221 | |
266 | ||
267 | #define DP_TEST_RESPONSE 0x260 | |
268 | # define DP_TEST_ACK (1 << 0) | |
269 | # define DP_TEST_NAK (1 << 1) | |
270 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) | |
271 | ||
86c3c3be AJ |
272 | #define DP_SOURCE_OUI 0x300 |
273 | #define DP_SINK_OUI 0x400 | |
274 | #define DP_BRANCH_OUI 0x500 | |
275 | ||
1a66c95a | 276 | #define DP_SET_POWER 0x600 |
5801ead6 AD |
277 | # define DP_SET_POWER_D0 0x1 |
278 | # define DP_SET_POWER_D3 0x2 | |
1a66c95a | 279 | |
b73fe58c BW |
280 | #define DP_PSR_ERROR_STATUS 0x2006 |
281 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) | |
282 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) | |
283 | ||
284 | #define DP_PSR_ESI 0x2007 | |
285 | # define DP_PSR_CAPS_CHANGE (1 << 0) | |
286 | ||
287 | #define DP_PSR_STATUS 0x2008 | |
288 | # define DP_PSR_SINK_INACTIVE 0 | |
289 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 | |
290 | # define DP_PSR_SINK_ACTIVE_RFB 2 | |
291 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 | |
292 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 | |
293 | # define DP_PSR_SINK_INTERNAL_ERROR 7 | |
294 | # define DP_PSR_SINK_STATE_MASK 0x07 | |
295 | ||
ab2c0672 DA |
296 | #define MODE_I2C_START 1 |
297 | #define MODE_I2C_WRITE 2 | |
298 | #define MODE_I2C_READ 4 | |
299 | #define MODE_I2C_STOP 8 | |
300 | ||
a4fc5ed6 KP |
301 | struct i2c_algo_dp_aux_data { |
302 | bool running; | |
303 | u16 address; | |
304 | int (*aux_ch) (struct i2c_adapter *adapter, | |
ab2c0672 DA |
305 | int mode, uint8_t write_byte, |
306 | uint8_t *read_byte); | |
a4fc5ed6 KP |
307 | }; |
308 | ||
309 | int | |
310 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); | |
311 | ||
ab2c0672 | 312 | #endif /* _DRM_DP_HELPER_H_ */ |