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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
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23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
a4fc5ed6 25
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26#include <linux/types.h>
27#include <linux/i2c.h>
1a644cd4 28#include <linux/delay.h>
9f0e7ff4 29
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30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
3c8a0922 40 * MST: Multistream Transport - part of DP 1.2a
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41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
a4fc5ed6 44
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45#define DP_AUX_I2C_WRITE 0x0
46#define DP_AUX_I2C_READ 0x1
47#define DP_AUX_I2C_STATUS 0x2
48#define DP_AUX_I2C_MOT 0x4
49#define DP_AUX_NATIVE_WRITE 0x8
50#define DP_AUX_NATIVE_READ 0x9
a4fc5ed6 51
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52#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
53#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
54#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
55#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
a4fc5ed6 56
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57#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
58#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
59#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
60#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
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61
62/* AUX CH addresses */
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63/* DPCD */
64#define DP_DPCD_REV 0x000
746c1aa4 65
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66#define DP_MAX_LINK_RATE 0x001
67
68#define DP_MAX_LANE_COUNT 0x002
69# define DP_MAX_LANE_COUNT_MASK 0x1f
a477f4fc 70# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
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71# define DP_ENHANCED_FRAME_CAP (1 << 7)
72
73#define DP_MAX_DOWNSPREAD 0x003
74# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
75
76#define DP_NORP 0x004
77
78#define DP_DOWNSTREAMPORT_PRESENT 0x005
79# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
80# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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81# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
82# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
83# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
84# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
5801ead6 85# define DP_FORMAT_CONVERSION (1 << 3)
a477f4fc 86# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
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87
88#define DP_MAIN_LINK_CHANNEL_CODING 0x006
89
de44d971 90#define DP_DOWN_STREAM_PORT_COUNT 0x007
e89861df 91# define DP_PORT_COUNT_MASK 0x0f
a477f4fc 92# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
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93# define DP_OUI_SUPPORT (1 << 7)
94
a477f4fc 95#define DP_I2C_SPEED_CAP 0x00c /* DPI */
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96# define DP_I2C_SPEED_1K 0x01
97# define DP_I2C_SPEED_5K 0x02
98# define DP_I2C_SPEED_10K 0x04
99# define DP_I2C_SPEED_100K 0x08
100# define DP_I2C_SPEED_400K 0x10
101# define DP_I2C_SPEED_1M 0x20
de44d971 102
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103#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
104#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
428c4b51 105
e89861df 106/* Multiple stream transport */
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107#define DP_FAUX_CAP 0x020 /* 1.2 */
108# define DP_FAUX_CAP_1 (1 << 0)
109
a477f4fc 110#define DP_MSTM_CAP 0x021 /* 1.2 */
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111# define DP_MST_CAP (1 << 0)
112
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113#define DP_GUID 0x030 /* 1.2 */
114
a477f4fc 115#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
b73fe58c 116# define DP_PSR_IS_SUPPORTED 1
a477f4fc 117#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
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118# define DP_PSR_NO_TRAIN_ON_EXIT 1
119# define DP_PSR_SETUP_TIME_330 (0 << 1)
120# define DP_PSR_SETUP_TIME_275 (1 << 1)
121# define DP_PSR_SETUP_TIME_220 (2 << 1)
122# define DP_PSR_SETUP_TIME_165 (3 << 1)
123# define DP_PSR_SETUP_TIME_110 (4 << 1)
124# define DP_PSR_SETUP_TIME_55 (5 << 1)
125# define DP_PSR_SETUP_TIME_0 (6 << 1)
126# define DP_PSR_SETUP_TIME_MASK (7 << 1)
127# define DP_PSR_SETUP_TIME_SHIFT 1
128
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129/*
130 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
131 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
132 * each port's descriptor is one byte wide. If it was set, each port's is
133 * four bytes wide, starting with the one byte from the base info. As of
134 * DP interop v1.1a only VGA defines additional detail.
135 */
136
137/* offset 0 */
138#define DP_DOWNSTREAM_PORT_0 0x80
139# define DP_DS_PORT_TYPE_MASK (7 << 0)
140# define DP_DS_PORT_TYPE_DP 0
141# define DP_DS_PORT_TYPE_VGA 1
142# define DP_DS_PORT_TYPE_DVI 2
143# define DP_DS_PORT_TYPE_HDMI 3
144# define DP_DS_PORT_TYPE_NON_EDID 4
145# define DP_DS_PORT_HPD (1 << 3)
146/* offset 1 for VGA is maximum megapixels per second / 8 */
147/* offset 2 */
148# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
149# define DP_DS_VGA_8BPC 0
150# define DP_DS_VGA_10BPC 1
151# define DP_DS_VGA_12BPC 2
152# define DP_DS_VGA_16BPC 3
153
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154/* link configuration */
155#define DP_LINK_BW_SET 0x100
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156# define DP_LINK_BW_1_62 0x06
157# define DP_LINK_BW_2_7 0x0a
a477f4fc 158# define DP_LINK_BW_5_4 0x14 /* 1.2 */
a4fc5ed6 159
5801ead6 160#define DP_LANE_COUNT_SET 0x101
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161# define DP_LANE_COUNT_MASK 0x0f
162# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
163
5801ead6 164#define DP_TRAINING_PATTERN_SET 0x102
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165# define DP_TRAINING_PATTERN_DISABLE 0
166# define DP_TRAINING_PATTERN_1 1
167# define DP_TRAINING_PATTERN_2 2
a477f4fc 168# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
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169# define DP_TRAINING_PATTERN_MASK 0x3
170
171# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
172# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
173# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
174# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
175# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
176
177# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
178# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
179
180# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
181# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
182# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
183# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
184
185#define DP_TRAINING_LANE0_SET 0x103
186#define DP_TRAINING_LANE1_SET 0x104
187#define DP_TRAINING_LANE2_SET 0x105
188#define DP_TRAINING_LANE3_SET 0x106
189
190# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
191# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
192# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
193# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
194# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
195# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
196# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
197
198# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
199# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
200# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
201# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
202# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
203
204# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
205# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
206
207#define DP_DOWNSPREAD_CTRL 0x107
208# define DP_SPREAD_AMP_0_5 (1 << 4)
a477f4fc 209# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
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210
211#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
212# define DP_SET_ANSI_8B10B (1 << 0)
213
a477f4fc 214#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
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215/* bitmask as for DP_I2C_SPEED_CAP */
216
a477f4fc 217#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
e89861df 218
a477f4fc 219#define DP_MSTM_CTRL 0x111 /* 1.2 */
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220# define DP_MST_EN (1 << 0)
221# define DP_UP_REQ_EN (1 << 1)
222# define DP_UPSTREAM_IS_SRC (1 << 2)
223
a477f4fc 224#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
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225# define DP_PSR_ENABLE (1 << 0)
226# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
227# define DP_PSR_CRC_VERIFICATION (1 << 2)
228# define DP_PSR_FRAME_CAPTURE (1 << 3)
229
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230#define DP_ADAPTER_CTRL 0x1a0
231# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
232
233#define DP_BRANCH_DEVICE_CTRL 0x1a1
234# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
235
236#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
237#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
238#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
239
e89861df 240#define DP_SINK_COUNT 0x200
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241/* prior to 1.2 bit 7 was reserved mbz */
242# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
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243# define DP_SINK_CP_READY (1 << 6)
244
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245#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
246# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
247# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
248# define DP_CP_IRQ (1 << 2)
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249# define DP_MCCS_IRQ (1 << 3)
250# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
251# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
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252# define DP_SINK_SPECIFIC_IRQ (1 << 6)
253
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254#define DP_LANE0_1_STATUS 0x202
255#define DP_LANE2_3_STATUS 0x203
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256# define DP_LANE_CR_DONE (1 << 0)
257# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
258# define DP_LANE_SYMBOL_LOCKED (1 << 2)
259
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260#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
261 DP_LANE_CHANNEL_EQ_DONE | \
262 DP_LANE_SYMBOL_LOCKED)
263
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264#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
265
266#define DP_INTERLANE_ALIGN_DONE (1 << 0)
267#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
268#define DP_LINK_STATUS_UPDATED (1 << 7)
269
270#define DP_SINK_STATUS 0x205
271
272#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
273#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
274
275#define DP_ADJUST_REQUEST_LANE0_1 0x206
276#define DP_ADJUST_REQUEST_LANE2_3 0x207
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277# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
278# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
279# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
280# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
281# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
282# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
283# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
284# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
a4fc5ed6 285
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286#define DP_TEST_REQUEST 0x218
287# define DP_TEST_LINK_TRAINING (1 << 0)
fe3c703c 288# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
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289# define DP_TEST_LINK_EDID_READ (1 << 2)
290# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
fe3c703c 291# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
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292
293#define DP_TEST_LINK_RATE 0x219
294# define DP_LINK_RATE_162 (0x6)
295# define DP_LINK_RATE_27 (0xa)
296
297#define DP_TEST_LANE_COUNT 0x220
298
299#define DP_TEST_PATTERN 0x221
300
a25eebb0
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301#define DP_TEST_CRC_R_CR 0x240
302#define DP_TEST_CRC_G_Y 0x242
303#define DP_TEST_CRC_B_CB 0x244
304
305#define DP_TEST_SINK_MISC 0x246
306#define DP_TEST_CRC_SUPPORTED (1 << 5)
307
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308#define DP_TEST_RESPONSE 0x260
309# define DP_TEST_ACK (1 << 0)
310# define DP_TEST_NAK (1 << 1)
311# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
312
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313#define DP_TEST_SINK 0x270
314#define DP_TEST_SINK_START (1 << 0)
315
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316#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
317# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
318# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
319
320#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
321/* up to ID_SLOT_63 at 0x2ff */
322
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323#define DP_SOURCE_OUI 0x300
324#define DP_SINK_OUI 0x400
325#define DP_BRANCH_OUI 0x500
326
1a66c95a 327#define DP_SET_POWER 0x600
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328# define DP_SET_POWER_D0 0x1
329# define DP_SET_POWER_D3 0x2
516c0f7c 330# define DP_SET_POWER_MASK 0x3
1a66c95a 331
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332#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
333#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
334#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
335#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
336
337#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
338/* 0-5 sink count */
339# define DP_SINK_COUNT_CP_READY (1 << 6)
340
341#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
342
343#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
344
345#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
346
a477f4fc 347#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
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348# define DP_PSR_LINK_CRC_ERROR (1 << 0)
349# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
350
a477f4fc 351#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
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352# define DP_PSR_CAPS_CHANGE (1 << 0)
353
a477f4fc 354#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
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355# define DP_PSR_SINK_INACTIVE 0
356# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
357# define DP_PSR_SINK_ACTIVE_RFB 2
358# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
359# define DP_PSR_SINK_ACTIVE_RESYNC 4
360# define DP_PSR_SINK_INTERNAL_ERROR 7
361# define DP_PSR_SINK_STATE_MASK 0x07
362
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DA
363/* DP 1.2 Sideband message defines */
364/* peer device type - DP 1.2a Table 2-92 */
365#define DP_PEER_DEVICE_NONE 0x0
366#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
367#define DP_PEER_DEVICE_MST_BRANCHING 0x2
368#define DP_PEER_DEVICE_SST_SINK 0x3
369#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
370
371/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
372#define DP_LINK_ADDRESS 0x01
373#define DP_CONNECTION_STATUS_NOTIFY 0x02
374#define DP_ENUM_PATH_RESOURCES 0x10
375#define DP_ALLOCATE_PAYLOAD 0x11
376#define DP_QUERY_PAYLOAD 0x12
377#define DP_RESOURCE_STATUS_NOTIFY 0x13
378#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
379#define DP_REMOTE_DPCD_READ 0x20
380#define DP_REMOTE_DPCD_WRITE 0x21
381#define DP_REMOTE_I2C_READ 0x22
382#define DP_REMOTE_I2C_WRITE 0x23
383#define DP_POWER_UP_PHY 0x24
384#define DP_POWER_DOWN_PHY 0x25
385#define DP_SINK_EVENT_NOTIFY 0x30
386#define DP_QUERY_STREAM_ENC_STATUS 0x38
387
388/* DP 1.2 MST sideband nak reasons - table 2.84 */
389#define DP_NAK_WRITE_FAILURE 0x01
390#define DP_NAK_INVALID_READ 0x02
391#define DP_NAK_CRC_FAILURE 0x03
392#define DP_NAK_BAD_PARAM 0x04
393#define DP_NAK_DEFER 0x05
394#define DP_NAK_LINK_FAILURE 0x06
395#define DP_NAK_NO_RESOURCES 0x07
396#define DP_NAK_DPCD_FAIL 0x08
397#define DP_NAK_I2C_NAK 0x09
398#define DP_NAK_ALLOCATE_FAIL 0x0a
399
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DA
400#define MODE_I2C_START 1
401#define MODE_I2C_WRITE 2
402#define MODE_I2C_READ 4
403#define MODE_I2C_STOP 8
404
28164fda
DV
405/**
406 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
407 * aux algorithm
408 * @running: set by the algo indicating whether an i2c is ongoing or whether
409 * the i2c bus is quiescent
410 * @address: i2c target address for the currently ongoing transfer
411 * @aux_ch: driver callback to transfer a single byte of the i2c payload
412 */
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413struct i2c_algo_dp_aux_data {
414 bool running;
415 u16 address;
416 int (*aux_ch) (struct i2c_adapter *adapter,
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DA
417 int mode, uint8_t write_byte,
418 uint8_t *read_byte);
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419};
420
421int
422i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
423
1ffdff13
DV
424
425#define DP_LINK_STATUS_SIZE 6
0aec2881 426bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1ffdff13 427 int lane_count);
0aec2881 428bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
01916270 429 int lane_count);
0aec2881 430u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
0f037bde 431 int lane);
0aec2881 432u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
0f037bde 433 int lane);
1ffdff13 434
52604b1f
SK
435#define DP_RECEIVER_CAP_SIZE 0xf
436#define EDP_PSR_RECEIVER_CAP_SIZE 2
437
0aec2881
JN
438void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
439void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1a644cd4 440
3b5c662e
DV
441u8 drm_dp_link_rate_to_bw_code(int link_rate);
442int drm_dp_bw_code_to_link_rate(u8 link_bw);
443
52604b1f
SK
444struct edp_sdp_header {
445 u8 HB0; /* Secondary Data Packet ID */
446 u8 HB1; /* Secondary Data Packet Type */
447 u8 HB2; /* 7:5 reserved, 4:0 revision number */
448 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
449} __packed;
450
451#define EDP_SDP_HEADER_REVISION_MASK 0x1F
452#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
453
454struct edp_vsc_psr {
455 struct edp_sdp_header sdp_header;
456 u8 DB0; /* Stereo Interface */
457 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
458 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
459 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
460 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
461 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
462 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
463 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
464 u8 DB8_31[24]; /* Reserved */
465} __packed;
466
467#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
468#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
469#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
470
3b5c662e 471static inline int
0aec2881 472drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
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473{
474 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
475}
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476
477static inline u8
0aec2881 478drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
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479{
480 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
481}
482
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483static inline bool
484drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
485{
486 return dpcd[DP_DPCD_REV] >= 0x11 &&
487 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
488}
489
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490/*
491 * DisplayPort AUX channel
492 */
493
494/**
495 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
496 * @address: address of the (first) register to access
497 * @request: contains the type of transaction (see DP_AUX_* macros)
498 * @reply: upon completion, contains the reply type of the transaction
499 * @buffer: pointer to a transmission or reception buffer
500 * @size: size of @buffer
501 */
502struct drm_dp_aux_msg {
503 unsigned int address;
504 u8 request;
505 u8 reply;
506 void *buffer;
507 size_t size;
508};
509
510/**
511 * struct drm_dp_aux - DisplayPort AUX channel
88759686 512 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
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513 * @dev: pointer to struct device that is the parent for this AUX channel
514 * @transfer: transfers a message representing a single AUX transaction
515 *
516 * The .dev field should be set to a pointer to the device that implements
517 * the AUX channel.
518 *
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519 * The .name field may be used to specify the name of the I2C adapter. If set to
520 * NULL, dev_name() of .dev will be used.
521 *
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522 * Drivers provide a hardware-specific implementation of how transactions
523 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
524 * structure describing the transaction is passed into this function. Upon
525 * success, the implementation should return the number of payload bytes
526 * that were transferred, or a negative error-code on failure. Helpers
527 * propagate errors from the .transfer() function, with the exception of
528 * the -EBUSY error, which causes a transaction to be retried. On a short,
529 * helpers will return -EPROTO to make it simpler to check for failure.
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530 *
531 * An AUX channel can also be used to transport I2C messages to a sink. A
532 * typical application of that is to access an EDID that's present in the
533 * sink device. The .transfer() function can also be used to execute such
534 * transactions. The drm_dp_aux_register_i2c_bus() function registers an
535 * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
536 * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter.
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537 *
538 * Note that the aux helper code assumes that the .transfer() function
539 * only modifies the reply field of the drm_dp_aux_msg structure. The
540 * retry logic and i2c helpers assume this is the case.
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541 */
542struct drm_dp_aux {
9dc40560 543 const char *name;
88759686 544 struct i2c_adapter ddc;
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545 struct device *dev;
546
547 ssize_t (*transfer)(struct drm_dp_aux *aux,
548 struct drm_dp_aux_msg *msg);
549};
550
551ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
552 void *buffer, size_t size);
553ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
554 void *buffer, size_t size);
555
556/**
557 * drm_dp_dpcd_readb() - read a single byte from the DPCD
558 * @aux: DisplayPort AUX channel
559 * @offset: address of the register to read
560 * @valuep: location where the value of the register will be stored
561 *
562 * Returns the number of bytes transferred (1) on success, or a negative
563 * error code on failure.
564 */
565static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
566 unsigned int offset, u8 *valuep)
567{
568 return drm_dp_dpcd_read(aux, offset, valuep, 1);
569}
570
571/**
572 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
573 * @aux: DisplayPort AUX channel
574 * @offset: address of the register to write
575 * @value: value to write to the register
576 *
577 * Returns the number of bytes transferred (1) on success, or a negative
578 * error code on failure.
579 */
580static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
581 unsigned int offset, u8 value)
582{
583 return drm_dp_dpcd_write(aux, offset, &value, 1);
584}
585
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586int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
587 u8 status[DP_LINK_STATUS_SIZE]);
588
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589/*
590 * DisplayPort link
591 */
592#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
593
594struct drm_dp_link {
595 unsigned char revision;
596 unsigned int rate;
597 unsigned int num_lanes;
598 unsigned long capabilities;
599};
600
601int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
602int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
603int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
604
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605int drm_dp_aux_register_i2c_bus(struct drm_dp_aux *aux);
606void drm_dp_aux_unregister_i2c_bus(struct drm_dp_aux *aux);
607
ab2c0672 608#endif /* _DRM_DP_HELPER_H_ */