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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
ab2c0672 DA |
23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ | |
a4fc5ed6 | 25 | |
1a644cd4 | 26 | #include <linux/delay.h> |
80664f75 TR |
27 | #include <linux/i2c.h> |
28 | #include <linux/types.h> | |
e5b92773 | 29 | #include <drm/drm_connector.h> |
9f0e7ff4 | 30 | |
a477f4fc AJ |
31 | /* |
32 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that | |
33 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, | |
34 | * 1.0 devices basically don't exist in the wild. | |
35 | * | |
36 | * Abbreviations, in chronological order: | |
37 | * | |
38 | * eDP: Embedded DisplayPort version 1 | |
39 | * DPI: DisplayPort Interoperability Guideline v1.1a | |
40 | * 1.2: DisplayPort 1.2 | |
3c8a0922 | 41 | * MST: Multistream Transport - part of DP 1.2a |
a477f4fc AJ |
42 | * |
43 | * 1.2 formally includes both eDP and DPI definitions. | |
44 | */ | |
a4fc5ed6 | 45 | |
508882f0 VS |
46 | /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ |
47 | #define DP_MSA_MISC_SYNC_CLOCK (1 << 0) | |
48 | #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) | |
49 | #define DP_MSA_MISC_STEREO_NO_3D (0 << 9) | |
50 | #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) | |
51 | #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) | |
52 | /* bits per component for non-RAW */ | |
53 | #define DP_MSA_MISC_6_BPC (0 << 5) | |
54 | #define DP_MSA_MISC_8_BPC (1 << 5) | |
55 | #define DP_MSA_MISC_10_BPC (2 << 5) | |
56 | #define DP_MSA_MISC_12_BPC (3 << 5) | |
57 | #define DP_MSA_MISC_16_BPC (4 << 5) | |
58 | /* bits per component for RAW */ | |
59 | #define DP_MSA_MISC_RAW_6_BPC (1 << 5) | |
60 | #define DP_MSA_MISC_RAW_7_BPC (2 << 5) | |
61 | #define DP_MSA_MISC_RAW_8_BPC (3 << 5) | |
62 | #define DP_MSA_MISC_RAW_10_BPC (4 << 5) | |
63 | #define DP_MSA_MISC_RAW_12_BPC (5 << 5) | |
64 | #define DP_MSA_MISC_RAW_14_BPC (6 << 5) | |
65 | #define DP_MSA_MISC_RAW_16_BPC (7 << 5) | |
66 | /* pixel encoding/colorimetry format */ | |
67 | #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ | |
68 | ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) | |
69 | #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) | |
70 | #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) | |
71 | #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) | |
72 | #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) | |
73 | #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) | |
74 | #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) | |
75 | #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) | |
76 | #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) | |
77 | #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) | |
78 | #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) | |
79 | #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) | |
80 | #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) | |
81 | #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) | |
82 | #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) | |
83 | #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) | |
84 | #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) | |
85 | #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) | |
86 | #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) | |
87 | ||
1d002fa7 SF |
88 | #define DP_AUX_MAX_PAYLOAD_BYTES 16 |
89 | ||
6b27f7f0 TR |
90 | #define DP_AUX_I2C_WRITE 0x0 |
91 | #define DP_AUX_I2C_READ 0x1 | |
2b712be7 | 92 | #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 |
6b27f7f0 TR |
93 | #define DP_AUX_I2C_MOT 0x4 |
94 | #define DP_AUX_NATIVE_WRITE 0x8 | |
95 | #define DP_AUX_NATIVE_READ 0x9 | |
a4fc5ed6 | 96 | |
6b27f7f0 TR |
97 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
98 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) | |
99 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) | |
100 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) | |
a4fc5ed6 | 101 | |
6b27f7f0 TR |
102 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
103 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) | |
104 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) | |
105 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) | |
a4fc5ed6 KP |
106 | |
107 | /* AUX CH addresses */ | |
5801ead6 AD |
108 | /* DPCD */ |
109 | #define DP_DPCD_REV 0x000 | |
0597017c MA |
110 | # define DP_DPCD_REV_10 0x10 |
111 | # define DP_DPCD_REV_11 0x11 | |
112 | # define DP_DPCD_REV_12 0x12 | |
113 | # define DP_DPCD_REV_13 0x13 | |
114 | # define DP_DPCD_REV_14 0x14 | |
746c1aa4 | 115 | |
5801ead6 AD |
116 | #define DP_MAX_LINK_RATE 0x001 |
117 | ||
118 | #define DP_MAX_LANE_COUNT 0x002 | |
119 | # define DP_MAX_LANE_COUNT_MASK 0x1f | |
a477f4fc | 120 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
5801ead6 AD |
121 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
122 | ||
123 | #define DP_MAX_DOWNSPREAD 0x003 | |
56c5da00 | 124 | # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) |
5801ead6 | 125 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
41d2f5fa | 126 | # define DP_TPS4_SUPPORTED (1 << 7) |
5801ead6 AD |
127 | |
128 | #define DP_NORP 0x004 | |
129 | ||
130 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 | |
131 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) | |
132 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 | |
3d2e423e JN |
133 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
134 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) | |
135 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) | |
136 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) | |
5801ead6 | 137 | # define DP_FORMAT_CONVERSION (1 << 3) |
a477f4fc | 138 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
5801ead6 AD |
139 | |
140 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 | |
99c830b8 | 141 | # define DP_CAP_ANSI_8B10B (1 << 0) |
5801ead6 | 142 | |
de44d971 | 143 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
e89861df | 144 | # define DP_PORT_COUNT_MASK 0x0f |
a477f4fc | 145 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
e89861df AJ |
146 | # define DP_OUI_SUPPORT (1 << 7) |
147 | ||
9474675a JN |
148 | #define DP_RECEIVE_PORT_0_CAP_0 0x008 |
149 | # define DP_LOCAL_EDID_PRESENT (1 << 1) | |
150 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) | |
151 | ||
152 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 | |
153 | ||
154 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a | |
155 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b | |
156 | ||
a477f4fc | 157 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
e89861df AJ |
158 | # define DP_I2C_SPEED_1K 0x01 |
159 | # define DP_I2C_SPEED_5K 0x02 | |
160 | # define DP_I2C_SPEED_10K 0x04 | |
161 | # define DP_I2C_SPEED_100K 0x08 | |
162 | # define DP_I2C_SPEED_400K 0x10 | |
163 | # define DP_I2C_SPEED_1M 0x20 | |
de44d971 | 164 | |
a477f4fc | 165 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
9474675a JN |
166 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) |
167 | # define DP_FRAMING_CHANGE_CAP (1 << 1) | |
e045d20b | 168 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ |
bd5da992 | 169 | |
0aeb35ea MA |
170 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
171 | # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ | |
172 | # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ | |
428c4b51 | 173 | |
9474675a JN |
174 | #define DP_ADAPTER_CAP 0x00f /* 1.2 */ |
175 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) | |
176 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) | |
177 | ||
bd5da992 JN |
178 | #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ |
179 | # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ | |
180 | ||
e89861df | 181 | /* Multiple stream transport */ |
3c8a0922 DA |
182 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
183 | # define DP_FAUX_CAP_1 (1 << 0) | |
184 | ||
a477f4fc | 185 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
e89861df AJ |
186 | # define DP_MST_CAP (1 << 0) |
187 | ||
9474675a JN |
188 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ |
189 | ||
190 | /* AV_SYNC_DATA_BLOCK 1.2 */ | |
191 | #define DP_AV_GRANULARITY 0x023 | |
192 | # define DP_AG_FACTOR_MASK (0xf << 0) | |
193 | # define DP_AG_FACTOR_3MS (0 << 0) | |
194 | # define DP_AG_FACTOR_2MS (1 << 0) | |
195 | # define DP_AG_FACTOR_1MS (2 << 0) | |
196 | # define DP_AG_FACTOR_500US (3 << 0) | |
197 | # define DP_AG_FACTOR_200US (4 << 0) | |
198 | # define DP_AG_FACTOR_100US (5 << 0) | |
199 | # define DP_AG_FACTOR_10US (6 << 0) | |
200 | # define DP_AG_FACTOR_1US (7 << 0) | |
201 | # define DP_VG_FACTOR_MASK (0xf << 4) | |
202 | # define DP_VG_FACTOR_3MS (0 << 4) | |
203 | # define DP_VG_FACTOR_2MS (1 << 4) | |
204 | # define DP_VG_FACTOR_1MS (2 << 4) | |
205 | # define DP_VG_FACTOR_500US (3 << 4) | |
206 | # define DP_VG_FACTOR_200US (4 << 4) | |
207 | # define DP_VG_FACTOR_100US (5 << 4) | |
208 | ||
209 | #define DP_AUD_DEC_LAT0 0x024 | |
210 | #define DP_AUD_DEC_LAT1 0x025 | |
211 | ||
212 | #define DP_AUD_PP_LAT0 0x026 | |
213 | #define DP_AUD_PP_LAT1 0x027 | |
214 | ||
215 | #define DP_VID_INTER_LAT 0x028 | |
216 | ||
217 | #define DP_VID_PROG_LAT 0x029 | |
218 | ||
219 | #define DP_REP_LAT 0x02a | |
220 | ||
221 | #define DP_AUD_DEL_INS0 0x02b | |
222 | #define DP_AUD_DEL_INS1 0x02c | |
223 | #define DP_AUD_DEL_INS2 0x02d | |
224 | /* End of AV_SYNC_DATA_BLOCK */ | |
225 | ||
6b1e3f61 JN |
226 | #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ |
227 | # define DP_ALPM_CAP (1 << 0) | |
228 | ||
229 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ | |
230 | # define DP_AUX_FRAME_SYNC_CAP (1 << 0) | |
231 | ||
3c8a0922 DA |
232 | #define DP_GUID 0x030 /* 1.2 */ |
233 | ||
ab6a46ea NM |
234 | #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ |
235 | # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) | |
236 | ||
237 | #define DP_DSC_REV 0x061 | |
238 | # define DP_DSC_MAJOR_MASK (0xf << 0) | |
239 | # define DP_DSC_MINOR_MASK (0xf << 4) | |
240 | # define DP_DSC_MAJOR_SHIFT 0 | |
241 | # define DP_DSC_MINOR_SHIFT 4 | |
242 | ||
243 | #define DP_DSC_RC_BUF_BLK_SIZE 0x062 | |
244 | # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 | |
245 | # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 | |
246 | # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 | |
247 | # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 | |
248 | ||
249 | #define DP_DSC_RC_BUF_SIZE 0x063 | |
250 | ||
251 | #define DP_DSC_SLICE_CAP_1 0x064 | |
252 | # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) | |
253 | # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) | |
254 | # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) | |
255 | # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) | |
256 | # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) | |
257 | # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) | |
258 | # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) | |
259 | ||
260 | #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 | |
261 | # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) | |
262 | # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 | |
263 | # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 | |
264 | # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 | |
265 | # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 | |
266 | # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 | |
267 | # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 | |
268 | # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 | |
269 | # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 | |
270 | # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 | |
271 | ||
272 | #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 | |
273 | # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) | |
274 | ||
275 | #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ | |
276 | ||
277 | #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ | |
ffddc436 MN |
278 | # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) |
279 | # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 | |
ab6a46ea NM |
280 | |
281 | #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 | |
282 | # define DP_DSC_RGB (1 << 0) | |
283 | # define DP_DSC_YCbCr444 (1 << 1) | |
284 | # define DP_DSC_YCbCr422_Simple (1 << 2) | |
285 | # define DP_DSC_YCbCr422_Native (1 << 3) | |
286 | # define DP_DSC_YCbCr420_Native (1 << 4) | |
287 | ||
288 | #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A | |
289 | # define DP_DSC_8_BPC (1 << 1) | |
290 | # define DP_DSC_10_BPC (1 << 2) | |
291 | # define DP_DSC_12_BPC (1 << 3) | |
292 | ||
293 | #define DP_DSC_PEAK_THROUGHPUT 0x06B | |
294 | # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) | |
295 | # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 | |
7837300c | 296 | # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 |
ab6a46ea NM |
297 | # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) |
298 | # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) | |
299 | # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) | |
300 | # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) | |
301 | # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) | |
302 | # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) | |
303 | # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) | |
304 | # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) | |
305 | # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) | |
306 | # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) | |
307 | # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) | |
308 | # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) | |
309 | # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) | |
310 | # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) | |
843cd325 | 311 | # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ |
ab6a46ea NM |
312 | # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) |
313 | # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 | |
7837300c | 314 | # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0 |
ab6a46ea NM |
315 | # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) |
316 | # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) | |
317 | # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) | |
318 | # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) | |
319 | # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) | |
320 | # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) | |
321 | # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) | |
322 | # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) | |
323 | # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) | |
324 | # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) | |
325 | # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) | |
326 | # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) | |
327 | # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) | |
328 | # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) | |
d7cd0e05 | 329 | # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4) |
ab6a46ea NM |
330 | |
331 | #define DP_DSC_MAX_SLICE_WIDTH 0x06C | |
ffddc436 MN |
332 | #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 |
333 | #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 | |
ab6a46ea NM |
334 | |
335 | #define DP_DSC_SLICE_CAP_2 0x06D | |
336 | # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) | |
337 | # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) | |
338 | # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) | |
339 | ||
340 | #define DP_DSC_BITS_PER_PIXEL_INC 0x06F | |
341 | # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 | |
342 | # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 | |
343 | # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 | |
344 | # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 | |
345 | # define DP_DSC_BITS_PER_PIXEL_1 0x4 | |
346 | ||
a477f4fc | 347 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
b73fe58c | 348 | # define DP_PSR_IS_SUPPORTED 1 |
6b1e3f61 | 349 | # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ |
c5fe4732 | 350 | # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ |
6b1e3f61 | 351 | |
a477f4fc | 352 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
b73fe58c BW |
353 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
354 | # define DP_PSR_SETUP_TIME_330 (0 << 1) | |
355 | # define DP_PSR_SETUP_TIME_275 (1 << 1) | |
356 | # define DP_PSR_SETUP_TIME_220 (2 << 1) | |
357 | # define DP_PSR_SETUP_TIME_165 (3 << 1) | |
358 | # define DP_PSR_SETUP_TIME_110 (4 << 1) | |
359 | # define DP_PSR_SETUP_TIME_55 (5 << 1) | |
360 | # define DP_PSR_SETUP_TIME_0 (6 << 1) | |
361 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) | |
362 | # define DP_PSR_SETUP_TIME_SHIFT 1 | |
d0ce9062 NV |
363 | # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ |
364 | # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ | |
71b15621 JRS |
365 | |
366 | #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ | |
367 | #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ | |
368 | ||
e89861df AJ |
369 | /* |
370 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts | |
371 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, | |
372 | * each port's descriptor is one byte wide. If it was set, each port's is | |
373 | * four bytes wide, starting with the one byte from the base info. As of | |
374 | * DP interop v1.1a only VGA defines additional detail. | |
375 | */ | |
376 | ||
377 | /* offset 0 */ | |
378 | #define DP_DOWNSTREAM_PORT_0 0x80 | |
379 | # define DP_DS_PORT_TYPE_MASK (7 << 0) | |
380 | # define DP_DS_PORT_TYPE_DP 0 | |
381 | # define DP_DS_PORT_TYPE_VGA 1 | |
382 | # define DP_DS_PORT_TYPE_DVI 2 | |
383 | # define DP_DS_PORT_TYPE_HDMI 3 | |
384 | # define DP_DS_PORT_TYPE_NON_EDID 4 | |
69b1e00f MK |
385 | # define DP_DS_PORT_TYPE_DP_DUALMODE 5 |
386 | # define DP_DS_PORT_TYPE_WIRELESS 6 | |
e89861df AJ |
387 | # define DP_DS_PORT_HPD (1 << 3) |
388 | /* offset 1 for VGA is maximum megapixels per second / 8 */ | |
389 | /* offset 2 */ | |
8fedf080 MK |
390 | # define DP_DS_MAX_BPC_MASK (3 << 0) |
391 | # define DP_DS_8BPC 0 | |
392 | # define DP_DS_10BPC 1 | |
393 | # define DP_DS_12BPC 2 | |
394 | # define DP_DS_16BPC 3 | |
e89861df | 395 | |
e5124751 OV |
396 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
397 | ||
45640058 AS |
398 | /* DP Forward error Correction Registers */ |
399 | #define DP_FEC_CAPABILITY 0x090 /* 1.4 */ | |
400 | # define DP_FEC_CAPABLE (1 << 0) | |
401 | # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) | |
402 | # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) | |
403 | # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) | |
404 | ||
f446489a NC |
405 | /* DP Extended DSC Capabilities */ |
406 | #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ | |
407 | #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 | |
408 | #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 | |
409 | ||
5801ead6 AD |
410 | /* link configuration */ |
411 | #define DP_LINK_BW_SET 0x100 | |
6b1e3f61 | 412 | # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ |
a4fc5ed6 KP |
413 | # define DP_LINK_BW_1_62 0x06 |
414 | # define DP_LINK_BW_2_7 0x0a | |
a477f4fc | 415 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
e0bd878a | 416 | # define DP_LINK_BW_8_1 0x1e /* 1.4 */ |
a4fc5ed6 | 417 | |
5801ead6 | 418 | #define DP_LANE_COUNT_SET 0x101 |
a4fc5ed6 KP |
419 | # define DP_LANE_COUNT_MASK 0x0f |
420 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) | |
421 | ||
5801ead6 | 422 | #define DP_TRAINING_PATTERN_SET 0x102 |
a4fc5ed6 KP |
423 | # define DP_TRAINING_PATTERN_DISABLE 0 |
424 | # define DP_TRAINING_PATTERN_1 1 | |
425 | # define DP_TRAINING_PATTERN_2 2 | |
a477f4fc | 426 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
41d2f5fa | 427 | # define DP_TRAINING_PATTERN_4 7 /* 1.4 */ |
a4fc5ed6 | 428 | # define DP_TRAINING_PATTERN_MASK 0x3 |
41d2f5fa | 429 | # define DP_TRAINING_PATTERN_MASK_1_4 0xf |
a4fc5ed6 | 430 | |
9474675a JN |
431 | /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ |
432 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) | |
433 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) | |
434 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) | |
435 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) | |
436 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) | |
a4fc5ed6 KP |
437 | |
438 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) | |
439 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) | |
440 | ||
441 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) | |
442 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) | |
443 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) | |
444 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) | |
445 | ||
446 | #define DP_TRAINING_LANE0_SET 0x103 | |
447 | #define DP_TRAINING_LANE1_SET 0x104 | |
448 | #define DP_TRAINING_LANE2_SET 0x105 | |
449 | #define DP_TRAINING_LANE3_SET 0x106 | |
450 | ||
451 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 | |
452 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 | |
453 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) | |
0504cd17 | 454 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
0504cd17 | 455 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
0504cd17 | 456 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
0504cd17 | 457 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
a4fc5ed6 KP |
458 | |
459 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) | |
0504cd17 | 460 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
0504cd17 | 461 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
0504cd17 | 462 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
0504cd17 | 463 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
a4fc5ed6 KP |
464 | |
465 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 | |
466 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) | |
467 | ||
468 | #define DP_DOWNSPREAD_CTRL 0x107 | |
469 | # define DP_SPREAD_AMP_0_5 (1 << 4) | |
a477f4fc | 470 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
a4fc5ed6 KP |
471 | |
472 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 | |
473 | # define DP_SET_ANSI_8B10B (1 << 0) | |
474 | ||
a477f4fc | 475 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
e89861df AJ |
476 | /* bitmask as for DP_I2C_SPEED_CAP */ |
477 | ||
a477f4fc | 478 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
9474675a JN |
479 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) |
480 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1) | |
481 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) | |
482 | ||
483 | #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ | |
484 | #define DP_LINK_QUAL_LANE1_SET 0x10c | |
485 | #define DP_LINK_QUAL_LANE2_SET 0x10d | |
486 | #define DP_LINK_QUAL_LANE3_SET 0x10e | |
487 | # define DP_LINK_QUAL_PATTERN_DISABLE 0 | |
488 | # define DP_LINK_QUAL_PATTERN_D10_2 1 | |
489 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 | |
490 | # define DP_LINK_QUAL_PATTERN_PRBS7 3 | |
491 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 | |
492 | # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 | |
493 | # define DP_LINK_QUAL_PATTERN_MASK 7 | |
494 | ||
495 | #define DP_TRAINING_LANE0_1_SET2 0x10f | |
496 | #define DP_TRAINING_LANE2_3_SET2 0x110 | |
497 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) | |
498 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) | |
499 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) | |
500 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) | |
e89861df | 501 | |
a477f4fc | 502 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
e89861df AJ |
503 | # define DP_MST_EN (1 << 0) |
504 | # define DP_UP_REQ_EN (1 << 1) | |
505 | # define DP_UPSTREAM_IS_SRC (1 << 2) | |
506 | ||
9474675a JN |
507 | #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ |
508 | #define DP_AUDIO_DELAY1 0x113 | |
509 | #define DP_AUDIO_DELAY2 0x114 | |
510 | ||
bd5da992 | 511 | #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ |
6b1e3f61 JN |
512 | # define DP_LINK_RATE_SET_SHIFT 0 |
513 | # define DP_LINK_RATE_SET_MASK (7 << 0) | |
514 | ||
515 | #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ | |
516 | # define DP_ALPM_ENABLE (1 << 0) | |
517 | # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) | |
518 | ||
519 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ | |
520 | # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) | |
521 | # define DP_IRQ_HPD_ENABLE (1 << 1) | |
e045d20b | 522 | |
9474675a JN |
523 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ |
524 | # define DP_PWR_NOT_NEEDED (1 << 0) | |
525 | ||
45640058 AS |
526 | #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ |
527 | # define DP_FEC_READY (1 << 0) | |
528 | # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) | |
529 | # define DP_FEC_ERR_COUNT_DIS (0 << 1) | |
530 | # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) | |
531 | # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) | |
532 | # define DP_FEC_BIT_ERROR_COUNT (3 << 1) | |
533 | # define DP_FEC_LANE_SELECT_MASK (3 << 4) | |
534 | # define DP_FEC_LANE_0_SELECT (0 << 4) | |
535 | # define DP_FEC_LANE_1_SELECT (1 << 4) | |
536 | # define DP_FEC_LANE_2_SELECT (2 << 4) | |
537 | # define DP_FEC_LANE_3_SELECT (3 << 4) | |
538 | ||
6b1e3f61 JN |
539 | #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ |
540 | # define DP_AUX_FRAME_SYNC_VALID (1 << 0) | |
541 | ||
ab6a46ea | 542 | #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ |
ffddc436 | 543 | # define DP_DECOMPRESSION_EN (1 << 0) |
ab6a46ea | 544 | |
a477f4fc | 545 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
b73fe58c BW |
546 | # define DP_PSR_ENABLE (1 << 0) |
547 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) | |
548 | # define DP_PSR_CRC_VERIFICATION (1 << 2) | |
549 | # define DP_PSR_FRAME_CAPTURE (1 << 3) | |
6b1e3f61 JN |
550 | # define DP_PSR_SELECTIVE_UPDATE (1 << 4) |
551 | # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) | |
4f212e40 | 552 | # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ |
b73fe58c | 553 | |
3c8a0922 DA |
554 | #define DP_ADAPTER_CTRL 0x1a0 |
555 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) | |
556 | ||
557 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 | |
558 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) | |
559 | ||
560 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 | |
561 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 | |
562 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 | |
563 | ||
e89861df | 564 | #define DP_SINK_COUNT 0x200 |
da131a46 AJ |
565 | /* prior to 1.2 bit 7 was reserved mbz */ |
566 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) | |
e89861df AJ |
567 | # define DP_SINK_CP_READY (1 << 6) |
568 | ||
a60f0e38 JB |
569 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
570 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) | |
571 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) | |
572 | # define DP_CP_IRQ (1 << 2) | |
3c8a0922 DA |
573 | # define DP_MCCS_IRQ (1 << 3) |
574 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ | |
575 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ | |
a60f0e38 JB |
576 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
577 | ||
a4fc5ed6 KP |
578 | #define DP_LANE0_1_STATUS 0x202 |
579 | #define DP_LANE2_3_STATUS 0x203 | |
a4fc5ed6 KP |
580 | # define DP_LANE_CR_DONE (1 << 0) |
581 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) | |
582 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) | |
583 | ||
5801ead6 AD |
584 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
585 | DP_LANE_CHANNEL_EQ_DONE | \ | |
586 | DP_LANE_SYMBOL_LOCKED) | |
587 | ||
a4fc5ed6 KP |
588 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
589 | ||
590 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) | |
591 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) | |
592 | #define DP_LINK_STATUS_UPDATED (1 << 7) | |
593 | ||
594 | #define DP_SINK_STATUS 0x205 | |
595 | ||
596 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) | |
597 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) | |
598 | ||
599 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 | |
600 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 | |
5801ead6 AD |
601 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
602 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 | |
603 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c | |
604 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 | |
605 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 | |
606 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 | |
607 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 | |
608 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 | |
a4fc5ed6 | 609 | |
ac58fff1 | 610 | #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c |
79465e0f TR |
611 | # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03 |
612 | # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0 | |
613 | # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c | |
614 | # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2 | |
615 | # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30 | |
616 | # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4 | |
617 | # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0 | |
618 | # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6 | |
ac58fff1 | 619 | |
a60f0e38 JB |
620 | #define DP_TEST_REQUEST 0x218 |
621 | # define DP_TEST_LINK_TRAINING (1 << 0) | |
fe3c703c | 622 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
a60f0e38 JB |
623 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
624 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ | |
fe3c703c | 625 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
45815d09 CU |
626 | # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ |
627 | # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ | |
a60f0e38 JB |
628 | |
629 | #define DP_TEST_LINK_RATE 0x219 | |
630 | # define DP_LINK_RATE_162 (0x6) | |
631 | # define DP_LINK_RATE_27 (0xa) | |
632 | ||
633 | #define DP_TEST_LANE_COUNT 0x220 | |
634 | ||
635 | #define DP_TEST_PATTERN 0x221 | |
08b79f62 MN |
636 | # define DP_NO_TEST_PATTERN 0x0 |
637 | # define DP_COLOR_RAMP 0x1 | |
638 | # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 | |
639 | # define DP_COLOR_SQUARE 0x3 | |
640 | ||
641 | #define DP_TEST_H_TOTAL_HI 0x222 | |
642 | #define DP_TEST_H_TOTAL_LO 0x223 | |
643 | ||
644 | #define DP_TEST_V_TOTAL_HI 0x224 | |
645 | #define DP_TEST_V_TOTAL_LO 0x225 | |
646 | ||
647 | #define DP_TEST_H_START_HI 0x226 | |
648 | #define DP_TEST_H_START_LO 0x227 | |
649 | ||
650 | #define DP_TEST_V_START_HI 0x228 | |
651 | #define DP_TEST_V_START_LO 0x229 | |
652 | ||
653 | #define DP_TEST_HSYNC_HI 0x22A | |
654 | # define DP_TEST_HSYNC_POLARITY (1 << 7) | |
655 | # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) | |
656 | #define DP_TEST_HSYNC_WIDTH_LO 0x22B | |
657 | ||
658 | #define DP_TEST_VSYNC_HI 0x22C | |
659 | # define DP_TEST_VSYNC_POLARITY (1 << 7) | |
660 | # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) | |
661 | #define DP_TEST_VSYNC_WIDTH_LO 0x22D | |
662 | ||
663 | #define DP_TEST_H_WIDTH_HI 0x22E | |
664 | #define DP_TEST_H_WIDTH_LO 0x22F | |
665 | ||
666 | #define DP_TEST_V_HEIGHT_HI 0x230 | |
667 | #define DP_TEST_V_HEIGHT_LO 0x231 | |
668 | ||
669 | #define DP_TEST_MISC0 0x232 | |
670 | # define DP_TEST_SYNC_CLOCK (1 << 0) | |
671 | # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) | |
672 | # define DP_TEST_COLOR_FORMAT_SHIFT 1 | |
673 | # define DP_COLOR_FORMAT_RGB (0 << 1) | |
674 | # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) | |
675 | # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) | |
45815d09 | 676 | # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) |
08b79f62 MN |
677 | # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) |
678 | # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) | |
679 | # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) | |
680 | # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) | |
681 | # define DP_TEST_BIT_DEPTH_MASK (7 << 5) | |
682 | # define DP_TEST_BIT_DEPTH_SHIFT 5 | |
683 | # define DP_TEST_BIT_DEPTH_6 (0 << 5) | |
684 | # define DP_TEST_BIT_DEPTH_8 (1 << 5) | |
685 | # define DP_TEST_BIT_DEPTH_10 (2 << 5) | |
686 | # define DP_TEST_BIT_DEPTH_12 (3 << 5) | |
687 | # define DP_TEST_BIT_DEPTH_16 (4 << 5) | |
688 | ||
689 | #define DP_TEST_MISC1 0x233 | |
690 | # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) | |
691 | # define DP_TEST_INTERLACED (1 << 1) | |
692 | ||
693 | #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 | |
a60f0e38 | 694 | |
ac58fff1 DA |
695 | #define DP_TEST_MISC0 0x232 |
696 | ||
a25eebb0 RV |
697 | #define DP_TEST_CRC_R_CR 0x240 |
698 | #define DP_TEST_CRC_G_Y 0x242 | |
699 | #define DP_TEST_CRC_B_CB 0x244 | |
700 | ||
701 | #define DP_TEST_SINK_MISC 0x246 | |
ad9dc91b | 702 | # define DP_TEST_CRC_SUPPORTED (1 << 5) |
90a21700 | 703 | # define DP_TEST_COUNT_MASK 0xf |
a25eebb0 | 704 | |
8811d9eb | 705 | #define DP_PHY_TEST_PATTERN 0x248 |
4342f839 AM |
706 | # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7 |
707 | # define DP_PHY_TEST_PATTERN_NONE 0x0 | |
708 | # define DP_PHY_TEST_PATTERN_D10_2 0x1 | |
709 | # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 | |
710 | # define DP_PHY_TEST_PATTERN_PRBS7 0x3 | |
711 | # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 | |
712 | # define DP_PHY_TEST_PATTERN_CP2520 0x5 | |
713 | ||
714 | #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A | |
ac58fff1 DA |
715 | #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 |
716 | #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 | |
717 | #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 | |
718 | #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 | |
719 | #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 | |
720 | #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 | |
721 | #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 | |
722 | #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 | |
723 | #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 | |
724 | #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 | |
725 | ||
a60f0e38 JB |
726 | #define DP_TEST_RESPONSE 0x260 |
727 | # define DP_TEST_ACK (1 << 0) | |
728 | # define DP_TEST_NAK (1 << 1) | |
729 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) | |
730 | ||
073ea2ae JH |
731 | #define DP_TEST_EDID_CHECKSUM 0x261 |
732 | ||
a25eebb0 | 733 | #define DP_TEST_SINK 0x270 |
ad9dc91b | 734 | # define DP_TEST_SINK_START (1 << 0) |
45815d09 CU |
735 | #define DP_TEST_AUDIO_MODE 0x271 |
736 | #define DP_TEST_AUDIO_PATTERN_TYPE 0x272 | |
737 | #define DP_TEST_AUDIO_PERIOD_CH1 0x273 | |
738 | #define DP_TEST_AUDIO_PERIOD_CH2 0x274 | |
739 | #define DP_TEST_AUDIO_PERIOD_CH3 0x275 | |
740 | #define DP_TEST_AUDIO_PERIOD_CH4 0x276 | |
741 | #define DP_TEST_AUDIO_PERIOD_CH5 0x277 | |
742 | #define DP_TEST_AUDIO_PERIOD_CH6 0x278 | |
743 | #define DP_TEST_AUDIO_PERIOD_CH7 0x279 | |
744 | #define DP_TEST_AUDIO_PERIOD_CH8 0x27A | |
a25eebb0 | 745 | |
45640058 AS |
746 | #define DP_FEC_STATUS 0x280 /* 1.4 */ |
747 | # define DP_FEC_DECODE_EN_DETECTED (1 << 0) | |
748 | # define DP_FEC_DECODE_DIS_DETECTED (1 << 1) | |
749 | ||
750 | #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ | |
751 | ||
752 | #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ | |
753 | # define DP_FEC_ERROR_COUNT_MASK 0x7F | |
754 | # define DP_FEC_ERR_COUNT_VALID (1 << 7) | |
755 | ||
3c8a0922 DA |
756 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
757 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) | |
758 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) | |
759 | ||
760 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ | |
761 | /* up to ID_SLOT_63 at 0x2ff */ | |
762 | ||
86c3c3be AJ |
763 | #define DP_SOURCE_OUI 0x300 |
764 | #define DP_SINK_OUI 0x400 | |
765 | #define DP_BRANCH_OUI 0x500 | |
266d783b | 766 | #define DP_BRANCH_ID 0x503 |
ac58fff1 | 767 | #define DP_BRANCH_REVISION_START 0x509 |
0e390a33 | 768 | #define DP_BRANCH_HW_REV 0x509 |
1a2724fa | 769 | #define DP_BRANCH_SW_REV 0x50A |
86c3c3be | 770 | |
1a66c95a | 771 | #define DP_SET_POWER 0x600 |
5801ead6 AD |
772 | # define DP_SET_POWER_D0 0x1 |
773 | # define DP_SET_POWER_D3 0x2 | |
516c0f7c | 774 | # define DP_SET_POWER_MASK 0x3 |
e26612aa | 775 | # define DP_SET_POWER_D3_AUX_ON 0x5 |
1a66c95a | 776 | |
bd5da992 | 777 | #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ |
6b1e3f61 JN |
778 | # define DP_EDP_11 0x00 |
779 | # define DP_EDP_12 0x01 | |
780 | # define DP_EDP_13 0x02 | |
781 | # define DP_EDP_14 0x03 | |
4c953d03 MN |
782 | # define DP_EDP_14a 0x04 /* eDP 1.4a */ |
783 | # define DP_EDP_14b 0x05 /* eDP 1.4b */ | |
e045d20b | 784 | |
0e71244c | 785 | #define DP_EDP_GENERAL_CAP_1 0x701 |
36af4ca7 JN |
786 | # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) |
787 | # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) | |
788 | # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) | |
789 | # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) | |
790 | # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) | |
791 | # define DP_EDP_FRC_ENABLE_CAP (1 << 5) | |
792 | # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) | |
793 | # define DP_EDP_SET_POWER_CAP (1 << 7) | |
0e71244c JN |
794 | |
795 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 | |
36af4ca7 JN |
796 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) |
797 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) | |
798 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) | |
799 | # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) | |
800 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) | |
801 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) | |
802 | # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) | |
803 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) | |
0e71244c JN |
804 | |
805 | #define DP_EDP_GENERAL_CAP_2 0x703 | |
36af4ca7 | 806 | # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) |
0e71244c | 807 | |
6b1e3f61 | 808 | #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ |
36af4ca7 JN |
809 | # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) |
810 | # define DP_EDP_X_REGION_CAP_SHIFT 0 | |
811 | # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) | |
812 | # define DP_EDP_Y_REGION_CAP_SHIFT 4 | |
6b1e3f61 | 813 | |
0e71244c | 814 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 |
36af4ca7 JN |
815 | # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) |
816 | # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) | |
817 | # define DP_EDP_FRC_ENABLE (1 << 2) | |
818 | # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) | |
819 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) | |
0e71244c JN |
820 | |
821 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 | |
36af4ca7 JN |
822 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) |
823 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) | |
824 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) | |
825 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) | |
826 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) | |
827 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) | |
828 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) | |
829 | # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) | |
830 | # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) | |
831 | # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ | |
0e71244c JN |
832 | |
833 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 | |
834 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 | |
835 | ||
836 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724 | |
837 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 | |
838 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 | |
77a494a7 | 839 | # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) |
0e71244c JN |
840 | |
841 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 | |
842 | ||
843 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 | |
77a494a7 | 844 | # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 |
0e71244c JN |
845 | |
846 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a | |
847 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b | |
848 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c | |
849 | ||
850 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d | |
851 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e | |
852 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f | |
853 | ||
854 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 | |
855 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 | |
856 | ||
6b1e3f61 JN |
857 | #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ |
858 | #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ | |
859 | ||
3c8a0922 DA |
860 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
861 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ | |
862 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ | |
863 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ | |
864 | ||
865 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ | |
866 | /* 0-5 sink count */ | |
867 | # define DP_SINK_COUNT_CP_READY (1 << 6) | |
868 | ||
869 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ | |
870 | ||
871 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ | |
d753e41d CT |
872 | # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) |
873 | # define DP_LOCK_ACQUISITION_REQUEST (1 << 1) | |
874 | # define DP_CEC_IRQ (1 << 2) | |
3c8a0922 DA |
875 | |
876 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ | |
877 | ||
a477f4fc | 878 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
b73fe58c BW |
879 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
880 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) | |
6b1e3f61 | 881 | # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ |
b73fe58c | 882 | |
a477f4fc | 883 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
b73fe58c BW |
884 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
885 | ||
a477f4fc | 886 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
b73fe58c BW |
887 | # define DP_PSR_SINK_INACTIVE 0 |
888 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 | |
889 | # define DP_PSR_SINK_ACTIVE_RFB 2 | |
890 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 | |
891 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 | |
892 | # define DP_PSR_SINK_INTERNAL_ERROR 7 | |
893 | # define DP_PSR_SINK_STATE_MASK 0x07 | |
894 | ||
ae59e633 | 895 | #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ |
896 | # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) | |
897 | # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 | |
898 | # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) | |
899 | # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 | |
900 | ||
fe36948a JRS |
901 | #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ |
902 | # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ | |
903 | # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ | |
904 | # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ | |
905 | # define DP_SU_VALID (1 << 3) /* eDP 1.4 */ | |
906 | # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ | |
907 | # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ | |
908 | # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ | |
909 | ||
6b1e3f61 JN |
910 | #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ |
911 | # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) | |
912 | ||
c673fe7f DP |
913 | #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ |
914 | #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ | |
915 | #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ | |
916 | #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ | |
917 | ||
ac58fff1 DA |
918 | #define DP_DP13_DPCD_REV 0x2200 |
919 | #define DP_DP13_MAX_LINK_RATE 0x2201 | |
920 | ||
d0ce9062 NV |
921 | #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ |
922 | # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ | |
923 | # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ | |
924 | # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ | |
925 | # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ | |
926 | # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ | |
927 | # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ | |
928 | # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ | |
929 | # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ | |
930 | ||
d753e41d CT |
931 | /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ |
932 | #define DP_CEC_TUNNELING_CAPABILITY 0x3000 | |
933 | # define DP_CEC_TUNNELING_CAPABLE (1 << 0) | |
934 | # define DP_CEC_SNOOPING_CAPABLE (1 << 1) | |
935 | # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) | |
936 | ||
937 | #define DP_CEC_TUNNELING_CONTROL 0x3001 | |
938 | # define DP_CEC_TUNNELING_ENABLE (1 << 0) | |
939 | # define DP_CEC_SNOOPING_ENABLE (1 << 1) | |
940 | ||
941 | #define DP_CEC_RX_MESSAGE_INFO 0x3002 | |
942 | # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) | |
943 | # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 | |
944 | # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) | |
945 | # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) | |
946 | # define DP_CEC_RX_MESSAGE_ACKED (1 << 6) | |
947 | # define DP_CEC_RX_MESSAGE_ENDED (1 << 7) | |
948 | ||
949 | #define DP_CEC_TX_MESSAGE_INFO 0x3003 | |
950 | # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) | |
951 | # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 | |
952 | # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) | |
953 | # define DP_CEC_TX_RETRY_COUNT_SHIFT 4 | |
954 | # define DP_CEC_TX_MESSAGE_SEND (1 << 7) | |
955 | ||
956 | #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 | |
957 | # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) | |
958 | # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) | |
959 | # define DP_CEC_TX_MESSAGE_SENT (1 << 4) | |
960 | # define DP_CEC_TX_LINE_ERROR (1 << 5) | |
961 | # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) | |
962 | # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) | |
963 | ||
964 | #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ | |
965 | # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) | |
966 | # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) | |
967 | # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) | |
968 | # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) | |
969 | # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) | |
970 | # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) | |
971 | # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) | |
972 | # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) | |
973 | #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ | |
974 | # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) | |
975 | # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) | |
976 | # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) | |
977 | # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) | |
978 | # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) | |
979 | # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) | |
980 | # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) | |
981 | # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) | |
982 | ||
983 | #define DP_CEC_RX_MESSAGE_BUFFER 0x3010 | |
984 | #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 | |
985 | #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 | |
986 | ||
495eb7f8 SP |
987 | #define DP_AUX_HDCP_BKSV 0x68000 |
988 | #define DP_AUX_HDCP_RI_PRIME 0x68005 | |
989 | #define DP_AUX_HDCP_AKSV 0x68007 | |
990 | #define DP_AUX_HDCP_AN 0x6800C | |
991 | #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) | |
992 | #define DP_AUX_HDCP_BCAPS 0x68028 | |
993 | # define DP_BCAPS_REPEATER_PRESENT BIT(1) | |
994 | # define DP_BCAPS_HDCP_CAPABLE BIT(0) | |
995 | #define DP_AUX_HDCP_BSTATUS 0x68029 | |
996 | # define DP_BSTATUS_REAUTH_REQ BIT(3) | |
997 | # define DP_BSTATUS_LINK_FAILURE BIT(2) | |
998 | # define DP_BSTATUS_R0_PRIME_READY BIT(1) | |
999 | # define DP_BSTATUS_READY BIT(0) | |
1000 | #define DP_AUX_HDCP_BINFO 0x6802A | |
1001 | #define DP_AUX_HDCP_KSV_FIFO 0x6802C | |
1002 | #define DP_AUX_HDCP_AINFO 0x6803B | |
1003 | ||
8b44fefe R |
1004 | /* DP HDCP2.2 parameter offsets in DPCD address space */ |
1005 | #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 | |
1006 | #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 | |
1007 | #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B | |
1008 | #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 | |
1009 | #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D | |
1010 | #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 | |
1011 | #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 | |
1012 | #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 | |
1013 | #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 | |
1014 | #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 | |
1015 | #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 | |
1016 | #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 | |
1017 | #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 | |
1018 | #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 | |
1019 | #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 | |
1020 | #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 | |
1021 | #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 | |
1022 | #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 | |
1023 | #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 | |
1024 | #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 | |
1025 | #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 | |
1026 | #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 | |
1027 | #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 | |
1028 | #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 | |
1029 | #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 | |
1030 | #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 | |
1031 | ||
55fd0e20 RS |
1032 | /* Link Training (LT)-tunable PHY Repeaters */ |
1033 | #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ | |
1034 | #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ | |
1035 | #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ | |
1036 | #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ | |
1037 | #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ | |
1038 | #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ | |
1039 | #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ | |
1040 | #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ | |
1041 | #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ | |
1042 | #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ | |
1043 | #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ | |
1044 | #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ | |
1045 | #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ | |
1046 | #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ | |
1047 | #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ | |
1048 | #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ | |
1049 | #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ | |
1050 | #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ | |
1051 | #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ | |
1052 | #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ | |
1053 | #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ | |
1054 | #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ | |
1055 | #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ | |
1056 | #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ | |
3f5f7420 RS |
1057 | #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */ |
1058 | #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */ | |
55fd0e20 | 1059 | |
1ccd5417 RS |
1060 | /* Repeater modes */ |
1061 | #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ | |
1062 | #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ | |
1063 | ||
8b44fefe R |
1064 | /* DP HDCP message start offsets in DPCD address space */ |
1065 | #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET | |
1066 | #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET | |
1067 | #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET | |
1068 | #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET | |
1069 | #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET | |
1070 | #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ | |
1071 | DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET | |
1072 | #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET | |
1073 | #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET | |
1074 | #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET | |
1075 | #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET | |
1076 | #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET | |
1077 | #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET | |
1078 | #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET | |
1079 | ||
1080 | #define HDCP_2_2_DP_RXSTATUS_LEN 1 | |
1081 | #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) | |
1082 | #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) | |
1083 | #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) | |
1084 | #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) | |
1085 | #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) | |
1086 | ||
3c8a0922 DA |
1087 | /* DP 1.2 Sideband message defines */ |
1088 | /* peer device type - DP 1.2a Table 2-92 */ | |
1089 | #define DP_PEER_DEVICE_NONE 0x0 | |
1090 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 | |
1091 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 | |
1092 | #define DP_PEER_DEVICE_SST_SINK 0x3 | |
1093 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 | |
1094 | ||
1095 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ | |
3dadbd29 | 1096 | #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */ |
3c8a0922 DA |
1097 | #define DP_LINK_ADDRESS 0x01 |
1098 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 | |
1099 | #define DP_ENUM_PATH_RESOURCES 0x10 | |
1100 | #define DP_ALLOCATE_PAYLOAD 0x11 | |
1101 | #define DP_QUERY_PAYLOAD 0x12 | |
1102 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 | |
1103 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 | |
1104 | #define DP_REMOTE_DPCD_READ 0x20 | |
1105 | #define DP_REMOTE_DPCD_WRITE 0x21 | |
1106 | #define DP_REMOTE_I2C_READ 0x22 | |
1107 | #define DP_REMOTE_I2C_WRITE 0x23 | |
1108 | #define DP_POWER_UP_PHY 0x24 | |
1109 | #define DP_POWER_DOWN_PHY 0x25 | |
1110 | #define DP_SINK_EVENT_NOTIFY 0x30 | |
1111 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 | |
1112 | ||
45bbda1e VS |
1113 | /* DP 1.2 MST sideband reply types */ |
1114 | #define DP_SIDEBAND_REPLY_ACK 0x00 | |
1115 | #define DP_SIDEBAND_REPLY_NAK 0x01 | |
1116 | ||
3c8a0922 DA |
1117 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ |
1118 | #define DP_NAK_WRITE_FAILURE 0x01 | |
1119 | #define DP_NAK_INVALID_READ 0x02 | |
1120 | #define DP_NAK_CRC_FAILURE 0x03 | |
1121 | #define DP_NAK_BAD_PARAM 0x04 | |
1122 | #define DP_NAK_DEFER 0x05 | |
1123 | #define DP_NAK_LINK_FAILURE 0x06 | |
1124 | #define DP_NAK_NO_RESOURCES 0x07 | |
1125 | #define DP_NAK_DPCD_FAIL 0x08 | |
1126 | #define DP_NAK_I2C_NAK 0x09 | |
1127 | #define DP_NAK_ALLOCATE_FAIL 0x0a | |
1128 | ||
ab2c0672 DA |
1129 | #define MODE_I2C_START 1 |
1130 | #define MODE_I2C_WRITE 2 | |
1131 | #define MODE_I2C_READ 4 | |
1132 | #define MODE_I2C_STOP 8 | |
1133 | ||
ccf03d69 DA |
1134 | /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ |
1135 | #define DP_MST_PHYSICAL_PORT_0 0 | |
1136 | #define DP_MST_LOGICAL_PORT_0 8 | |
1137 | ||
1ffdff13 | 1138 | #define DP_LINK_STATUS_SIZE 6 |
0aec2881 | 1139 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 | 1140 | int lane_count); |
0aec2881 | 1141 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
01916270 | 1142 | int lane_count); |
0aec2881 | 1143 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 1144 | int lane); |
0aec2881 | 1145 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 1146 | int lane); |
79465e0f TR |
1147 | u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], |
1148 | unsigned int lane); | |
1ffdff13 | 1149 | |
44790462 | 1150 | #define DP_BRANCH_OUI_HEADER_SIZE 0xc |
52604b1f | 1151 | #define DP_RECEIVER_CAP_SIZE 0xf |
ffddc436 | 1152 | #define DP_DSC_RECEIVER_CAP_SIZE 0xf |
52604b1f | 1153 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
4e382db3 | 1154 | #define EDP_DISPLAY_CTL_CAP_SIZE 3 |
52604b1f | 1155 | |
0aec2881 JN |
1156 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
1157 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); | |
1a644cd4 | 1158 | |
3b5c662e DV |
1159 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
1160 | int drm_dp_bw_code_to_link_rate(u8 link_bw); | |
1161 | ||
25a8ef26 VS |
1162 | #define DP_SDP_AUDIO_TIMESTAMP 0x01 |
1163 | #define DP_SDP_AUDIO_STREAM 0x02 | |
1164 | #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ | |
1165 | #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ | |
1166 | #define DP_SDP_ISRC 0x06 /* DP 1.2 */ | |
1167 | #define DP_SDP_VSC 0x07 /* DP 1.2 */ | |
1168 | #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ | |
1169 | #define DP_SDP_PPS 0x10 /* DP 1.4 */ | |
1170 | #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ | |
1171 | #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ | |
1172 | /* 0x80+ CEA-861 infoframe types */ | |
1173 | ||
05bad235 MN |
1174 | /** |
1175 | * struct dp_sdp_header - DP secondary data packet header | |
1176 | * @HB0: Secondary Data Packet ID | |
1177 | * @HB1: Secondary Data Packet Type | |
1178 | * @HB2: Secondary Data Packet Specific header, Byte 0 | |
1179 | * @HB3: Secondary Data packet Specific header, Byte 1 | |
1180 | */ | |
ebb513ad | 1181 | struct dp_sdp_header { |
05bad235 MN |
1182 | u8 HB0; |
1183 | u8 HB1; | |
1184 | u8 HB2; | |
1185 | u8 HB3; | |
52604b1f SK |
1186 | } __packed; |
1187 | ||
1188 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F | |
1189 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F | |
6e97272a | 1190 | #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F |
52604b1f | 1191 | |
4d432f95 GM |
1192 | /** |
1193 | * struct dp_sdp - DP secondary data packet | |
1194 | * @sdp_header: DP secondary data packet header | |
1195 | * @db: DP secondaray data packet data blocks | |
1196 | * VSC SDP Payload for PSR | |
1197 | * db[0]: Stereo Interface | |
1198 | * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid | |
1199 | * db[2]: CRC value bits 7:0 of the R or Cr component | |
1200 | * db[3]: CRC value bits 15:8 of the R or Cr component | |
1201 | * db[4]: CRC value bits 7:0 of the G or Y component | |
1202 | * db[5]: CRC value bits 15:8 of the G or Y component | |
1203 | * db[6]: CRC value bits 7:0 of the B or Cb component | |
1204 | * db[7]: CRC value bits 15:8 of the B or Cb component | |
1205 | * db[8] - db[31]: Reserved | |
1206 | * VSC SDP Payload for Pixel Encoding/Colorimetry Format | |
1207 | * db[0] - db[15]: Reserved | |
1208 | * db[16]: Pixel Encoding and Colorimetry Formats | |
1209 | * db[17]: Dynamic Range and Component Bit Depth | |
1210 | * db[18]: Content Type | |
1211 | * db[19] - db[31]: Reserved | |
1212 | */ | |
1213 | struct dp_sdp { | |
ebb513ad | 1214 | struct dp_sdp_header sdp_header; |
4d432f95 | 1215 | u8 db[32]; |
52604b1f SK |
1216 | } __packed; |
1217 | ||
1218 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) | |
1219 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) | |
1220 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) | |
1221 | ||
e2e4c4e1 GM |
1222 | /** |
1223 | * enum dp_pixelformat - drm DP Pixel encoding formats | |
1224 | * | |
1225 | * This enum is used to indicate DP VSC SDP Pixel encoding formats. | |
1226 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through | |
1227 | * DB18] | |
1228 | * | |
1229 | * @DP_PIXELFORMAT_RGB: RGB pixel encoding format | |
1230 | * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format | |
1231 | * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format | |
1232 | * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format | |
1233 | * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format | |
1234 | * @DP_PIXELFORMAT_RAW: RAW pixel encoding format | |
1235 | * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format | |
1236 | */ | |
1237 | enum dp_pixelformat { | |
1238 | DP_PIXELFORMAT_RGB = 0, | |
1239 | DP_PIXELFORMAT_YUV444 = 0x1, | |
1240 | DP_PIXELFORMAT_YUV422 = 0x2, | |
1241 | DP_PIXELFORMAT_YUV420 = 0x3, | |
1242 | DP_PIXELFORMAT_Y_ONLY = 0x4, | |
1243 | DP_PIXELFORMAT_RAW = 0x5, | |
1244 | DP_PIXELFORMAT_RESERVED = 0x6, | |
1245 | }; | |
1246 | ||
1247 | /** | |
1248 | * enum dp_colorimetry - drm DP Colorimetry formats | |
1249 | * | |
1250 | * This enum is used to indicate DP VSC SDP Colorimetry formats. | |
1251 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through | |
1252 | * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition. | |
1253 | * | |
1254 | * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or | |
1255 | * ITU-R BT.601 colorimetry format | |
1256 | * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format | |
1257 | * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format | |
1258 | * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point | |
1259 | * (scRGB (IEC 61966-2-2)) colorimetry format | |
1260 | * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format | |
1261 | * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format | |
1262 | * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format | |
1263 | * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format | |
1264 | * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format | |
1265 | * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format | |
1266 | * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format | |
1267 | * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format | |
1268 | * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format | |
1269 | * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format | |
1270 | */ | |
1271 | enum dp_colorimetry { | |
1272 | DP_COLORIMETRY_DEFAULT = 0, | |
1273 | DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, | |
1274 | DP_COLORIMETRY_BT709_YCC = 0x1, | |
1275 | DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, | |
1276 | DP_COLORIMETRY_XVYCC_601 = 0x2, | |
1277 | DP_COLORIMETRY_OPRGB = 0x3, | |
1278 | DP_COLORIMETRY_XVYCC_709 = 0x3, | |
1279 | DP_COLORIMETRY_DCI_P3_RGB = 0x4, | |
1280 | DP_COLORIMETRY_SYCC_601 = 0x4, | |
1281 | DP_COLORIMETRY_RGB_CUSTOM = 0x5, | |
1282 | DP_COLORIMETRY_OPYCC_601 = 0x5, | |
1283 | DP_COLORIMETRY_BT2020_RGB = 0x6, | |
1284 | DP_COLORIMETRY_BT2020_CYCC = 0x6, | |
1285 | DP_COLORIMETRY_BT2020_YCC = 0x7, | |
1286 | }; | |
1287 | ||
1288 | /** | |
1289 | * enum dp_dynamic_range - drm DP Dynamic Range | |
1290 | * | |
1291 | * This enum is used to indicate DP VSC SDP Dynamic Range. | |
1292 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through | |
1293 | * DB18] | |
1294 | * | |
1295 | * @DP_DYNAMIC_RANGE_VESA: VESA range | |
1296 | * @DP_DYNAMIC_RANGE_CTA: CTA range | |
1297 | */ | |
1298 | enum dp_dynamic_range { | |
1299 | DP_DYNAMIC_RANGE_VESA = 0, | |
1300 | DP_DYNAMIC_RANGE_CTA = 1, | |
1301 | }; | |
1302 | ||
1303 | /** | |
1304 | * enum dp_content_type - drm DP Content Type | |
1305 | * | |
1306 | * This enum is used to indicate DP VSC SDP Content Types. | |
1307 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through | |
1308 | * DB18] | |
1309 | * CTA-861-G defines content types and expected processing by a sink device | |
1310 | * | |
1311 | * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type | |
1312 | * @DP_CONTENT_TYPE_GRAPHICS: Graphics type | |
1313 | * @DP_CONTENT_TYPE_PHOTO: Photo type | |
1314 | * @DP_CONTENT_TYPE_VIDEO: Video type | |
1315 | * @DP_CONTENT_TYPE_GAME: Game type | |
1316 | */ | |
1317 | enum dp_content_type { | |
1318 | DP_CONTENT_TYPE_NOT_DEFINED = 0x00, | |
1319 | DP_CONTENT_TYPE_GRAPHICS = 0x01, | |
1320 | DP_CONTENT_TYPE_PHOTO = 0x02, | |
1321 | DP_CONTENT_TYPE_VIDEO = 0x03, | |
1322 | DP_CONTENT_TYPE_GAME = 0x04, | |
1323 | }; | |
1324 | ||
1325 | /** | |
1326 | * struct drm_dp_vsc_sdp - drm DP VSC SDP | |
1327 | * | |
1328 | * This structure represents a DP VSC SDP of drm | |
1329 | * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and | |
1330 | * [Table 2-117: VSC SDP Payload for DB16 through DB18] | |
1331 | * | |
1332 | * @sdp_type: secondary-data packet type | |
1333 | * @revision: revision number | |
1334 | * @length: number of valid data bytes | |
1335 | * @pixelformat: pixel encoding format | |
1336 | * @colorimetry: colorimetry format | |
1337 | * @bpc: bit per color | |
1338 | * @dynamic_range: dynamic range information | |
1339 | * @content_type: CTA-861-G defines content types and expected processing by a sink device | |
1340 | */ | |
1341 | struct drm_dp_vsc_sdp { | |
1342 | unsigned char sdp_type; | |
1343 | unsigned char revision; | |
1344 | unsigned char length; | |
1345 | enum dp_pixelformat pixelformat; | |
1346 | enum dp_colorimetry colorimetry; | |
1347 | int bpc; | |
1348 | enum dp_dynamic_range dynamic_range; | |
1349 | enum dp_content_type content_type; | |
1350 | }; | |
1351 | ||
2ba6221c GM |
1352 | void drm_dp_vsc_sdp_log(const char *level, struct device *dev, |
1353 | const struct drm_dp_vsc_sdp *vsc); | |
1354 | ||
6608804b VS |
1355 | int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); |
1356 | ||
3b5c662e | 1357 | static inline int |
0aec2881 | 1358 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3b5c662e DV |
1359 | { |
1360 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); | |
1361 | } | |
397fe157 DV |
1362 | |
1363 | static inline u8 | |
0aec2881 | 1364 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
397fe157 DV |
1365 | { |
1366 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; | |
1367 | } | |
1368 | ||
58704e6a JN |
1369 | static inline bool |
1370 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1371 | { | |
1372 | return dpcd[DP_DPCD_REV] >= 0x11 && | |
1373 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); | |
1374 | } | |
1375 | ||
8cda78b1 TR |
1376 | static inline bool |
1377 | drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1378 | { | |
1379 | return dpcd[DP_DPCD_REV] >= 0x11 && | |
1380 | (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); | |
1381 | } | |
1382 | ||
7cc53cf0 JN |
1383 | static inline bool |
1384 | drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1385 | { | |
1386 | return dpcd[DP_DPCD_REV] >= 0x12 && | |
1387 | dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; | |
1388 | } | |
1389 | ||
41d2f5fa MN |
1390 | static inline bool |
1391 | drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1392 | { | |
1393 | return dpcd[DP_DPCD_REV] >= 0x14 && | |
1394 | dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; | |
1395 | } | |
1396 | ||
1397 | static inline u8 | |
1398 | drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1399 | { | |
1400 | return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : | |
1401 | DP_TRAINING_PATTERN_MASK; | |
1402 | } | |
1403 | ||
c726ad01 ID |
1404 | static inline bool |
1405 | drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1406 | { | |
1407 | return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; | |
1408 | } | |
1409 | ||
05756500 MN |
1410 | /* DP/eDP DSC support */ |
1411 | u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], | |
1412 | bool is_edp); | |
1413 | u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); | |
4d4101c8 MN |
1414 | int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], |
1415 | u8 dsc_bpc[3]); | |
05756500 MN |
1416 | |
1417 | static inline bool | |
1418 | drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
1419 | { | |
1420 | return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & | |
1421 | DP_DSC_DECOMPRESSION_IS_SUPPORTED; | |
1422 | } | |
1423 | ||
1424 | static inline u16 | |
1425 | drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
1426 | { | |
1427 | return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | | |
1428 | (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & | |
1429 | DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << | |
1430 | DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); | |
1431 | } | |
1432 | ||
1433 | static inline u32 | |
1434 | drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
1435 | { | |
1436 | /* Max Slicewidth = Number of Pixels * 320 */ | |
1437 | return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * | |
1438 | DP_DSC_SLICE_WIDTH_MULTIPLIER; | |
1439 | } | |
1440 | ||
857d8283 AS |
1441 | /* Forward Error Correction Support on DP 1.4 */ |
1442 | static inline bool | |
1443 | drm_dp_sink_supports_fec(const u8 fec_capable) | |
1444 | { | |
1445 | return fec_capable & DP_FEC_CAPABLE; | |
1446 | } | |
1447 | ||
99c830b8 TR |
1448 | static inline bool |
1449 | drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1450 | { | |
1451 | return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; | |
1452 | } | |
1453 | ||
7624629d TR |
1454 | static inline bool |
1455 | drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1456 | { | |
1457 | return dpcd[DP_EDP_CONFIGURATION_CAP] & | |
1458 | DP_ALTERNATE_SCRAMBLER_RESET_CAP; | |
1459 | } | |
1460 | ||
24cfbec9 MN |
1461 | /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ |
1462 | static inline bool | |
1463 | drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
1464 | { | |
1465 | return dpcd[DP_DOWN_STREAM_PORT_COUNT] & | |
1466 | DP_MSA_TIMING_PAR_IGNORED; | |
1467 | } | |
1468 | ||
c197db75 TR |
1469 | /* |
1470 | * DisplayPort AUX channel | |
1471 | */ | |
1472 | ||
1473 | /** | |
1474 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction | |
1475 | * @address: address of the (first) register to access | |
1476 | * @request: contains the type of transaction (see DP_AUX_* macros) | |
1477 | * @reply: upon completion, contains the reply type of the transaction | |
1478 | * @buffer: pointer to a transmission or reception buffer | |
1479 | * @size: size of @buffer | |
1480 | */ | |
1481 | struct drm_dp_aux_msg { | |
1482 | unsigned int address; | |
1483 | u8 request; | |
1484 | u8 reply; | |
1485 | void *buffer; | |
1486 | size_t size; | |
1487 | }; | |
1488 | ||
2c6d1fff HV |
1489 | struct cec_adapter; |
1490 | struct edid; | |
ae85b0df | 1491 | struct drm_connector; |
2c6d1fff HV |
1492 | |
1493 | /** | |
1494 | * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX | |
1495 | * @lock: mutex protecting this struct | |
1496 | * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. | |
ae85b0df | 1497 | * @connector: the connector this CEC adapter is associated with |
2c6d1fff HV |
1498 | * @unregister_work: unregister the CEC adapter |
1499 | */ | |
1500 | struct drm_dp_aux_cec { | |
1501 | struct mutex lock; | |
1502 | struct cec_adapter *adap; | |
ae85b0df | 1503 | struct drm_connector *connector; |
2c6d1fff HV |
1504 | struct delayed_work unregister_work; |
1505 | }; | |
1506 | ||
c197db75 TR |
1507 | /** |
1508 | * struct drm_dp_aux - DisplayPort AUX channel | |
b8380580 | 1509 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
88759686 | 1510 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
c197db75 | 1511 | * @dev: pointer to struct device that is the parent for this AUX channel |
4bb310fd | 1512 | * @crtc: backpointer to the crtc that is currently using this AUX channel |
4f71d0cb | 1513 | * @hw_mutex: internal mutex used for locking transfers |
79c1da7c TV |
1514 | * @crc_work: worker that captures CRCs for each frame |
1515 | * @crc_count: counter of captured frame CRCs | |
c197db75 TR |
1516 | * @transfer: transfers a message representing a single AUX transaction |
1517 | * | |
1518 | * The .dev field should be set to a pointer to the device that implements | |
1519 | * the AUX channel. | |
1520 | * | |
9dc40560 JN |
1521 | * The .name field may be used to specify the name of the I2C adapter. If set to |
1522 | * NULL, dev_name() of .dev will be used. | |
1523 | * | |
c197db75 TR |
1524 | * Drivers provide a hardware-specific implementation of how transactions |
1525 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg | |
1526 | * structure describing the transaction is passed into this function. Upon | |
1527 | * success, the implementation should return the number of payload bytes | |
1528 | * that were transferred, or a negative error-code on failure. Helpers | |
1529 | * propagate errors from the .transfer() function, with the exception of | |
1530 | * the -EBUSY error, which causes a transaction to be retried. On a short, | |
1531 | * helpers will return -EPROTO to make it simpler to check for failure. | |
88759686 TR |
1532 | * |
1533 | * An AUX channel can also be used to transport I2C messages to a sink. A | |
1534 | * typical application of that is to access an EDID that's present in the | |
1535 | * sink device. The .transfer() function can also be used to execute such | |
6921f88b JH |
1536 | * transactions. The drm_dp_aux_register() function registers an I2C |
1537 | * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers | |
1538 | * should call drm_dp_aux_unregister() to remove the I2C adapter. | |
1d002fa7 SF |
1539 | * The I2C adapter uses long transfers by default; if a partial response is |
1540 | * received, the adapter will drop down to the size given by the partial | |
1541 | * response for this transaction only. | |
732d50b4 AD |
1542 | * |
1543 | * Note that the aux helper code assumes that the .transfer() function | |
1544 | * only modifies the reply field of the drm_dp_aux_msg structure. The | |
1545 | * retry logic and i2c helpers assume this is the case. | |
c197db75 TR |
1546 | */ |
1547 | struct drm_dp_aux { | |
9dc40560 | 1548 | const char *name; |
88759686 | 1549 | struct i2c_adapter ddc; |
c197db75 | 1550 | struct device *dev; |
4bb310fd | 1551 | struct drm_crtc *crtc; |
4f71d0cb | 1552 | struct mutex hw_mutex; |
79c1da7c TV |
1553 | struct work_struct crc_work; |
1554 | u8 crc_count; | |
c197db75 TR |
1555 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
1556 | struct drm_dp_aux_msg *msg); | |
212ae891 DV |
1557 | /** |
1558 | * @i2c_nack_count: Counts I2C NACKs, used for DP validation. | |
1559 | */ | |
1560 | unsigned i2c_nack_count; | |
1561 | /** | |
1562 | * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. | |
1563 | */ | |
1564 | unsigned i2c_defer_count; | |
2c6d1fff HV |
1565 | /** |
1566 | * @cec: struct containing fields used for CEC-Tunneling-over-AUX. | |
1567 | */ | |
1568 | struct drm_dp_aux_cec cec; | |
562836a2 VS |
1569 | /** |
1570 | * @is_remote: Is this AUX CH actually using sideband messaging. | |
1571 | */ | |
1572 | bool is_remote; | |
c197db75 TR |
1573 | }; |
1574 | ||
1575 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, | |
1576 | void *buffer, size_t size); | |
1577 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, | |
1578 | void *buffer, size_t size); | |
1579 | ||
1580 | /** | |
1581 | * drm_dp_dpcd_readb() - read a single byte from the DPCD | |
1582 | * @aux: DisplayPort AUX channel | |
1583 | * @offset: address of the register to read | |
1584 | * @valuep: location where the value of the register will be stored | |
1585 | * | |
1586 | * Returns the number of bytes transferred (1) on success, or a negative | |
1587 | * error code on failure. | |
1588 | */ | |
1589 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, | |
1590 | unsigned int offset, u8 *valuep) | |
1591 | { | |
1592 | return drm_dp_dpcd_read(aux, offset, valuep, 1); | |
1593 | } | |
1594 | ||
1595 | /** | |
1596 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD | |
1597 | * @aux: DisplayPort AUX channel | |
1598 | * @offset: address of the register to write | |
1599 | * @value: value to write to the register | |
1600 | * | |
1601 | * Returns the number of bytes transferred (1) on success, or a negative | |
1602 | * error code on failure. | |
1603 | */ | |
1604 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, | |
1605 | unsigned int offset, u8 value) | |
1606 | { | |
1607 | return drm_dp_dpcd_write(aux, offset, &value, 1); | |
1608 | } | |
1609 | ||
8d4adc6a TR |
1610 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
1611 | u8 status[DP_LINK_STATUS_SIZE]); | |
1612 | ||
e11f5bd8 JFZ |
1613 | bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, |
1614 | u8 real_edid_checksum); | |
1615 | ||
3d3721cc LP |
1616 | int drm_dp_read_downstream_info(struct drm_dp_aux *aux, |
1617 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
1618 | u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); | |
1c29bd3d MK |
1619 | int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
1620 | const u8 port_cap[4]); | |
7529d6af MK |
1621 | int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
1622 | const u8 port_cap[4]); | |
266d783b | 1623 | int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); |
80209e5f MK |
1624 | void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
1625 | const u8 port_cap[4], struct drm_dp_aux *aux); | |
e5b92773 OV |
1626 | enum drm_mode_subconnector |
1627 | drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
1628 | const u8 port_cap[4]); | |
1629 | void drm_dp_set_subconnector_property(struct drm_connector *connector, | |
1630 | enum drm_connector_status status, | |
1631 | const u8 *dpcd, | |
1632 | const u8 port_cap[4]); | |
516c0f7c | 1633 | |
693c3ec5 LP |
1634 | struct drm_dp_desc; |
1635 | bool drm_dp_read_sink_count_cap(struct drm_connector *connector, | |
1636 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
1637 | const struct drm_dp_desc *desc); | |
1638 | ||
c908b1c4 | 1639 | void drm_dp_remote_aux_init(struct drm_dp_aux *aux); |
acd8f414 | 1640 | void drm_dp_aux_init(struct drm_dp_aux *aux); |
4f71d0cb DA |
1641 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
1642 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); | |
88759686 | 1643 | |
79c1da7c TV |
1644 | int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); |
1645 | int drm_dp_stop_crc(struct drm_dp_aux *aux); | |
1646 | ||
118b90f3 JN |
1647 | struct drm_dp_dpcd_ident { |
1648 | u8 oui[3]; | |
1649 | u8 device_id[6]; | |
1650 | u8 hw_rev; | |
1651 | u8 sw_major_rev; | |
1652 | u8 sw_minor_rev; | |
1653 | } __packed; | |
1654 | ||
1655 | /** | |
1656 | * struct drm_dp_desc - DP branch/sink device descriptor | |
1657 | * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). | |
76fa998a | 1658 | * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. |
118b90f3 JN |
1659 | */ |
1660 | struct drm_dp_desc { | |
1661 | struct drm_dp_dpcd_ident ident; | |
76fa998a | 1662 | u32 quirks; |
118b90f3 JN |
1663 | }; |
1664 | ||
1665 | int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, | |
1666 | bool is_branch); | |
0883ce81 | 1667 | u32 drm_dp_get_edid_quirks(const struct edid *edid); |
118b90f3 | 1668 | |
76fa998a JN |
1669 | /** |
1670 | * enum drm_dp_quirk - Display Port sink/branch device specific quirks | |
1671 | * | |
1672 | * Display Port sink and branch devices in the wild have a variety of bugs, try | |
1673 | * to collect them here. The quirks are shared, but it's up to the drivers to | |
0883ce81 LP |
1674 | * implement workarounds for them. Note that because some devices have |
1675 | * unreliable OUIDs, the EDID of sinks should also be checked for quirks using | |
1676 | * drm_dp_get_edid_quirks(). | |
76fa998a JN |
1677 | */ |
1678 | enum drm_dp_quirk { | |
1679 | /** | |
53ca2edc | 1680 | * @DP_DPCD_QUIRK_CONSTANT_N: |
76fa998a JN |
1681 | * |
1682 | * The device requires main link attributes Mvid and Nvid to be limited | |
53ca2edc | 1683 | * to 16 bits. So will give a constant value (0x8000) for compatability. |
76fa998a | 1684 | */ |
53ca2edc | 1685 | DP_DPCD_QUIRK_CONSTANT_N, |
7c5c641a | 1686 | /** |
ed17b555 | 1687 | * @DP_DPCD_QUIRK_NO_PSR: |
7c5c641a JRS |
1688 | * |
1689 | * The device does not support PSR even if reports that it supports or | |
1690 | * driver still need to implement proper handling for such device. | |
1691 | */ | |
1692 | DP_DPCD_QUIRK_NO_PSR, | |
7974033e VS |
1693 | /** |
1694 | * @DP_DPCD_QUIRK_NO_SINK_COUNT: | |
1695 | * | |
1696 | * The device does not set SINK_COUNT to a non-zero value. | |
693c3ec5 LP |
1697 | * The driver should ignore SINK_COUNT during detection. Note that |
1698 | * drm_dp_read_sink_count_cap() automatically checks for this quirk. | |
7974033e VS |
1699 | */ |
1700 | DP_DPCD_QUIRK_NO_SINK_COUNT, | |
5b03f9d8 ML |
1701 | /** |
1702 | * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: | |
1703 | * | |
1704 | * The device supports MST DSC despite not supporting Virtual DPCD. | |
1705 | * The DSC caps can be read from the physical aux instead. | |
1706 | */ | |
1707 | DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, | |
17f5d579 LP |
1708 | /** |
1709 | * @DP_QUIRK_FORCE_DPCD_BACKLIGHT: | |
1710 | * | |
1711 | * The device is telling the truth when it says that it uses DPCD | |
1712 | * backlight controls, even if the system's firmware disagrees. This | |
1713 | * quirk should be checked against both the ident and panel EDID. | |
1714 | * When present, the driver should honor the DPCD backlight | |
1715 | * capabilities advertised. | |
1716 | */ | |
1717 | DP_QUIRK_FORCE_DPCD_BACKLIGHT, | |
639e0db2 MK |
1718 | /** |
1719 | * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: | |
1720 | * | |
1721 | * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite | |
1722 | * the DP_MAX_LINK_RATE register reporting a lower max multiplier. | |
1723 | */ | |
1724 | DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, | |
76fa998a JN |
1725 | }; |
1726 | ||
1727 | /** | |
1728 | * drm_dp_has_quirk() - does the DP device have a specific quirk | |
fedbfcc6 | 1729 | * @desc: Device descriptor filled by drm_dp_read_desc() |
0883ce81 | 1730 | * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks() |
76fa998a JN |
1731 | * @quirk: Quirk to query for |
1732 | * | |
1733 | * Return true if DP device identified by @desc has @quirk. | |
1734 | */ | |
1735 | static inline bool | |
0883ce81 LP |
1736 | drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks, |
1737 | enum drm_dp_quirk quirk) | |
76fa998a | 1738 | { |
0883ce81 | 1739 | return (desc->quirks | edid_quirks) & BIT(quirk); |
76fa998a JN |
1740 | } |
1741 | ||
2c6d1fff HV |
1742 | #ifdef CONFIG_DRM_DP_CEC |
1743 | void drm_dp_cec_irq(struct drm_dp_aux *aux); | |
ae85b0df DM |
1744 | void drm_dp_cec_register_connector(struct drm_dp_aux *aux, |
1745 | struct drm_connector *connector); | |
2c6d1fff HV |
1746 | void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); |
1747 | void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); | |
1748 | void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); | |
1749 | #else | |
1750 | static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) | |
1751 | { | |
1752 | } | |
1753 | ||
ae85b0df DM |
1754 | static inline void |
1755 | drm_dp_cec_register_connector(struct drm_dp_aux *aux, | |
1756 | struct drm_connector *connector) | |
2c6d1fff HV |
1757 | { |
1758 | } | |
1759 | ||
1760 | static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) | |
1761 | { | |
1762 | } | |
1763 | ||
1764 | static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, | |
1765 | const struct edid *edid) | |
1766 | { | |
1767 | } | |
1768 | ||
1769 | static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) | |
1770 | { | |
1771 | } | |
1772 | ||
1773 | #endif | |
1774 | ||
4342f839 AM |
1775 | /** |
1776 | * struct drm_dp_phy_test_params - DP Phy Compliance parameters | |
1777 | * @link_rate: Requested Link rate from DPCD 0x219 | |
1778 | * @num_lanes: Number of lanes requested by sing through DPCD 0x220 | |
1779 | * @phy_pattern: DP Phy test pattern from DPCD 0x248 | |
1780 | * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B | |
1781 | * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 | |
1782 | * @enhanced_frame_cap: flag for enhanced frame capability. | |
1783 | */ | |
1784 | struct drm_dp_phy_test_params { | |
1785 | int link_rate; | |
1786 | u8 num_lanes; | |
1787 | u8 phy_pattern; | |
1788 | u8 hbr2_reset[2]; | |
1789 | u8 custom80[10]; | |
1790 | bool enhanced_frame_cap; | |
1791 | }; | |
1792 | ||
1793 | int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, | |
1794 | struct drm_dp_phy_test_params *data); | |
1795 | int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, | |
1796 | struct drm_dp_phy_test_params *data, u8 dp_rev); | |
ab2c0672 | 1797 | #endif /* _DRM_DP_HELPER_H_ */ |