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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
ab2c0672 DA |
23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ | |
a4fc5ed6 | 25 | |
9f0e7ff4 JB |
26 | #include <linux/types.h> |
27 | #include <linux/i2c.h> | |
1a644cd4 | 28 | #include <linux/delay.h> |
9f0e7ff4 | 29 | |
a477f4fc AJ |
30 | /* |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that | |
32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, | |
33 | * 1.0 devices basically don't exist in the wild. | |
34 | * | |
35 | * Abbreviations, in chronological order: | |
36 | * | |
37 | * eDP: Embedded DisplayPort version 1 | |
38 | * DPI: DisplayPort Interoperability Guideline v1.1a | |
39 | * 1.2: DisplayPort 1.2 | |
3c8a0922 | 40 | * MST: Multistream Transport - part of DP 1.2a |
a477f4fc AJ |
41 | * |
42 | * 1.2 formally includes both eDP and DPI definitions. | |
43 | */ | |
a4fc5ed6 | 44 | |
1d002fa7 SF |
45 | #define DP_AUX_MAX_PAYLOAD_BYTES 16 |
46 | ||
6b27f7f0 TR |
47 | #define DP_AUX_I2C_WRITE 0x0 |
48 | #define DP_AUX_I2C_READ 0x1 | |
2b712be7 | 49 | #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 |
6b27f7f0 TR |
50 | #define DP_AUX_I2C_MOT 0x4 |
51 | #define DP_AUX_NATIVE_WRITE 0x8 | |
52 | #define DP_AUX_NATIVE_READ 0x9 | |
a4fc5ed6 | 53 | |
6b27f7f0 TR |
54 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
55 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) | |
56 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) | |
57 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) | |
a4fc5ed6 | 58 | |
6b27f7f0 TR |
59 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
60 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) | |
61 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) | |
62 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) | |
a4fc5ed6 KP |
63 | |
64 | /* AUX CH addresses */ | |
5801ead6 AD |
65 | /* DPCD */ |
66 | #define DP_DPCD_REV 0x000 | |
746c1aa4 | 67 | |
5801ead6 AD |
68 | #define DP_MAX_LINK_RATE 0x001 |
69 | ||
70 | #define DP_MAX_LANE_COUNT 0x002 | |
71 | # define DP_MAX_LANE_COUNT_MASK 0x1f | |
a477f4fc | 72 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
5801ead6 AD |
73 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
74 | ||
75 | #define DP_MAX_DOWNSPREAD 0x003 | |
56c5da00 | 76 | # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) |
5801ead6 AD |
77 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
78 | ||
79 | #define DP_NORP 0x004 | |
80 | ||
81 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 | |
82 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) | |
83 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 | |
3d2e423e JN |
84 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
85 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) | |
86 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) | |
87 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) | |
5801ead6 | 88 | # define DP_FORMAT_CONVERSION (1 << 3) |
a477f4fc | 89 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
5801ead6 AD |
90 | |
91 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 | |
92 | ||
de44d971 | 93 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
e89861df | 94 | # define DP_PORT_COUNT_MASK 0x0f |
a477f4fc | 95 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
e89861df AJ |
96 | # define DP_OUI_SUPPORT (1 << 7) |
97 | ||
9474675a JN |
98 | #define DP_RECEIVE_PORT_0_CAP_0 0x008 |
99 | # define DP_LOCAL_EDID_PRESENT (1 << 1) | |
100 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) | |
101 | ||
102 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 | |
103 | ||
104 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a | |
105 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b | |
106 | ||
a477f4fc | 107 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
e89861df AJ |
108 | # define DP_I2C_SPEED_1K 0x01 |
109 | # define DP_I2C_SPEED_5K 0x02 | |
110 | # define DP_I2C_SPEED_10K 0x04 | |
111 | # define DP_I2C_SPEED_100K 0x08 | |
112 | # define DP_I2C_SPEED_400K 0x10 | |
113 | # define DP_I2C_SPEED_1M 0x20 | |
de44d971 | 114 | |
a477f4fc | 115 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
9474675a JN |
116 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) |
117 | # define DP_FRAMING_CHANGE_CAP (1 << 1) | |
e045d20b | 118 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ |
bd5da992 | 119 | |
a477f4fc | 120 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
428c4b51 | 121 | |
9474675a JN |
122 | #define DP_ADAPTER_CAP 0x00f /* 1.2 */ |
123 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) | |
124 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) | |
125 | ||
bd5da992 JN |
126 | #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ |
127 | # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ | |
128 | ||
e89861df | 129 | /* Multiple stream transport */ |
3c8a0922 DA |
130 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
131 | # define DP_FAUX_CAP_1 (1 << 0) | |
132 | ||
a477f4fc | 133 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
e89861df AJ |
134 | # define DP_MST_CAP (1 << 0) |
135 | ||
9474675a JN |
136 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ |
137 | ||
138 | /* AV_SYNC_DATA_BLOCK 1.2 */ | |
139 | #define DP_AV_GRANULARITY 0x023 | |
140 | # define DP_AG_FACTOR_MASK (0xf << 0) | |
141 | # define DP_AG_FACTOR_3MS (0 << 0) | |
142 | # define DP_AG_FACTOR_2MS (1 << 0) | |
143 | # define DP_AG_FACTOR_1MS (2 << 0) | |
144 | # define DP_AG_FACTOR_500US (3 << 0) | |
145 | # define DP_AG_FACTOR_200US (4 << 0) | |
146 | # define DP_AG_FACTOR_100US (5 << 0) | |
147 | # define DP_AG_FACTOR_10US (6 << 0) | |
148 | # define DP_AG_FACTOR_1US (7 << 0) | |
149 | # define DP_VG_FACTOR_MASK (0xf << 4) | |
150 | # define DP_VG_FACTOR_3MS (0 << 4) | |
151 | # define DP_VG_FACTOR_2MS (1 << 4) | |
152 | # define DP_VG_FACTOR_1MS (2 << 4) | |
153 | # define DP_VG_FACTOR_500US (3 << 4) | |
154 | # define DP_VG_FACTOR_200US (4 << 4) | |
155 | # define DP_VG_FACTOR_100US (5 << 4) | |
156 | ||
157 | #define DP_AUD_DEC_LAT0 0x024 | |
158 | #define DP_AUD_DEC_LAT1 0x025 | |
159 | ||
160 | #define DP_AUD_PP_LAT0 0x026 | |
161 | #define DP_AUD_PP_LAT1 0x027 | |
162 | ||
163 | #define DP_VID_INTER_LAT 0x028 | |
164 | ||
165 | #define DP_VID_PROG_LAT 0x029 | |
166 | ||
167 | #define DP_REP_LAT 0x02a | |
168 | ||
169 | #define DP_AUD_DEL_INS0 0x02b | |
170 | #define DP_AUD_DEL_INS1 0x02c | |
171 | #define DP_AUD_DEL_INS2 0x02d | |
172 | /* End of AV_SYNC_DATA_BLOCK */ | |
173 | ||
6b1e3f61 JN |
174 | #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ |
175 | # define DP_ALPM_CAP (1 << 0) | |
176 | ||
177 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ | |
178 | # define DP_AUX_FRAME_SYNC_CAP (1 << 0) | |
179 | ||
3c8a0922 DA |
180 | #define DP_GUID 0x030 /* 1.2 */ |
181 | ||
a477f4fc | 182 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
b73fe58c | 183 | # define DP_PSR_IS_SUPPORTED 1 |
6b1e3f61 JN |
184 | # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ |
185 | ||
a477f4fc | 186 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
b73fe58c BW |
187 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
188 | # define DP_PSR_SETUP_TIME_330 (0 << 1) | |
189 | # define DP_PSR_SETUP_TIME_275 (1 << 1) | |
190 | # define DP_PSR_SETUP_TIME_220 (2 << 1) | |
191 | # define DP_PSR_SETUP_TIME_165 (3 << 1) | |
192 | # define DP_PSR_SETUP_TIME_110 (4 << 1) | |
193 | # define DP_PSR_SETUP_TIME_55 (5 << 1) | |
194 | # define DP_PSR_SETUP_TIME_0 (6 << 1) | |
195 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) | |
196 | # define DP_PSR_SETUP_TIME_SHIFT 1 | |
197 | ||
e89861df AJ |
198 | /* |
199 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts | |
200 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, | |
201 | * each port's descriptor is one byte wide. If it was set, each port's is | |
202 | * four bytes wide, starting with the one byte from the base info. As of | |
203 | * DP interop v1.1a only VGA defines additional detail. | |
204 | */ | |
205 | ||
206 | /* offset 0 */ | |
207 | #define DP_DOWNSTREAM_PORT_0 0x80 | |
208 | # define DP_DS_PORT_TYPE_MASK (7 << 0) | |
209 | # define DP_DS_PORT_TYPE_DP 0 | |
210 | # define DP_DS_PORT_TYPE_VGA 1 | |
211 | # define DP_DS_PORT_TYPE_DVI 2 | |
212 | # define DP_DS_PORT_TYPE_HDMI 3 | |
213 | # define DP_DS_PORT_TYPE_NON_EDID 4 | |
69b1e00f MK |
214 | # define DP_DS_PORT_TYPE_DP_DUALMODE 5 |
215 | # define DP_DS_PORT_TYPE_WIRELESS 6 | |
e89861df AJ |
216 | # define DP_DS_PORT_HPD (1 << 3) |
217 | /* offset 1 for VGA is maximum megapixels per second / 8 */ | |
218 | /* offset 2 */ | |
8fedf080 MK |
219 | # define DP_DS_MAX_BPC_MASK (3 << 0) |
220 | # define DP_DS_8BPC 0 | |
221 | # define DP_DS_10BPC 1 | |
222 | # define DP_DS_12BPC 2 | |
223 | # define DP_DS_16BPC 3 | |
e89861df | 224 | |
5801ead6 AD |
225 | /* link configuration */ |
226 | #define DP_LINK_BW_SET 0x100 | |
6b1e3f61 | 227 | # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ |
a4fc5ed6 KP |
228 | # define DP_LINK_BW_1_62 0x06 |
229 | # define DP_LINK_BW_2_7 0x0a | |
a477f4fc | 230 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
a4fc5ed6 | 231 | |
5801ead6 | 232 | #define DP_LANE_COUNT_SET 0x101 |
a4fc5ed6 KP |
233 | # define DP_LANE_COUNT_MASK 0x0f |
234 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) | |
235 | ||
5801ead6 | 236 | #define DP_TRAINING_PATTERN_SET 0x102 |
a4fc5ed6 KP |
237 | # define DP_TRAINING_PATTERN_DISABLE 0 |
238 | # define DP_TRAINING_PATTERN_1 1 | |
239 | # define DP_TRAINING_PATTERN_2 2 | |
a477f4fc | 240 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
a4fc5ed6 KP |
241 | # define DP_TRAINING_PATTERN_MASK 0x3 |
242 | ||
9474675a JN |
243 | /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ |
244 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) | |
245 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) | |
246 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) | |
247 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) | |
248 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) | |
a4fc5ed6 KP |
249 | |
250 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) | |
251 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) | |
252 | ||
253 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) | |
254 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) | |
255 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) | |
256 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) | |
257 | ||
258 | #define DP_TRAINING_LANE0_SET 0x103 | |
259 | #define DP_TRAINING_LANE1_SET 0x104 | |
260 | #define DP_TRAINING_LANE2_SET 0x105 | |
261 | #define DP_TRAINING_LANE3_SET 0x106 | |
262 | ||
263 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 | |
264 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 | |
265 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) | |
0504cd17 | 266 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
0504cd17 | 267 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
0504cd17 | 268 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
0504cd17 | 269 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
a4fc5ed6 KP |
270 | |
271 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) | |
0504cd17 | 272 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
0504cd17 | 273 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
0504cd17 | 274 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
0504cd17 | 275 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
a4fc5ed6 KP |
276 | |
277 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 | |
278 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) | |
279 | ||
280 | #define DP_DOWNSPREAD_CTRL 0x107 | |
281 | # define DP_SPREAD_AMP_0_5 (1 << 4) | |
a477f4fc | 282 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
a4fc5ed6 KP |
283 | |
284 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 | |
285 | # define DP_SET_ANSI_8B10B (1 << 0) | |
286 | ||
a477f4fc | 287 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
e89861df AJ |
288 | /* bitmask as for DP_I2C_SPEED_CAP */ |
289 | ||
a477f4fc | 290 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
9474675a JN |
291 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) |
292 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1) | |
293 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) | |
294 | ||
295 | #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ | |
296 | #define DP_LINK_QUAL_LANE1_SET 0x10c | |
297 | #define DP_LINK_QUAL_LANE2_SET 0x10d | |
298 | #define DP_LINK_QUAL_LANE3_SET 0x10e | |
299 | # define DP_LINK_QUAL_PATTERN_DISABLE 0 | |
300 | # define DP_LINK_QUAL_PATTERN_D10_2 1 | |
301 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 | |
302 | # define DP_LINK_QUAL_PATTERN_PRBS7 3 | |
303 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 | |
304 | # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 | |
305 | # define DP_LINK_QUAL_PATTERN_MASK 7 | |
306 | ||
307 | #define DP_TRAINING_LANE0_1_SET2 0x10f | |
308 | #define DP_TRAINING_LANE2_3_SET2 0x110 | |
309 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) | |
310 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) | |
311 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) | |
312 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) | |
e89861df | 313 | |
a477f4fc | 314 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
e89861df AJ |
315 | # define DP_MST_EN (1 << 0) |
316 | # define DP_UP_REQ_EN (1 << 1) | |
317 | # define DP_UPSTREAM_IS_SRC (1 << 2) | |
318 | ||
9474675a JN |
319 | #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ |
320 | #define DP_AUDIO_DELAY1 0x113 | |
321 | #define DP_AUDIO_DELAY2 0x114 | |
322 | ||
bd5da992 | 323 | #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ |
6b1e3f61 JN |
324 | # define DP_LINK_RATE_SET_SHIFT 0 |
325 | # define DP_LINK_RATE_SET_MASK (7 << 0) | |
326 | ||
327 | #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ | |
328 | # define DP_ALPM_ENABLE (1 << 0) | |
329 | # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) | |
330 | ||
331 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ | |
332 | # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) | |
333 | # define DP_IRQ_HPD_ENABLE (1 << 1) | |
e045d20b | 334 | |
9474675a JN |
335 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ |
336 | # define DP_PWR_NOT_NEEDED (1 << 0) | |
337 | ||
6b1e3f61 JN |
338 | #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ |
339 | # define DP_AUX_FRAME_SYNC_VALID (1 << 0) | |
340 | ||
a477f4fc | 341 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
b73fe58c BW |
342 | # define DP_PSR_ENABLE (1 << 0) |
343 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) | |
344 | # define DP_PSR_CRC_VERIFICATION (1 << 2) | |
345 | # define DP_PSR_FRAME_CAPTURE (1 << 3) | |
6b1e3f61 JN |
346 | # define DP_PSR_SELECTIVE_UPDATE (1 << 4) |
347 | # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) | |
b73fe58c | 348 | |
3c8a0922 DA |
349 | #define DP_ADAPTER_CTRL 0x1a0 |
350 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) | |
351 | ||
352 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 | |
353 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) | |
354 | ||
355 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 | |
356 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 | |
357 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 | |
358 | ||
e89861df | 359 | #define DP_SINK_COUNT 0x200 |
da131a46 AJ |
360 | /* prior to 1.2 bit 7 was reserved mbz */ |
361 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) | |
e89861df AJ |
362 | # define DP_SINK_CP_READY (1 << 6) |
363 | ||
a60f0e38 JB |
364 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
365 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) | |
366 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) | |
367 | # define DP_CP_IRQ (1 << 2) | |
3c8a0922 DA |
368 | # define DP_MCCS_IRQ (1 << 3) |
369 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ | |
370 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ | |
a60f0e38 JB |
371 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
372 | ||
a4fc5ed6 KP |
373 | #define DP_LANE0_1_STATUS 0x202 |
374 | #define DP_LANE2_3_STATUS 0x203 | |
a4fc5ed6 KP |
375 | # define DP_LANE_CR_DONE (1 << 0) |
376 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) | |
377 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) | |
378 | ||
5801ead6 AD |
379 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
380 | DP_LANE_CHANNEL_EQ_DONE | \ | |
381 | DP_LANE_SYMBOL_LOCKED) | |
382 | ||
a4fc5ed6 KP |
383 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
384 | ||
385 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) | |
386 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) | |
387 | #define DP_LINK_STATUS_UPDATED (1 << 7) | |
388 | ||
389 | #define DP_SINK_STATUS 0x205 | |
390 | ||
391 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) | |
392 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) | |
393 | ||
394 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 | |
395 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 | |
5801ead6 AD |
396 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
397 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 | |
398 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c | |
399 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 | |
400 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 | |
401 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 | |
402 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 | |
403 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 | |
a4fc5ed6 | 404 | |
a60f0e38 JB |
405 | #define DP_TEST_REQUEST 0x218 |
406 | # define DP_TEST_LINK_TRAINING (1 << 0) | |
fe3c703c | 407 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
a60f0e38 JB |
408 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
409 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ | |
fe3c703c | 410 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
a60f0e38 JB |
411 | |
412 | #define DP_TEST_LINK_RATE 0x219 | |
413 | # define DP_LINK_RATE_162 (0x6) | |
414 | # define DP_LINK_RATE_27 (0xa) | |
415 | ||
416 | #define DP_TEST_LANE_COUNT 0x220 | |
417 | ||
418 | #define DP_TEST_PATTERN 0x221 | |
419 | ||
a25eebb0 RV |
420 | #define DP_TEST_CRC_R_CR 0x240 |
421 | #define DP_TEST_CRC_G_Y 0x242 | |
422 | #define DP_TEST_CRC_B_CB 0x244 | |
423 | ||
424 | #define DP_TEST_SINK_MISC 0x246 | |
ad9dc91b | 425 | # define DP_TEST_CRC_SUPPORTED (1 << 5) |
90a21700 | 426 | # define DP_TEST_COUNT_MASK 0xf |
a25eebb0 | 427 | |
a60f0e38 JB |
428 | #define DP_TEST_RESPONSE 0x260 |
429 | # define DP_TEST_ACK (1 << 0) | |
430 | # define DP_TEST_NAK (1 << 1) | |
431 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) | |
432 | ||
073ea2ae JH |
433 | #define DP_TEST_EDID_CHECKSUM 0x261 |
434 | ||
a25eebb0 | 435 | #define DP_TEST_SINK 0x270 |
ad9dc91b | 436 | # define DP_TEST_SINK_START (1 << 0) |
a25eebb0 | 437 | |
3c8a0922 DA |
438 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
439 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) | |
440 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) | |
441 | ||
442 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ | |
443 | /* up to ID_SLOT_63 at 0x2ff */ | |
444 | ||
86c3c3be AJ |
445 | #define DP_SOURCE_OUI 0x300 |
446 | #define DP_SINK_OUI 0x400 | |
447 | #define DP_BRANCH_OUI 0x500 | |
448 | ||
1a66c95a | 449 | #define DP_SET_POWER 0x600 |
5801ead6 AD |
450 | # define DP_SET_POWER_D0 0x1 |
451 | # define DP_SET_POWER_D3 0x2 | |
516c0f7c | 452 | # define DP_SET_POWER_MASK 0x3 |
1a66c95a | 453 | |
bd5da992 | 454 | #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ |
6b1e3f61 JN |
455 | # define DP_EDP_11 0x00 |
456 | # define DP_EDP_12 0x01 | |
457 | # define DP_EDP_13 0x02 | |
458 | # define DP_EDP_14 0x03 | |
e045d20b | 459 | |
0e71244c | 460 | #define DP_EDP_GENERAL_CAP_1 0x701 |
36af4ca7 JN |
461 | # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) |
462 | # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) | |
463 | # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) | |
464 | # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) | |
465 | # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) | |
466 | # define DP_EDP_FRC_ENABLE_CAP (1 << 5) | |
467 | # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) | |
468 | # define DP_EDP_SET_POWER_CAP (1 << 7) | |
0e71244c JN |
469 | |
470 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 | |
36af4ca7 JN |
471 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) |
472 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) | |
473 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) | |
474 | # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) | |
475 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) | |
476 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) | |
477 | # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) | |
478 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) | |
0e71244c JN |
479 | |
480 | #define DP_EDP_GENERAL_CAP_2 0x703 | |
36af4ca7 | 481 | # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) |
0e71244c | 482 | |
6b1e3f61 | 483 | #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ |
36af4ca7 JN |
484 | # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) |
485 | # define DP_EDP_X_REGION_CAP_SHIFT 0 | |
486 | # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) | |
487 | # define DP_EDP_Y_REGION_CAP_SHIFT 4 | |
6b1e3f61 | 488 | |
0e71244c | 489 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 |
36af4ca7 JN |
490 | # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) |
491 | # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) | |
492 | # define DP_EDP_FRC_ENABLE (1 << 2) | |
493 | # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) | |
494 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) | |
0e71244c JN |
495 | |
496 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 | |
36af4ca7 JN |
497 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) |
498 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) | |
499 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) | |
500 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) | |
501 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) | |
502 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) | |
503 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) | |
504 | # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) | |
505 | # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) | |
506 | # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ | |
0e71244c JN |
507 | |
508 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 | |
509 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 | |
510 | ||
511 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724 | |
512 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 | |
513 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 | |
514 | ||
515 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 | |
516 | ||
517 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 | |
518 | ||
519 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a | |
520 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b | |
521 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c | |
522 | ||
523 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d | |
524 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e | |
525 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f | |
526 | ||
527 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 | |
528 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 | |
529 | ||
6b1e3f61 JN |
530 | #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ |
531 | #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ | |
532 | ||
3c8a0922 DA |
533 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
534 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ | |
535 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ | |
536 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ | |
537 | ||
538 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ | |
539 | /* 0-5 sink count */ | |
540 | # define DP_SINK_COUNT_CP_READY (1 << 6) | |
541 | ||
542 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ | |
543 | ||
544 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ | |
545 | ||
546 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ | |
547 | ||
a477f4fc | 548 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
b73fe58c BW |
549 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
550 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) | |
6b1e3f61 | 551 | # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ |
b73fe58c | 552 | |
a477f4fc | 553 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
b73fe58c BW |
554 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
555 | ||
a477f4fc | 556 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
b73fe58c BW |
557 | # define DP_PSR_SINK_INACTIVE 0 |
558 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 | |
559 | # define DP_PSR_SINK_ACTIVE_RFB 2 | |
560 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 | |
561 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 | |
562 | # define DP_PSR_SINK_INTERNAL_ERROR 7 | |
563 | # define DP_PSR_SINK_STATE_MASK 0x07 | |
564 | ||
6b1e3f61 JN |
565 | #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ |
566 | # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) | |
567 | ||
3c8a0922 DA |
568 | /* DP 1.2 Sideband message defines */ |
569 | /* peer device type - DP 1.2a Table 2-92 */ | |
570 | #define DP_PEER_DEVICE_NONE 0x0 | |
571 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 | |
572 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 | |
573 | #define DP_PEER_DEVICE_SST_SINK 0x3 | |
574 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 | |
575 | ||
576 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ | |
577 | #define DP_LINK_ADDRESS 0x01 | |
578 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 | |
579 | #define DP_ENUM_PATH_RESOURCES 0x10 | |
580 | #define DP_ALLOCATE_PAYLOAD 0x11 | |
581 | #define DP_QUERY_PAYLOAD 0x12 | |
582 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 | |
583 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 | |
584 | #define DP_REMOTE_DPCD_READ 0x20 | |
585 | #define DP_REMOTE_DPCD_WRITE 0x21 | |
586 | #define DP_REMOTE_I2C_READ 0x22 | |
587 | #define DP_REMOTE_I2C_WRITE 0x23 | |
588 | #define DP_POWER_UP_PHY 0x24 | |
589 | #define DP_POWER_DOWN_PHY 0x25 | |
590 | #define DP_SINK_EVENT_NOTIFY 0x30 | |
591 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 | |
592 | ||
593 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ | |
594 | #define DP_NAK_WRITE_FAILURE 0x01 | |
595 | #define DP_NAK_INVALID_READ 0x02 | |
596 | #define DP_NAK_CRC_FAILURE 0x03 | |
597 | #define DP_NAK_BAD_PARAM 0x04 | |
598 | #define DP_NAK_DEFER 0x05 | |
599 | #define DP_NAK_LINK_FAILURE 0x06 | |
600 | #define DP_NAK_NO_RESOURCES 0x07 | |
601 | #define DP_NAK_DPCD_FAIL 0x08 | |
602 | #define DP_NAK_I2C_NAK 0x09 | |
603 | #define DP_NAK_ALLOCATE_FAIL 0x0a | |
604 | ||
ab2c0672 DA |
605 | #define MODE_I2C_START 1 |
606 | #define MODE_I2C_WRITE 2 | |
607 | #define MODE_I2C_READ 4 | |
608 | #define MODE_I2C_STOP 8 | |
609 | ||
ccf03d69 DA |
610 | /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ |
611 | #define DP_MST_PHYSICAL_PORT_0 0 | |
612 | #define DP_MST_LOGICAL_PORT_0 8 | |
613 | ||
1ffdff13 | 614 | #define DP_LINK_STATUS_SIZE 6 |
0aec2881 | 615 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 | 616 | int lane_count); |
0aec2881 | 617 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
01916270 | 618 | int lane_count); |
0aec2881 | 619 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 620 | int lane); |
0aec2881 | 621 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 622 | int lane); |
1ffdff13 | 623 | |
44790462 | 624 | #define DP_BRANCH_OUI_HEADER_SIZE 0xc |
52604b1f SK |
625 | #define DP_RECEIVER_CAP_SIZE 0xf |
626 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 | |
4e382db3 | 627 | #define EDP_DISPLAY_CTL_CAP_SIZE 3 |
52604b1f | 628 | |
0aec2881 JN |
629 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
630 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); | |
1a644cd4 | 631 | |
3b5c662e DV |
632 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
633 | int drm_dp_bw_code_to_link_rate(u8 link_bw); | |
634 | ||
52604b1f SK |
635 | struct edp_sdp_header { |
636 | u8 HB0; /* Secondary Data Packet ID */ | |
637 | u8 HB1; /* Secondary Data Packet Type */ | |
638 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ | |
639 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ | |
640 | } __packed; | |
641 | ||
642 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F | |
643 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F | |
644 | ||
645 | struct edp_vsc_psr { | |
646 | struct edp_sdp_header sdp_header; | |
647 | u8 DB0; /* Stereo Interface */ | |
648 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ | |
649 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ | |
650 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ | |
651 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ | |
652 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ | |
653 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ | |
654 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ | |
655 | u8 DB8_31[24]; /* Reserved */ | |
656 | } __packed; | |
657 | ||
658 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) | |
659 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) | |
660 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) | |
661 | ||
6608804b VS |
662 | int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); |
663 | ||
3b5c662e | 664 | static inline int |
0aec2881 | 665 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3b5c662e DV |
666 | { |
667 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); | |
668 | } | |
397fe157 DV |
669 | |
670 | static inline u8 | |
0aec2881 | 671 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
397fe157 DV |
672 | { |
673 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; | |
674 | } | |
675 | ||
58704e6a JN |
676 | static inline bool |
677 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
678 | { | |
679 | return dpcd[DP_DPCD_REV] >= 0x11 && | |
680 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); | |
681 | } | |
682 | ||
7cc53cf0 JN |
683 | static inline bool |
684 | drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
685 | { | |
686 | return dpcd[DP_DPCD_REV] >= 0x12 && | |
687 | dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; | |
688 | } | |
689 | ||
c197db75 TR |
690 | /* |
691 | * DisplayPort AUX channel | |
692 | */ | |
693 | ||
694 | /** | |
695 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction | |
696 | * @address: address of the (first) register to access | |
697 | * @request: contains the type of transaction (see DP_AUX_* macros) | |
698 | * @reply: upon completion, contains the reply type of the transaction | |
699 | * @buffer: pointer to a transmission or reception buffer | |
700 | * @size: size of @buffer | |
701 | */ | |
702 | struct drm_dp_aux_msg { | |
703 | unsigned int address; | |
704 | u8 request; | |
705 | u8 reply; | |
706 | void *buffer; | |
707 | size_t size; | |
708 | }; | |
709 | ||
710 | /** | |
711 | * struct drm_dp_aux - DisplayPort AUX channel | |
b8380580 | 712 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
88759686 | 713 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
c197db75 | 714 | * @dev: pointer to struct device that is the parent for this AUX channel |
4f71d0cb | 715 | * @hw_mutex: internal mutex used for locking transfers |
c197db75 TR |
716 | * @transfer: transfers a message representing a single AUX transaction |
717 | * | |
718 | * The .dev field should be set to a pointer to the device that implements | |
719 | * the AUX channel. | |
720 | * | |
9dc40560 JN |
721 | * The .name field may be used to specify the name of the I2C adapter. If set to |
722 | * NULL, dev_name() of .dev will be used. | |
723 | * | |
c197db75 TR |
724 | * Drivers provide a hardware-specific implementation of how transactions |
725 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg | |
726 | * structure describing the transaction is passed into this function. Upon | |
727 | * success, the implementation should return the number of payload bytes | |
728 | * that were transferred, or a negative error-code on failure. Helpers | |
729 | * propagate errors from the .transfer() function, with the exception of | |
730 | * the -EBUSY error, which causes a transaction to be retried. On a short, | |
731 | * helpers will return -EPROTO to make it simpler to check for failure. | |
88759686 TR |
732 | * |
733 | * An AUX channel can also be used to transport I2C messages to a sink. A | |
734 | * typical application of that is to access an EDID that's present in the | |
735 | * sink device. The .transfer() function can also be used to execute such | |
6921f88b JH |
736 | * transactions. The drm_dp_aux_register() function registers an I2C |
737 | * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers | |
738 | * should call drm_dp_aux_unregister() to remove the I2C adapter. | |
1d002fa7 SF |
739 | * The I2C adapter uses long transfers by default; if a partial response is |
740 | * received, the adapter will drop down to the size given by the partial | |
741 | * response for this transaction only. | |
732d50b4 AD |
742 | * |
743 | * Note that the aux helper code assumes that the .transfer() function | |
744 | * only modifies the reply field of the drm_dp_aux_msg structure. The | |
745 | * retry logic and i2c helpers assume this is the case. | |
c197db75 TR |
746 | */ |
747 | struct drm_dp_aux { | |
9dc40560 | 748 | const char *name; |
88759686 | 749 | struct i2c_adapter ddc; |
c197db75 | 750 | struct device *dev; |
4f71d0cb | 751 | struct mutex hw_mutex; |
c197db75 TR |
752 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
753 | struct drm_dp_aux_msg *msg); | |
212ae891 DV |
754 | /** |
755 | * @i2c_nack_count: Counts I2C NACKs, used for DP validation. | |
756 | */ | |
757 | unsigned i2c_nack_count; | |
758 | /** | |
759 | * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. | |
760 | */ | |
761 | unsigned i2c_defer_count; | |
c197db75 TR |
762 | }; |
763 | ||
764 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, | |
765 | void *buffer, size_t size); | |
766 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, | |
767 | void *buffer, size_t size); | |
768 | ||
769 | /** | |
770 | * drm_dp_dpcd_readb() - read a single byte from the DPCD | |
771 | * @aux: DisplayPort AUX channel | |
772 | * @offset: address of the register to read | |
773 | * @valuep: location where the value of the register will be stored | |
774 | * | |
775 | * Returns the number of bytes transferred (1) on success, or a negative | |
776 | * error code on failure. | |
777 | */ | |
778 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, | |
779 | unsigned int offset, u8 *valuep) | |
780 | { | |
781 | return drm_dp_dpcd_read(aux, offset, valuep, 1); | |
782 | } | |
783 | ||
784 | /** | |
785 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD | |
786 | * @aux: DisplayPort AUX channel | |
787 | * @offset: address of the register to write | |
788 | * @value: value to write to the register | |
789 | * | |
790 | * Returns the number of bytes transferred (1) on success, or a negative | |
791 | * error code on failure. | |
792 | */ | |
793 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, | |
794 | unsigned int offset, u8 value) | |
795 | { | |
796 | return drm_dp_dpcd_write(aux, offset, &value, 1); | |
797 | } | |
798 | ||
8d4adc6a TR |
799 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
800 | u8 status[DP_LINK_STATUS_SIZE]); | |
801 | ||
516c0f7c TR |
802 | /* |
803 | * DisplayPort link | |
804 | */ | |
805 | #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) | |
806 | ||
807 | struct drm_dp_link { | |
808 | unsigned char revision; | |
809 | unsigned int rate; | |
810 | unsigned int num_lanes; | |
811 | unsigned long capabilities; | |
812 | }; | |
813 | ||
814 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); | |
815 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); | |
d816f077 | 816 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); |
516c0f7c TR |
817 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); |
818 | ||
acd8f414 | 819 | void drm_dp_aux_init(struct drm_dp_aux *aux); |
4f71d0cb DA |
820 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
821 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); | |
88759686 | 822 | |
ab2c0672 | 823 | #endif /* _DRM_DP_HELPER_H_ */ |