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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
ab2c0672 DA |
23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ | |
a4fc5ed6 | 25 | |
9f0e7ff4 JB |
26 | #include <linux/types.h> |
27 | #include <linux/i2c.h> | |
1a644cd4 | 28 | #include <linux/delay.h> |
9f0e7ff4 | 29 | |
a477f4fc AJ |
30 | /* |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that | |
32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, | |
33 | * 1.0 devices basically don't exist in the wild. | |
34 | * | |
35 | * Abbreviations, in chronological order: | |
36 | * | |
37 | * eDP: Embedded DisplayPort version 1 | |
38 | * DPI: DisplayPort Interoperability Guideline v1.1a | |
39 | * 1.2: DisplayPort 1.2 | |
3c8a0922 | 40 | * MST: Multistream Transport - part of DP 1.2a |
a477f4fc AJ |
41 | * |
42 | * 1.2 formally includes both eDP and DPI definitions. | |
43 | */ | |
a4fc5ed6 | 44 | |
6b27f7f0 TR |
45 | #define DP_AUX_I2C_WRITE 0x0 |
46 | #define DP_AUX_I2C_READ 0x1 | |
47 | #define DP_AUX_I2C_STATUS 0x2 | |
48 | #define DP_AUX_I2C_MOT 0x4 | |
49 | #define DP_AUX_NATIVE_WRITE 0x8 | |
50 | #define DP_AUX_NATIVE_READ 0x9 | |
a4fc5ed6 | 51 | |
6b27f7f0 TR |
52 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
53 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) | |
54 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) | |
55 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) | |
a4fc5ed6 | 56 | |
6b27f7f0 TR |
57 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
58 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) | |
59 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) | |
60 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) | |
a4fc5ed6 KP |
61 | |
62 | /* AUX CH addresses */ | |
5801ead6 AD |
63 | /* DPCD */ |
64 | #define DP_DPCD_REV 0x000 | |
746c1aa4 | 65 | |
5801ead6 AD |
66 | #define DP_MAX_LINK_RATE 0x001 |
67 | ||
68 | #define DP_MAX_LANE_COUNT 0x002 | |
69 | # define DP_MAX_LANE_COUNT_MASK 0x1f | |
a477f4fc | 70 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
5801ead6 AD |
71 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
72 | ||
73 | #define DP_MAX_DOWNSPREAD 0x003 | |
74 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) | |
75 | ||
76 | #define DP_NORP 0x004 | |
77 | ||
78 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 | |
79 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) | |
80 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 | |
3d2e423e JN |
81 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
82 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) | |
83 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) | |
84 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) | |
5801ead6 | 85 | # define DP_FORMAT_CONVERSION (1 << 3) |
a477f4fc | 86 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
5801ead6 AD |
87 | |
88 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 | |
89 | ||
de44d971 | 90 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
e89861df | 91 | # define DP_PORT_COUNT_MASK 0x0f |
a477f4fc | 92 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
e89861df AJ |
93 | # define DP_OUI_SUPPORT (1 << 7) |
94 | ||
9474675a JN |
95 | #define DP_RECEIVE_PORT_0_CAP_0 0x008 |
96 | # define DP_LOCAL_EDID_PRESENT (1 << 1) | |
97 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) | |
98 | ||
99 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 | |
100 | ||
101 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a | |
102 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b | |
103 | ||
a477f4fc | 104 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
e89861df AJ |
105 | # define DP_I2C_SPEED_1K 0x01 |
106 | # define DP_I2C_SPEED_5K 0x02 | |
107 | # define DP_I2C_SPEED_10K 0x04 | |
108 | # define DP_I2C_SPEED_100K 0x08 | |
109 | # define DP_I2C_SPEED_400K 0x10 | |
110 | # define DP_I2C_SPEED_1M 0x20 | |
de44d971 | 111 | |
a477f4fc | 112 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
9474675a JN |
113 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) |
114 | # define DP_FRAMING_CHANGE_CAP (1 << 1) | |
e045d20b | 115 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ |
bd5da992 | 116 | |
a477f4fc | 117 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
428c4b51 | 118 | |
9474675a JN |
119 | #define DP_ADAPTER_CAP 0x00f /* 1.2 */ |
120 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) | |
121 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) | |
122 | ||
bd5da992 JN |
123 | #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ |
124 | # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ | |
125 | ||
e89861df | 126 | /* Multiple stream transport */ |
3c8a0922 DA |
127 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
128 | # define DP_FAUX_CAP_1 (1 << 0) | |
129 | ||
a477f4fc | 130 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
e89861df AJ |
131 | # define DP_MST_CAP (1 << 0) |
132 | ||
9474675a JN |
133 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ |
134 | ||
135 | /* AV_SYNC_DATA_BLOCK 1.2 */ | |
136 | #define DP_AV_GRANULARITY 0x023 | |
137 | # define DP_AG_FACTOR_MASK (0xf << 0) | |
138 | # define DP_AG_FACTOR_3MS (0 << 0) | |
139 | # define DP_AG_FACTOR_2MS (1 << 0) | |
140 | # define DP_AG_FACTOR_1MS (2 << 0) | |
141 | # define DP_AG_FACTOR_500US (3 << 0) | |
142 | # define DP_AG_FACTOR_200US (4 << 0) | |
143 | # define DP_AG_FACTOR_100US (5 << 0) | |
144 | # define DP_AG_FACTOR_10US (6 << 0) | |
145 | # define DP_AG_FACTOR_1US (7 << 0) | |
146 | # define DP_VG_FACTOR_MASK (0xf << 4) | |
147 | # define DP_VG_FACTOR_3MS (0 << 4) | |
148 | # define DP_VG_FACTOR_2MS (1 << 4) | |
149 | # define DP_VG_FACTOR_1MS (2 << 4) | |
150 | # define DP_VG_FACTOR_500US (3 << 4) | |
151 | # define DP_VG_FACTOR_200US (4 << 4) | |
152 | # define DP_VG_FACTOR_100US (5 << 4) | |
153 | ||
154 | #define DP_AUD_DEC_LAT0 0x024 | |
155 | #define DP_AUD_DEC_LAT1 0x025 | |
156 | ||
157 | #define DP_AUD_PP_LAT0 0x026 | |
158 | #define DP_AUD_PP_LAT1 0x027 | |
159 | ||
160 | #define DP_VID_INTER_LAT 0x028 | |
161 | ||
162 | #define DP_VID_PROG_LAT 0x029 | |
163 | ||
164 | #define DP_REP_LAT 0x02a | |
165 | ||
166 | #define DP_AUD_DEL_INS0 0x02b | |
167 | #define DP_AUD_DEL_INS1 0x02c | |
168 | #define DP_AUD_DEL_INS2 0x02d | |
169 | /* End of AV_SYNC_DATA_BLOCK */ | |
170 | ||
3c8a0922 DA |
171 | #define DP_GUID 0x030 /* 1.2 */ |
172 | ||
a477f4fc | 173 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
b73fe58c | 174 | # define DP_PSR_IS_SUPPORTED 1 |
a477f4fc | 175 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
b73fe58c BW |
176 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
177 | # define DP_PSR_SETUP_TIME_330 (0 << 1) | |
178 | # define DP_PSR_SETUP_TIME_275 (1 << 1) | |
179 | # define DP_PSR_SETUP_TIME_220 (2 << 1) | |
180 | # define DP_PSR_SETUP_TIME_165 (3 << 1) | |
181 | # define DP_PSR_SETUP_TIME_110 (4 << 1) | |
182 | # define DP_PSR_SETUP_TIME_55 (5 << 1) | |
183 | # define DP_PSR_SETUP_TIME_0 (6 << 1) | |
184 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) | |
185 | # define DP_PSR_SETUP_TIME_SHIFT 1 | |
186 | ||
e89861df AJ |
187 | /* |
188 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts | |
189 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, | |
190 | * each port's descriptor is one byte wide. If it was set, each port's is | |
191 | * four bytes wide, starting with the one byte from the base info. As of | |
192 | * DP interop v1.1a only VGA defines additional detail. | |
193 | */ | |
194 | ||
195 | /* offset 0 */ | |
196 | #define DP_DOWNSTREAM_PORT_0 0x80 | |
197 | # define DP_DS_PORT_TYPE_MASK (7 << 0) | |
198 | # define DP_DS_PORT_TYPE_DP 0 | |
199 | # define DP_DS_PORT_TYPE_VGA 1 | |
200 | # define DP_DS_PORT_TYPE_DVI 2 | |
201 | # define DP_DS_PORT_TYPE_HDMI 3 | |
202 | # define DP_DS_PORT_TYPE_NON_EDID 4 | |
203 | # define DP_DS_PORT_HPD (1 << 3) | |
204 | /* offset 1 for VGA is maximum megapixels per second / 8 */ | |
205 | /* offset 2 */ | |
206 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) | |
207 | # define DP_DS_VGA_8BPC 0 | |
208 | # define DP_DS_VGA_10BPC 1 | |
209 | # define DP_DS_VGA_12BPC 2 | |
210 | # define DP_DS_VGA_16BPC 3 | |
211 | ||
5801ead6 AD |
212 | /* link configuration */ |
213 | #define DP_LINK_BW_SET 0x100 | |
a4fc5ed6 KP |
214 | # define DP_LINK_BW_1_62 0x06 |
215 | # define DP_LINK_BW_2_7 0x0a | |
a477f4fc | 216 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
a4fc5ed6 | 217 | |
5801ead6 | 218 | #define DP_LANE_COUNT_SET 0x101 |
a4fc5ed6 KP |
219 | # define DP_LANE_COUNT_MASK 0x0f |
220 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) | |
221 | ||
5801ead6 | 222 | #define DP_TRAINING_PATTERN_SET 0x102 |
a4fc5ed6 KP |
223 | # define DP_TRAINING_PATTERN_DISABLE 0 |
224 | # define DP_TRAINING_PATTERN_1 1 | |
225 | # define DP_TRAINING_PATTERN_2 2 | |
a477f4fc | 226 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
a4fc5ed6 KP |
227 | # define DP_TRAINING_PATTERN_MASK 0x3 |
228 | ||
9474675a JN |
229 | /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ |
230 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) | |
231 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) | |
232 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) | |
233 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) | |
234 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) | |
a4fc5ed6 KP |
235 | |
236 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) | |
237 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) | |
238 | ||
239 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) | |
240 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) | |
241 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) | |
242 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) | |
243 | ||
244 | #define DP_TRAINING_LANE0_SET 0x103 | |
245 | #define DP_TRAINING_LANE1_SET 0x104 | |
246 | #define DP_TRAINING_LANE2_SET 0x105 | |
247 | #define DP_TRAINING_LANE3_SET 0x106 | |
248 | ||
249 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 | |
250 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 | |
251 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) | |
0504cd17 | 252 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
0504cd17 | 253 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
0504cd17 | 254 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
0504cd17 | 255 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
a4fc5ed6 KP |
256 | |
257 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) | |
0504cd17 | 258 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
0504cd17 | 259 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
0504cd17 | 260 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
0504cd17 | 261 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
a4fc5ed6 KP |
262 | |
263 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 | |
264 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) | |
265 | ||
266 | #define DP_DOWNSPREAD_CTRL 0x107 | |
267 | # define DP_SPREAD_AMP_0_5 (1 << 4) | |
a477f4fc | 268 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
a4fc5ed6 KP |
269 | |
270 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 | |
271 | # define DP_SET_ANSI_8B10B (1 << 0) | |
272 | ||
a477f4fc | 273 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
e89861df AJ |
274 | /* bitmask as for DP_I2C_SPEED_CAP */ |
275 | ||
a477f4fc | 276 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
9474675a JN |
277 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) |
278 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1) | |
279 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) | |
280 | ||
281 | #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ | |
282 | #define DP_LINK_QUAL_LANE1_SET 0x10c | |
283 | #define DP_LINK_QUAL_LANE2_SET 0x10d | |
284 | #define DP_LINK_QUAL_LANE3_SET 0x10e | |
285 | # define DP_LINK_QUAL_PATTERN_DISABLE 0 | |
286 | # define DP_LINK_QUAL_PATTERN_D10_2 1 | |
287 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 | |
288 | # define DP_LINK_QUAL_PATTERN_PRBS7 3 | |
289 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 | |
290 | # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 | |
291 | # define DP_LINK_QUAL_PATTERN_MASK 7 | |
292 | ||
293 | #define DP_TRAINING_LANE0_1_SET2 0x10f | |
294 | #define DP_TRAINING_LANE2_3_SET2 0x110 | |
295 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) | |
296 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) | |
297 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) | |
298 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) | |
e89861df | 299 | |
a477f4fc | 300 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
e89861df AJ |
301 | # define DP_MST_EN (1 << 0) |
302 | # define DP_UP_REQ_EN (1 << 1) | |
303 | # define DP_UPSTREAM_IS_SRC (1 << 2) | |
304 | ||
9474675a JN |
305 | #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ |
306 | #define DP_AUDIO_DELAY1 0x113 | |
307 | #define DP_AUDIO_DELAY2 0x114 | |
308 | ||
bd5da992 | 309 | #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ |
e045d20b | 310 | |
9474675a JN |
311 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ |
312 | # define DP_PWR_NOT_NEEDED (1 << 0) | |
313 | ||
a477f4fc | 314 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
b73fe58c BW |
315 | # define DP_PSR_ENABLE (1 << 0) |
316 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) | |
317 | # define DP_PSR_CRC_VERIFICATION (1 << 2) | |
318 | # define DP_PSR_FRAME_CAPTURE (1 << 3) | |
319 | ||
3c8a0922 DA |
320 | #define DP_ADAPTER_CTRL 0x1a0 |
321 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) | |
322 | ||
323 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 | |
324 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) | |
325 | ||
326 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 | |
327 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 | |
328 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 | |
329 | ||
e89861df | 330 | #define DP_SINK_COUNT 0x200 |
da131a46 AJ |
331 | /* prior to 1.2 bit 7 was reserved mbz */ |
332 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) | |
e89861df AJ |
333 | # define DP_SINK_CP_READY (1 << 6) |
334 | ||
a60f0e38 JB |
335 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
336 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) | |
337 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) | |
338 | # define DP_CP_IRQ (1 << 2) | |
3c8a0922 DA |
339 | # define DP_MCCS_IRQ (1 << 3) |
340 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ | |
341 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ | |
a60f0e38 JB |
342 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
343 | ||
a4fc5ed6 KP |
344 | #define DP_LANE0_1_STATUS 0x202 |
345 | #define DP_LANE2_3_STATUS 0x203 | |
a4fc5ed6 KP |
346 | # define DP_LANE_CR_DONE (1 << 0) |
347 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) | |
348 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) | |
349 | ||
5801ead6 AD |
350 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
351 | DP_LANE_CHANNEL_EQ_DONE | \ | |
352 | DP_LANE_SYMBOL_LOCKED) | |
353 | ||
a4fc5ed6 KP |
354 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
355 | ||
356 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) | |
357 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) | |
358 | #define DP_LINK_STATUS_UPDATED (1 << 7) | |
359 | ||
360 | #define DP_SINK_STATUS 0x205 | |
361 | ||
362 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) | |
363 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) | |
364 | ||
365 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 | |
366 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 | |
5801ead6 AD |
367 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
368 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 | |
369 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c | |
370 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 | |
371 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 | |
372 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 | |
373 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 | |
374 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 | |
a4fc5ed6 | 375 | |
a60f0e38 JB |
376 | #define DP_TEST_REQUEST 0x218 |
377 | # define DP_TEST_LINK_TRAINING (1 << 0) | |
fe3c703c | 378 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
a60f0e38 JB |
379 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
380 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ | |
fe3c703c | 381 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
a60f0e38 JB |
382 | |
383 | #define DP_TEST_LINK_RATE 0x219 | |
384 | # define DP_LINK_RATE_162 (0x6) | |
385 | # define DP_LINK_RATE_27 (0xa) | |
386 | ||
387 | #define DP_TEST_LANE_COUNT 0x220 | |
388 | ||
389 | #define DP_TEST_PATTERN 0x221 | |
390 | ||
a25eebb0 RV |
391 | #define DP_TEST_CRC_R_CR 0x240 |
392 | #define DP_TEST_CRC_G_Y 0x242 | |
393 | #define DP_TEST_CRC_B_CB 0x244 | |
394 | ||
395 | #define DP_TEST_SINK_MISC 0x246 | |
ad9dc91b RV |
396 | # define DP_TEST_CRC_SUPPORTED (1 << 5) |
397 | # define DP_TEST_COUNT_MASK 0x7 | |
a25eebb0 | 398 | |
a60f0e38 JB |
399 | #define DP_TEST_RESPONSE 0x260 |
400 | # define DP_TEST_ACK (1 << 0) | |
401 | # define DP_TEST_NAK (1 << 1) | |
402 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) | |
403 | ||
073ea2ae JH |
404 | #define DP_TEST_EDID_CHECKSUM 0x261 |
405 | ||
a25eebb0 | 406 | #define DP_TEST_SINK 0x270 |
ad9dc91b | 407 | # define DP_TEST_SINK_START (1 << 0) |
a25eebb0 | 408 | |
3c8a0922 DA |
409 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
410 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) | |
411 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) | |
412 | ||
413 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ | |
414 | /* up to ID_SLOT_63 at 0x2ff */ | |
415 | ||
86c3c3be AJ |
416 | #define DP_SOURCE_OUI 0x300 |
417 | #define DP_SINK_OUI 0x400 | |
418 | #define DP_BRANCH_OUI 0x500 | |
419 | ||
1a66c95a | 420 | #define DP_SET_POWER 0x600 |
5801ead6 AD |
421 | # define DP_SET_POWER_D0 0x1 |
422 | # define DP_SET_POWER_D3 0x2 | |
516c0f7c | 423 | # define DP_SET_POWER_MASK 0x3 |
1a66c95a | 424 | |
bd5da992 | 425 | #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ |
e045d20b | 426 | |
0e71244c JN |
427 | #define DP_EDP_GENERAL_CAP_1 0x701 |
428 | ||
429 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 | |
430 | ||
431 | #define DP_EDP_GENERAL_CAP_2 0x703 | |
432 | ||
433 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 | |
434 | ||
435 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 | |
436 | ||
437 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 | |
438 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 | |
439 | ||
440 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724 | |
441 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 | |
442 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 | |
443 | ||
444 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 | |
445 | ||
446 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 | |
447 | ||
448 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a | |
449 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b | |
450 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c | |
451 | ||
452 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d | |
453 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e | |
454 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f | |
455 | ||
456 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 | |
457 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 | |
458 | ||
3c8a0922 DA |
459 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
460 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ | |
461 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ | |
462 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ | |
463 | ||
464 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ | |
465 | /* 0-5 sink count */ | |
466 | # define DP_SINK_COUNT_CP_READY (1 << 6) | |
467 | ||
468 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ | |
469 | ||
470 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ | |
471 | ||
472 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ | |
473 | ||
a477f4fc | 474 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
b73fe58c BW |
475 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
476 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) | |
477 | ||
a477f4fc | 478 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
b73fe58c BW |
479 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
480 | ||
a477f4fc | 481 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
b73fe58c BW |
482 | # define DP_PSR_SINK_INACTIVE 0 |
483 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 | |
484 | # define DP_PSR_SINK_ACTIVE_RFB 2 | |
485 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 | |
486 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 | |
487 | # define DP_PSR_SINK_INTERNAL_ERROR 7 | |
488 | # define DP_PSR_SINK_STATE_MASK 0x07 | |
489 | ||
3c8a0922 DA |
490 | /* DP 1.2 Sideband message defines */ |
491 | /* peer device type - DP 1.2a Table 2-92 */ | |
492 | #define DP_PEER_DEVICE_NONE 0x0 | |
493 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 | |
494 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 | |
495 | #define DP_PEER_DEVICE_SST_SINK 0x3 | |
496 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 | |
497 | ||
498 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ | |
499 | #define DP_LINK_ADDRESS 0x01 | |
500 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 | |
501 | #define DP_ENUM_PATH_RESOURCES 0x10 | |
502 | #define DP_ALLOCATE_PAYLOAD 0x11 | |
503 | #define DP_QUERY_PAYLOAD 0x12 | |
504 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 | |
505 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 | |
506 | #define DP_REMOTE_DPCD_READ 0x20 | |
507 | #define DP_REMOTE_DPCD_WRITE 0x21 | |
508 | #define DP_REMOTE_I2C_READ 0x22 | |
509 | #define DP_REMOTE_I2C_WRITE 0x23 | |
510 | #define DP_POWER_UP_PHY 0x24 | |
511 | #define DP_POWER_DOWN_PHY 0x25 | |
512 | #define DP_SINK_EVENT_NOTIFY 0x30 | |
513 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 | |
514 | ||
515 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ | |
516 | #define DP_NAK_WRITE_FAILURE 0x01 | |
517 | #define DP_NAK_INVALID_READ 0x02 | |
518 | #define DP_NAK_CRC_FAILURE 0x03 | |
519 | #define DP_NAK_BAD_PARAM 0x04 | |
520 | #define DP_NAK_DEFER 0x05 | |
521 | #define DP_NAK_LINK_FAILURE 0x06 | |
522 | #define DP_NAK_NO_RESOURCES 0x07 | |
523 | #define DP_NAK_DPCD_FAIL 0x08 | |
524 | #define DP_NAK_I2C_NAK 0x09 | |
525 | #define DP_NAK_ALLOCATE_FAIL 0x0a | |
526 | ||
ab2c0672 DA |
527 | #define MODE_I2C_START 1 |
528 | #define MODE_I2C_WRITE 2 | |
529 | #define MODE_I2C_READ 4 | |
530 | #define MODE_I2C_STOP 8 | |
531 | ||
1ffdff13 | 532 | #define DP_LINK_STATUS_SIZE 6 |
0aec2881 | 533 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 | 534 | int lane_count); |
0aec2881 | 535 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
01916270 | 536 | int lane_count); |
0aec2881 | 537 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 538 | int lane); |
0aec2881 | 539 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 540 | int lane); |
1ffdff13 | 541 | |
52604b1f SK |
542 | #define DP_RECEIVER_CAP_SIZE 0xf |
543 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 | |
544 | ||
0aec2881 JN |
545 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
546 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); | |
1a644cd4 | 547 | |
3b5c662e DV |
548 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
549 | int drm_dp_bw_code_to_link_rate(u8 link_bw); | |
550 | ||
52604b1f SK |
551 | struct edp_sdp_header { |
552 | u8 HB0; /* Secondary Data Packet ID */ | |
553 | u8 HB1; /* Secondary Data Packet Type */ | |
554 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ | |
555 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ | |
556 | } __packed; | |
557 | ||
558 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F | |
559 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F | |
560 | ||
561 | struct edp_vsc_psr { | |
562 | struct edp_sdp_header sdp_header; | |
563 | u8 DB0; /* Stereo Interface */ | |
564 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ | |
565 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ | |
566 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ | |
567 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ | |
568 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ | |
569 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ | |
570 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ | |
571 | u8 DB8_31[24]; /* Reserved */ | |
572 | } __packed; | |
573 | ||
574 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) | |
575 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) | |
576 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) | |
577 | ||
3b5c662e | 578 | static inline int |
0aec2881 | 579 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3b5c662e DV |
580 | { |
581 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); | |
582 | } | |
397fe157 DV |
583 | |
584 | static inline u8 | |
0aec2881 | 585 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
397fe157 DV |
586 | { |
587 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; | |
588 | } | |
589 | ||
58704e6a JN |
590 | static inline bool |
591 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
592 | { | |
593 | return dpcd[DP_DPCD_REV] >= 0x11 && | |
594 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); | |
595 | } | |
596 | ||
c197db75 TR |
597 | /* |
598 | * DisplayPort AUX channel | |
599 | */ | |
600 | ||
601 | /** | |
602 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction | |
603 | * @address: address of the (first) register to access | |
604 | * @request: contains the type of transaction (see DP_AUX_* macros) | |
605 | * @reply: upon completion, contains the reply type of the transaction | |
606 | * @buffer: pointer to a transmission or reception buffer | |
607 | * @size: size of @buffer | |
608 | */ | |
609 | struct drm_dp_aux_msg { | |
610 | unsigned int address; | |
611 | u8 request; | |
612 | u8 reply; | |
613 | void *buffer; | |
614 | size_t size; | |
615 | }; | |
616 | ||
617 | /** | |
618 | * struct drm_dp_aux - DisplayPort AUX channel | |
b8380580 | 619 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
88759686 | 620 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
c197db75 | 621 | * @dev: pointer to struct device that is the parent for this AUX channel |
4f71d0cb | 622 | * @hw_mutex: internal mutex used for locking transfers |
c197db75 TR |
623 | * @transfer: transfers a message representing a single AUX transaction |
624 | * | |
625 | * The .dev field should be set to a pointer to the device that implements | |
626 | * the AUX channel. | |
627 | * | |
9dc40560 JN |
628 | * The .name field may be used to specify the name of the I2C adapter. If set to |
629 | * NULL, dev_name() of .dev will be used. | |
630 | * | |
c197db75 TR |
631 | * Drivers provide a hardware-specific implementation of how transactions |
632 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg | |
633 | * structure describing the transaction is passed into this function. Upon | |
634 | * success, the implementation should return the number of payload bytes | |
635 | * that were transferred, or a negative error-code on failure. Helpers | |
636 | * propagate errors from the .transfer() function, with the exception of | |
637 | * the -EBUSY error, which causes a transaction to be retried. On a short, | |
638 | * helpers will return -EPROTO to make it simpler to check for failure. | |
88759686 TR |
639 | * |
640 | * An AUX channel can also be used to transport I2C messages to a sink. A | |
641 | * typical application of that is to access an EDID that's present in the | |
642 | * sink device. The .transfer() function can also be used to execute such | |
643 | * transactions. The drm_dp_aux_register_i2c_bus() function registers an | |
644 | * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers | |
645 | * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter. | |
732d50b4 AD |
646 | * |
647 | * Note that the aux helper code assumes that the .transfer() function | |
648 | * only modifies the reply field of the drm_dp_aux_msg structure. The | |
649 | * retry logic and i2c helpers assume this is the case. | |
c197db75 TR |
650 | */ |
651 | struct drm_dp_aux { | |
9dc40560 | 652 | const char *name; |
88759686 | 653 | struct i2c_adapter ddc; |
c197db75 | 654 | struct device *dev; |
4f71d0cb | 655 | struct mutex hw_mutex; |
c197db75 TR |
656 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
657 | struct drm_dp_aux_msg *msg); | |
e9cf6194 | 658 | unsigned i2c_nack_count, i2c_defer_count; |
c197db75 TR |
659 | }; |
660 | ||
661 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, | |
662 | void *buffer, size_t size); | |
663 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, | |
664 | void *buffer, size_t size); | |
665 | ||
666 | /** | |
667 | * drm_dp_dpcd_readb() - read a single byte from the DPCD | |
668 | * @aux: DisplayPort AUX channel | |
669 | * @offset: address of the register to read | |
670 | * @valuep: location where the value of the register will be stored | |
671 | * | |
672 | * Returns the number of bytes transferred (1) on success, or a negative | |
673 | * error code on failure. | |
674 | */ | |
675 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, | |
676 | unsigned int offset, u8 *valuep) | |
677 | { | |
678 | return drm_dp_dpcd_read(aux, offset, valuep, 1); | |
679 | } | |
680 | ||
681 | /** | |
682 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD | |
683 | * @aux: DisplayPort AUX channel | |
684 | * @offset: address of the register to write | |
685 | * @value: value to write to the register | |
686 | * | |
687 | * Returns the number of bytes transferred (1) on success, or a negative | |
688 | * error code on failure. | |
689 | */ | |
690 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, | |
691 | unsigned int offset, u8 value) | |
692 | { | |
693 | return drm_dp_dpcd_write(aux, offset, &value, 1); | |
694 | } | |
695 | ||
8d4adc6a TR |
696 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
697 | u8 status[DP_LINK_STATUS_SIZE]); | |
698 | ||
516c0f7c TR |
699 | /* |
700 | * DisplayPort link | |
701 | */ | |
702 | #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) | |
703 | ||
704 | struct drm_dp_link { | |
705 | unsigned char revision; | |
706 | unsigned int rate; | |
707 | unsigned int num_lanes; | |
708 | unsigned long capabilities; | |
709 | }; | |
710 | ||
711 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); | |
712 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); | |
d816f077 | 713 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); |
516c0f7c TR |
714 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); |
715 | ||
4f71d0cb DA |
716 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
717 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); | |
88759686 | 718 | |
ab2c0672 | 719 | #endif /* _DRM_DP_HELPER_H_ */ |