[mirror_ubuntu-bionic-kernel.git] / include / drm / drm_edid.h

/*
 * Copyright © 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __DRM_EDID_H__
#define __DRM_EDID_H__

#include <linux/types.h>
#include <linux/hdmi.h>

struct drm_device;
struct i2c_adapter;

#define EDID_LENGTH 128
#define DDC_ADDR 0x50
#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */

#define CEA_EXT	    0x02
#define VTB_EXT	    0x10
#define DI_EXT	    0x40
#define LS_EXT	    0x50
#define MI_EXT	    0x60
#define DISPLAYID_EXT 0x70

struct est_timings {
	u8 t1;
	u8 t2;
	u8 mfg_rsvd;
} __attribute__((packed));

/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
#define EDID_TIMING_ASPECT_SHIFT 6
#define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)

/* need to add 60 */
#define EDID_TIMING_VFREQ_SHIFT  0
#define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)

struct std_timing {
	u8 hsize; /* need to multiply by 8 then add 248 */
	u8 vfreq_aspect;
} __attribute__((packed));

#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
#define DRM_EDID_PT_STEREO         (1 << 5)
#define DRM_EDID_PT_INTERLACED     (1 << 7)

/* If detailed data is pixel timing */
struct detailed_pixel_timing {
	u8 hactive_lo;
	u8 hblank_lo;
	u8 hactive_hblank_hi;
	u8 vactive_lo;
	u8 vblank_lo;
	u8 vactive_vblank_hi;
	u8 hsync_offset_lo;
	u8 hsync_pulse_width_lo;
	u8 vsync_offset_pulse_width_lo;
	u8 hsync_vsync_offset_pulse_width_hi;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 width_height_mm_hi;
	u8 hborder;
	u8 vborder;
	u8 misc;
} __attribute__((packed));

/* If it's not pixel timing, it'll be one of the below */
struct detailed_data_string {
	u8 str[13];
} __attribute__((packed));

struct detailed_data_monitor_range {
	u8 min_vfreq;
	u8 max_vfreq;
	u8 min_hfreq_khz;
	u8 max_hfreq_khz;
	u8 pixel_clock_mhz; /* need to multiply by 10 */
	u8 flags;
	union {
		struct {
			u8 reserved;
			u8 hfreq_start_khz; /* need to multiply by 2 */
			u8 c; /* need to divide by 2 */
			__le16 m;
			u8 k;
			u8 j; /* need to divide by 2 */
		} __attribute__((packed)) gtf2;
		struct {
			u8 version;
			u8 data1; /* high 6 bits: extra clock resolution */
			u8 data2; /* plus low 2 of above: max hactive */
			u8 supported_aspects;
			u8 flags; /* preferred aspect and blanking support */
			u8 supported_scalings;
			u8 preferred_refresh;
		} __attribute__((packed)) cvt;
	} formula;
} __attribute__((packed));

struct detailed_data_wpindex {
	u8 white_yx_lo; /* Lower 2 bits each */
	u8 white_x_hi;
	u8 white_y_hi;
	u8 gamma; /* need to divide by 100 then add 1 */
} __attribute__((packed));

struct detailed_data_color_point {
	u8 windex1;
	u8 wpindex1[3];
	u8 windex2;
	u8 wpindex2[3];
} __attribute__((packed));

struct cvt_timing {
	u8 code[3];
} __attribute__((packed));

struct detailed_non_pixel {
	u8 pad1;
	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
		    fb=color point data, fa=standard timing data,
		    f9=undefined, f8=mfg. reserved */
	u8 pad2;
	union {
		struct detailed_data_string str;
		struct detailed_data_monitor_range range;
		struct detailed_data_wpindex color;
		struct std_timing timings[6];
		struct cvt_timing cvt[4];
	} data;
} __attribute__((packed));

#define EDID_DETAIL_EST_TIMINGS 0xf7
#define EDID_DETAIL_CVT_3BYTE 0xf8
#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
#define EDID_DETAIL_STD_MODES 0xfa
#define EDID_DETAIL_MONITOR_CPDATA 0xfb
#define EDID_DETAIL_MONITOR_NAME 0xfc
#define EDID_DETAIL_MONITOR_RANGE 0xfd
#define EDID_DETAIL_MONITOR_STRING 0xfe
#define EDID_DETAIL_MONITOR_SERIAL 0xff

struct detailed_timing {
	__le16 pixel_clock; /* need to multiply by 10 KHz */
	union {
		struct detailed_pixel_timing pixel_data;
		struct detailed_non_pixel other_data;
	} data;
} __attribute__((packed));

#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
#define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
#define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
#define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
#define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
#define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
#define DRM_EDID_INPUT_DIGITAL         (1 << 7)
#define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4)
#define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4)
#define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4)
#define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4)
#define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4)
#define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4)
#define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4)
#define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4)
#define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4)
#define DRM_EDID_DIGITAL_TYPE_UNDEF    (0)
#define DRM_EDID_DIGITAL_TYPE_DVI      (1)
#define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2)
#define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3)
#define DRM_EDID_DIGITAL_TYPE_MDDI     (4)
#define DRM_EDID_DIGITAL_TYPE_DP       (5)

#define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
/* If analog */
#define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
/* If digital */
#define DRM_EDID_FEATURE_COLOR_MASK	  (3 << 3)
#define DRM_EDID_FEATURE_RGB		  (0 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB444	  (1 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB422	  (2 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB	  (3 << 3) /* both 4:4:4 and 4:2:2 */

#define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)

#define DRM_EDID_HDMI_DC_48               (1 << 6)
#define DRM_EDID_HDMI_DC_36               (1 << 5)
#define DRM_EDID_HDMI_DC_30               (1 << 4)
#define DRM_EDID_HDMI_DC_Y444             (1 << 3)

/* YCBCR 420 deep color modes */
#define DRM_EDID_YCBCR420_DC_48		  (1 << 6)
#define DRM_EDID_YCBCR420_DC_36		  (1 << 5)
#define DRM_EDID_YCBCR420_DC_30		  (1 << 4)
#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
				    DRM_EDID_YCBCR420_DC_36 | \
				    DRM_EDID_YCBCR420_DC_30)

/* ELD Header Block */
#define DRM_ELD_HEADER_BLOCK_SIZE	4

#define DRM_ELD_VER			0
# define DRM_ELD_VER_SHIFT		3
# define DRM_ELD_VER_MASK		(0x1f << 3)
# define DRM_ELD_VER_CEA861D		(2 << 3) /* supports 861D or below */
# define DRM_ELD_VER_CANNED		(0x1f << 3)

#define DRM_ELD_BASELINE_ELD_LEN	2	/* in dwords! */

/* ELD Baseline Block for ELD_Ver == 2 */
#define DRM_ELD_CEA_EDID_VER_MNL	4
# define DRM_ELD_CEA_EDID_VER_SHIFT	5
# define DRM_ELD_CEA_EDID_VER_MASK	(7 << 5)
# define DRM_ELD_CEA_EDID_VER_NONE	(0 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861	(1 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861A	(2 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861BCD	(3 << 5)
# define DRM_ELD_MNL_SHIFT		0
# define DRM_ELD_MNL_MASK		(0x1f << 0)

#define DRM_ELD_SAD_COUNT_CONN_TYPE	5
# define DRM_ELD_SAD_COUNT_SHIFT	4
# define DRM_ELD_SAD_COUNT_MASK		(0xf << 4)
# define DRM_ELD_CONN_TYPE_SHIFT	2
# define DRM_ELD_CONN_TYPE_MASK		(3 << 2)
# define DRM_ELD_CONN_TYPE_HDMI		(0 << 2)
# define DRM_ELD_CONN_TYPE_DP		(1 << 2)
# define DRM_ELD_SUPPORTS_AI		(1 << 1)
# define DRM_ELD_SUPPORTS_HDCP		(1 << 0)

#define DRM_ELD_AUD_SYNCH_DELAY		6	/* in units of 2 ms */
# define DRM_ELD_AUD_SYNCH_DELAY_MAX	0xfa	/* 500 ms */

#define DRM_ELD_SPEAKER			7
# define DRM_ELD_SPEAKER_MASK		0x7f
# define DRM_ELD_SPEAKER_RLRC		(1 << 6)
# define DRM_ELD_SPEAKER_FLRC		(1 << 5)
# define DRM_ELD_SPEAKER_RC		(1 << 4)
# define DRM_ELD_SPEAKER_RLR		(1 << 3)
# define DRM_ELD_SPEAKER_FC		(1 << 2)
# define DRM_ELD_SPEAKER_LFE		(1 << 1)
# define DRM_ELD_SPEAKER_FLR		(1 << 0)

#define DRM_ELD_PORT_ID			8	/* offsets 8..15 inclusive */
# define DRM_ELD_PORT_ID_LEN		8

#define DRM_ELD_MANUFACTURER_NAME0	16
#define DRM_ELD_MANUFACTURER_NAME1	17

#define DRM_ELD_PRODUCT_CODE0		18
#define DRM_ELD_PRODUCT_CODE1		19

#define DRM_ELD_MONITOR_NAME_STRING	20	/* offsets 20..(20+mnl-1) inclusive */

#define DRM_ELD_CEA_SAD(mnl, sad)	(20 + (mnl) + 3 * (sad))

struct edid {
	u8 header[8];
	/* Vendor & product info */
	u8 mfg_id[2];
	u8 prod_code[2];
	u32 serial; /* FIXME: byte order */
	u8 mfg_week;
	u8 mfg_year;
	/* EDID version */
	u8 version;
	u8 revision;
	/* Display info: */
	u8 input;
	u8 width_cm;
	u8 height_cm;
	u8 gamma;
	u8 features;
	/* Color characteristics */
	u8 red_green_lo;
	u8 black_white_lo;
	u8 red_x;
	u8 red_y;
	u8 green_x;
	u8 green_y;
	u8 blue_x;
	u8 blue_y;
	u8 white_x;
	u8 white_y;
	/* Est. timings and mfg rsvd timings*/
	struct est_timings established_timings;
	/* Standard timings 1-8*/
	struct std_timing standard_timings[8];
	/* Detailing timings 1-4 */
	struct detailed_timing detailed_timings[4];
	/* Number of 128 byte ext. blocks */
	u8 extensions;
	/* Checksum */
	u8 checksum;
} __attribute__((packed));

#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))

/* Short Audio Descriptor */
struct cea_sad {
	u8 format;
	u8 channels; /* max number of channels - 1 */
	u8 freq;
	u8 byte2; /* meaning depends on format */
};

struct drm_encoder;
struct drm_connector;
struct drm_display_mode;

void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
int drm_av_sync_delay(struct drm_connector *connector,
		      const struct drm_display_mode *mode);

#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
struct edid *drm_load_edid_firmware(struct drm_connector *connector);
int __drm_set_edid_firmware_path(const char *path);
int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
#else
static inline struct edid *
drm_load_edid_firmware(struct drm_connector *connector)
{
	return ERR_PTR(-ENOENT);
}
#endif

int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
					 const struct drm_display_mode *mode,
					 bool is_hdmi2_sink);
int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
					    const struct drm_display_mode *mode);
void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
				   const struct drm_display_mode *mode,
				   enum hdmi_quantization_range rgb_quant_range,
				   bool rgb_quant_range_selectable,
				   bool is_hdmi2_sink);

/**
 * drm_eld_mnl - Get ELD monitor name length in bytes.
 * @eld: pointer to an eld memory structure with mnl set
 */
static inline int drm_eld_mnl(const uint8_t *eld)
{
	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
}

/**
 * drm_eld_sad - Get ELD SAD structures.
 * @eld: pointer to an eld memory structure with sad_count set
 */
static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
{
	unsigned int ver, mnl;

	ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
	if (ver != 2 && ver != 31)
		return NULL;

	mnl = drm_eld_mnl(eld);
	if (mnl > 16)
		return NULL;

	return eld + DRM_ELD_CEA_SAD(mnl, 0);
}

/**
 * drm_eld_sad_count - Get ELD SAD count.
 * @eld: pointer to an eld memory structure with sad_count set
 */
static inline int drm_eld_sad_count(const uint8_t *eld)
{
	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
		DRM_ELD_SAD_COUNT_SHIFT;
}

/**
 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
 * @eld: pointer to an eld memory structure with mnl and sad_count set
 *
 * This is a helper for determining the payload size of the baseline block, in
 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
 */
static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
{
	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
		drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
}

/**
 * drm_eld_size - Get ELD size in bytes
 * @eld: pointer to a complete eld memory structure
 *
 * The returned value does not include the vendor block. It's vendor specific,
 * and comprises of the remaining bytes in the ELD memory buffer after
 * drm_eld_size() bytes of header and baseline block.
 *
 * The returned value is guaranteed to be a multiple of 4.
 */
static inline int drm_eld_size(const uint8_t *eld)
{
	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
}

/**
 * drm_eld_get_spk_alloc - Get speaker allocation
 * @eld: pointer to an ELD memory structure
 *
 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
 * field definitions to identify speakers.
 */
static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
{
	return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
}

/**
 * drm_eld_get_conn_type - Get device type hdmi/dp connected
 * @eld: pointer to an ELD memory structure
 *
 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
 * identify the display type connected.
 */
static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
{
	return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
}

bool drm_probe_ddc(struct i2c_adapter *adapter);
struct edid *drm_do_get_edid(struct drm_connector *connector,
	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
			      size_t len),
	void *data);
struct edid *drm_get_edid(struct drm_connector *connector,
			  struct i2c_adapter *adapter);
struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
				     struct i2c_adapter *adapter);
struct edid *drm_edid_duplicate(const struct edid *edid);
void drm_reset_display_info(struct drm_connector *connector);
u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid);
int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);

u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
bool drm_detect_hdmi_monitor(struct edid *edid);
bool drm_detect_monitor_audio(struct edid *edid);
bool drm_rgb_quant_range_selectable(struct edid *edid);
enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode *mode);
int drm_add_modes_noedid(struct drm_connector *connector,
			 int hdisplay, int vdisplay);
void drm_set_preferred_mode(struct drm_connector *connector,
			    int hpref, int vpref);

int drm_edid_header_is_valid(const u8 *raw_edid);
bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
			  bool *edid_corrupt);
bool drm_edid_is_valid(struct edid *edid);
void drm_edid_get_monitor_name(struct edid *edid, char *name,
			       int buflen);
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
					   int hsize, int vsize, int fresh,
					   bool rb);
#endif /* __DRM_EDID_H__ */
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright © 2007-2008 Intel Corporation
	3	* Jesse Barnes <jesse.barnes@intel.com>
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*/
	23	#ifndef __DRM_EDID_H__
	24	#define __DRM_EDID_H__
	25
	26	#include <linux/types.h>
00147934	27	#include <linux/hdmi.h>
f453ba04	28
cdc3d09f DV	29	struct drm_device;
	30	struct i2c_adapter;
	31
f453ba04 DA	32	#define EDID_LENGTH 128
f453ba04 DA	33	#define DDC_ADDR 0x50
b49b55bd	34	#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
f453ba04	35
4d76a221 AJ	36	#define CEA_EXT 0x02
	37	#define VTB_EXT 0x10
	38	#define DI_EXT 0x40
	39	#define LS_EXT 0x50
	40	#define MI_EXT 0x60
b49b55bd	41	#define DISPLAYID_EXT 0x70
4d76a221	42
f453ba04 DA	43	struct est_timings {
	44	u8 t1;
	45	u8 t2;
	46	u8 mfg_rsvd;
	47	} __attribute__((packed));
	48
0454beab	49	/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
e14cbee4	50	#define EDID_TIMING_ASPECT_SHIFT 6
0454beab MD	51	#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
	52
	53	/* need to add 60 */
e14cbee4	54	#define EDID_TIMING_VFREQ_SHIFT 0
0454beab MD	55	#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
0454beab MD	56
f453ba04 DA	57	struct std_timing {
f453ba04 DA	58	u8 hsize; /* need to multiply by 8 then add 248 */
0454beab	59	u8 vfreq_aspect;
f453ba04 DA	60	} __attribute__((packed));
f453ba04 DA	61
e14cbee4 MD	62	#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
e14cbee4 MD	63	#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
0454beab	64	#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
e14cbee4 MD	65	#define DRM_EDID_PT_STEREO (1 << 5)
e14cbee4 MD	66	#define DRM_EDID_PT_INTERLACED (1 << 7)
0454beab	67
f453ba04 DA	68	/* If detailed data is pixel timing */
	69	struct detailed_pixel_timing {
	70	u8 hactive_lo;
	71	u8 hblank_lo;
0454beab	72	u8 hactive_hblank_hi;
f453ba04 DA	73	u8 vactive_lo;
f453ba04 DA	74	u8 vblank_lo;
0454beab	75	u8 vactive_vblank_hi;
f453ba04 DA	76	u8 hsync_offset_lo;
f453ba04 DA	77	u8 hsync_pulse_width_lo;
0454beab MD	78	u8 vsync_offset_pulse_width_lo;
0454beab MD	79	u8 hsync_vsync_offset_pulse_width_hi;
f453ba04 DA	80	u8 width_mm_lo;
f453ba04 DA	81	u8 height_mm_lo;
0454beab	82	u8 width_height_mm_hi;
f453ba04 DA	83	u8 hborder;
f453ba04 DA	84	u8 vborder;
0454beab	85	u8 misc;
f453ba04 DA	86	} __attribute__((packed));
	87
	88	/* If it's not pixel timing, it'll be one of the below */
	89	struct detailed_data_string {
	90	u8 str[13];
	91	} __attribute__((packed));
	92
	93	struct detailed_data_monitor_range {
	94	u8 min_vfreq;
	95	u8 max_vfreq;
	96	u8 min_hfreq_khz;
	97	u8 max_hfreq_khz;
	98	u8 pixel_clock_mhz; /* need to multiply by 10 */
eeefa4be AJ	99	u8 flags;
	100	union {
	101	struct {
	102	u8 reserved;
	103	u8 hfreq_start_khz; /* need to multiply by 2 */
	104	u8 c; /* need to divide by 2 */
	105	__le16 m;
	106	u8 k;
	107	u8 j; /* need to divide by 2 */
8353e6c6	108	} __attribute__((packed)) gtf2;
eeefa4be AJ	109	struct {
	110	u8 version;
	111	u8 data1; /* high 6 bits: extra clock resolution */
	112	u8 data2; /* plus low 2 of above: max hactive */
	113	u8 supported_aspects;
	114	u8 flags; /* preferred aspect and blanking support */
	115	u8 supported_scalings;
	116	u8 preferred_refresh;
8353e6c6	117	} __attribute__((packed)) cvt;
eeefa4be	118	} formula;
f453ba04 DA	119	} __attribute__((packed));
	120
	121	struct detailed_data_wpindex {
e14cbee4	122	u8 white_yx_lo; /* Lower 2 bits each */
f453ba04 DA	123	u8 white_x_hi;
	124	u8 white_y_hi;
	125	u8 gamma; /* need to divide by 100 then add 1 */
	126	} __attribute__((packed));
	127
	128	struct detailed_data_color_point {
	129	u8 windex1;
	130	u8 wpindex1[3];
	131	u8 windex2;
	132	u8 wpindex2[3];
	133	} __attribute__((packed));
	134
9340d8cf AJ	135	struct cvt_timing {
	136	u8 code[3];
	137	} __attribute__((packed));
	138
f453ba04 DA	139	struct detailed_non_pixel {
	140	u8 pad1;
	141	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
	142	fb=color point data, fa=standard timing data,
	143	f9=undefined, f8=mfg. reserved */
	144	u8 pad2;
	145	union {
	146	struct detailed_data_string str;
	147	struct detailed_data_monitor_range range;
	148	struct detailed_data_wpindex color;
96525a2f	149	struct std_timing timings[6];
9340d8cf	150	struct cvt_timing cvt[4];
f453ba04 DA	151	} data;
	152	} __attribute__((packed));
	153
2dbdc52c AJ	154	#define EDID_DETAIL_EST_TIMINGS 0xf7
	155	#define EDID_DETAIL_CVT_3BYTE 0xf8
	156	#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
f453ba04 DA	157	#define EDID_DETAIL_STD_MODES 0xfa
	158	#define EDID_DETAIL_MONITOR_CPDATA 0xfb
	159	#define EDID_DETAIL_MONITOR_NAME 0xfc
	160	#define EDID_DETAIL_MONITOR_RANGE 0xfd
	161	#define EDID_DETAIL_MONITOR_STRING 0xfe
	162	#define EDID_DETAIL_MONITOR_SERIAL 0xff
	163
	164	struct detailed_timing {
0454beab	165	__le16 pixel_clock; /* need to multiply by 10 KHz */
f453ba04 DA	166	union {
	167	struct detailed_pixel_timing pixel_data;
	168	struct detailed_non_pixel other_data;
	169	} data;
	170	} __attribute__((packed));
	171
e14cbee4 MD	172	#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
	173	#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
	174	#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
0454beab	175	#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
e14cbee4 MD	176	#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
e14cbee4 MD	177	#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
3b11228b JB	178	#define DRM_EDID_INPUT_DIGITAL (1 << 7)
	179	#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
	180	#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
	181	#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
	182	#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
	183	#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
	184	#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
	185	#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
	186	#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
	187	#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
	188	#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
	189	#define DRM_EDID_DIGITAL_TYPE_DVI (1)
	190	#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
	191	#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
	192	#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
	193	#define DRM_EDID_DIGITAL_TYPE_DP (5)
0454beab	194
e14cbee4 MD	195	#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
	196	#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
	197	#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
da05a5a7	198	/* If analog */
0454beab	199	#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
da05a5a7 JB	200	/* If digital */
	201	#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
	202	#define DRM_EDID_FEATURE_RGB (0 << 3)
	203	#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
	204	#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
	205	#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
	206
e14cbee4 MD	207	#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
	208	#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
	209	#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
0454beab	210
d0c94692 MK	211	#define DRM_EDID_HDMI_DC_48 (1 << 6)
	212	#define DRM_EDID_HDMI_DC_36 (1 << 5)
	213	#define DRM_EDID_HDMI_DC_30 (1 << 4)
	214	#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
	215
e6a9a2c3 SS	216	/* YCBCR 420 deep color modes */
	217	#define DRM_EDID_YCBCR420_DC_48 (1 << 6)
	218	#define DRM_EDID_YCBCR420_DC_36 (1 << 5)
	219	#define DRM_EDID_YCBCR420_DC_30 (1 << 4)
	220	#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 \| \
	221	DRM_EDID_YCBCR420_DC_36 \| \
	222	DRM_EDID_YCBCR420_DC_30)
	223
babc9493 JN	224	/* ELD Header Block */
	225	#define DRM_ELD_HEADER_BLOCK_SIZE 4
	226
	227	#define DRM_ELD_VER 0
	228	# define DRM_ELD_VER_SHIFT 3
	229	# define DRM_ELD_VER_MASK (0x1f << 3)
1b54bdb8 JN	230	# define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */
1b54bdb8 JN	231	# define DRM_ELD_VER_CANNED (0x1f << 3)
babc9493 JN	232
	233	#define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
	234
	235	/* ELD Baseline Block for ELD_Ver == 2 */
	236	#define DRM_ELD_CEA_EDID_VER_MNL 4
	237	# define DRM_ELD_CEA_EDID_VER_SHIFT 5
	238	# define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
	239	# define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
	240	# define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
	241	# define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
	242	# define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
	243	# define DRM_ELD_MNL_SHIFT 0
	244	# define DRM_ELD_MNL_MASK (0x1f << 0)
	245
	246	#define DRM_ELD_SAD_COUNT_CONN_TYPE 5
	247	# define DRM_ELD_SAD_COUNT_SHIFT 4
	248	# define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
	249	# define DRM_ELD_CONN_TYPE_SHIFT 2
	250	# define DRM_ELD_CONN_TYPE_MASK (3 << 2)
	251	# define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
	252	# define DRM_ELD_CONN_TYPE_DP (1 << 2)
	253	# define DRM_ELD_SUPPORTS_AI (1 << 1)
	254	# define DRM_ELD_SUPPORTS_HDCP (1 << 0)
	255
	256	#define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
	257	# define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
	258
	259	#define DRM_ELD_SPEAKER 7
c82dbe5c	260	# define DRM_ELD_SPEAKER_MASK 0x7f
babc9493 JN	261	# define DRM_ELD_SPEAKER_RLRC (1 << 6)
	262	# define DRM_ELD_SPEAKER_FLRC (1 << 5)
	263	# define DRM_ELD_SPEAKER_RC (1 << 4)
	264	# define DRM_ELD_SPEAKER_RLR (1 << 3)
	265	# define DRM_ELD_SPEAKER_FC (1 << 2)
	266	# define DRM_ELD_SPEAKER_LFE (1 << 1)
	267	# define DRM_ELD_SPEAKER_FLR (1 << 0)
	268
	269	#define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
	270	# define DRM_ELD_PORT_ID_LEN 8
	271
	272	#define DRM_ELD_MANUFACTURER_NAME0 16
	273	#define DRM_ELD_MANUFACTURER_NAME1 17
	274
	275	#define DRM_ELD_PRODUCT_CODE0 18
	276	#define DRM_ELD_PRODUCT_CODE1 19
	277
	278	#define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
	279
	280	#define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
	281
f453ba04 DA	282	struct edid {
	283	u8 header[8];
	284	/* Vendor & product info */
	285	u8 mfg_id[2];
	286	u8 prod_code[2];
	287	u32 serial; /* FIXME: byte order */
	288	u8 mfg_week;
	289	u8 mfg_year;
	290	/* EDID version */
	291	u8 version;
	292	u8 revision;
	293	/* Display info: */
0454beab	294	u8 input;
f453ba04 DA	295	u8 width_cm;
	296	u8 height_cm;
	297	u8 gamma;
0454beab	298	u8 features;
f453ba04 DA	299	/* Color characteristics */
	300	u8 red_green_lo;
	301	u8 black_white_lo;
	302	u8 red_x;
	303	u8 red_y;
	304	u8 green_x;
	305	u8 green_y;
	306	u8 blue_x;
	307	u8 blue_y;
	308	u8 white_x;
	309	u8 white_y;
	310	/* Est. timings and mfg rsvd timings*/
	311	struct est_timings established_timings;
	312	/* Standard timings 1-8*/
	313	struct std_timing standard_timings[8];
	314	/* Detailing timings 1-4 */
	315	struct detailed_timing detailed_timings[4];
	316	/* Number of 128 byte ext. blocks */
	317	u8 extensions;
	318	/* Checksum */
	319	u8 checksum;
	320	} __attribute__((packed));
	321
f453ba04 DA	322	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
f453ba04 DA	323
fe214163 RM	324	/* Short Audio Descriptor */
	325	struct cea_sad {
	326	u8 format;
	327	u8 channels; /* max number of channels - 1 */
	328	u8 freq;
	329	u8 byte2; /* meaning depends on format */
	330	};
	331
76adaa34 WF	332	struct drm_encoder;
	333	struct drm_connector;
	334	struct drm_display_mode;
10a85120	335
76adaa34	336	void drm_edid_to_eld(struct drm_connector connector, struct edid edid);
fe214163	337	int drm_edid_to_sad(struct edid edid, struct cea_sad *sads);
d105f476	338	int drm_edid_to_speaker_allocation(struct edid edid, u8 *sadb);
76adaa34	339	int drm_av_sync_delay(struct drm_connector *connector,
3a818d35	340	const struct drm_display_mode *mode);
ba34d58c EG	341
ba34d58c EG	342	#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
07c2b84b	343	struct edid drm_load_edid_firmware(struct drm_connector connector);
ac6c35a4 JN	344	int __drm_set_edid_firmware_path(const char *path);
ac6c35a4 JN	345	int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
ba34d58c	346	#else
07c2b84b JN	347	static inline struct edid *
07c2b84b JN	348	drm_load_edid_firmware(struct drm_connector *connector)
ba34d58c	349	{
07c2b84b	350	return ERR_PTR(-ENOENT);
ba34d58c EG	351	}
ba34d58c EG	352	#endif
76adaa34	353
10a85120 TR	354	int
10a85120 TR	355	drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
0c1f528c SS	356	const struct drm_display_mode *mode,
0c1f528c SS	357	bool is_hdmi2_sink);
83dd0008 LD	358	int
	359	drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
	360	const struct drm_display_mode *mode);
a2ce26f8 VS	361	void
a2ce26f8 VS	362	drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
779c4c28	363	const struct drm_display_mode *mode,
a2ce26f8	364	enum hdmi_quantization_range rgb_quant_range,
9271c0ca VS	365	bool rgb_quant_range_selectable,
9271c0ca VS	366	bool is_hdmi2_sink);
10a85120	367
babc9493 JN	368	/**
	369	* drm_eld_mnl - Get ELD monitor name length in bytes.
	370	* @eld: pointer to an eld memory structure with mnl set
	371	*/
	372	static inline int drm_eld_mnl(const uint8_t *eld)
	373	{
	374	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
	375	}
	376
1c73d3b1 RK	377	/**
	378	* drm_eld_sad - Get ELD SAD structures.
	379	* @eld: pointer to an eld memory structure with sad_count set
	380	*/
	381	static inline const uint8_t drm_eld_sad(const uint8_t eld)
	382	{
	383	unsigned int ver, mnl;
	384
	385	ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
	386	if (ver != 2 && ver != 31)
	387	return NULL;
	388
	389	mnl = drm_eld_mnl(eld);
	390	if (mnl > 16)
	391	return NULL;
	392
	393	return eld + DRM_ELD_CEA_SAD(mnl, 0);
	394	}
	395
babc9493 JN	396	/**
	397	* drm_eld_sad_count - Get ELD SAD count.
	398	* @eld: pointer to an eld memory structure with sad_count set
	399	*/
	400	static inline int drm_eld_sad_count(const uint8_t *eld)
	401	{
	402	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
	403	DRM_ELD_SAD_COUNT_SHIFT;
	404	}
	405
	406	/**
	407	* drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
	408	* @eld: pointer to an eld memory structure with mnl and sad_count set
	409	*
	410	* This is a helper for determining the payload size of the baseline block, in
	411	* bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
	412	*/
	413	static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
	414	{
	415	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
	416	drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
	417	}
	418
	419	/**
	420	* drm_eld_size - Get ELD size in bytes
	421	* @eld: pointer to a complete eld memory structure
	422	*
	423	* The returned value does not include the vendor block. It's vendor specific,
	424	* and comprises of the remaining bytes in the ELD memory buffer after
	425	* drm_eld_size() bytes of header and baseline block.
	426	*
	427	* The returned value is guaranteed to be a multiple of 4.
	428	*/
	429	static inline int drm_eld_size(const uint8_t *eld)
	430	{
	431	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
	432	}
	433
c82dbe5c AP	434	/**
	435	* drm_eld_get_spk_alloc - Get speaker allocation
	436	* @eld: pointer to an ELD memory structure
	437	*
	438	* The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
	439	* field definitions to identify speakers.
	440	*/
	441	static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
	442	{
	443	return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
	444	}
	445
1aa8ec25 SP	446	/**
	447	* drm_eld_get_conn_type - Get device type hdmi/dp connected
	448	* @eld: pointer to an ELD memory structure
	449	*
	450	* The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
	451	* identify the display type connected.
	452	*/
	453	static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
	454	{
	455	return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
	456	}
	457
cdc3d09f	458	bool drm_probe_ddc(struct i2c_adapter *adapter);
18df89fe LPC	459	struct edid drm_do_get_edid(struct drm_connector connector,
	460	int (get_edid_block)(void data, u8 *buf, unsigned int block,
	461	size_t len),
	462	void *data);
cdc3d09f DV	463	struct edid drm_get_edid(struct drm_connector connector,
	464	struct i2c_adapter *adapter);
	465	struct edid drm_get_edid_switcheroo(struct drm_connector connector,
	466	struct i2c_adapter *adapter);
	467	struct edid drm_edid_duplicate(const struct edid edid);
4b4df570 KP	468	void drm_reset_display_info(struct drm_connector *connector);
4b4df570 KP	469	u32 drm_add_display_info(struct drm_connector connector, const struct edid edid);
cdc3d09f DV	470	int drm_add_edid_modes(struct drm_connector connector, struct edid edid);
	471
	472	u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
	473	enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
	474	bool drm_detect_hdmi_monitor(struct edid *edid);
	475	bool drm_detect_monitor_audio(struct edid *edid);
	476	bool drm_rgb_quant_range_selectable(struct edid *edid);
c8127cf0 VS	477	enum hdmi_quantization_range
c8127cf0 VS	478	drm_default_rgb_quant_range(const struct drm_display_mode *mode);
cdc3d09f DV	479	int drm_add_modes_noedid(struct drm_connector *connector,
	480	int hdisplay, int vdisplay);
	481	void drm_set_preferred_mode(struct drm_connector *connector,
	482	int hpref, int vpref);
	483
	484	int drm_edid_header_is_valid(const u8 *raw_edid);
	485	bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
	486	bool *edid_corrupt);
	487	bool drm_edid_is_valid(struct edid *edid);
	488	void drm_edid_get_monitor_name(struct edid edid, char name,
	489	int buflen);
	490	struct drm_display_mode drm_mode_find_dmt(struct drm_device dev,
	491	int hsize, int vsize, int fresh,
	492	bool rb);
f453ba04	493	#endif /* __DRM_EDID_H__ */