[mirror_ubuntu-bionic-kernel.git] / include / drm / drm_edid.h

/*
 * Copyright © 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __DRM_EDID_H__
#define __DRM_EDID_H__

#include <linux/types.h>

#define EDID_LENGTH 128
#define DDC_ADDR 0x50

#define CEA_EXT	    0x02
#define VTB_EXT	    0x10
#define DI_EXT	    0x40
#define LS_EXT	    0x50
#define MI_EXT	    0x60

struct est_timings {
	u8 t1;
	u8 t2;
	u8 mfg_rsvd;
} __attribute__((packed));

/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
#define EDID_TIMING_ASPECT_SHIFT 6
#define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)

/* need to add 60 */
#define EDID_TIMING_VFREQ_SHIFT  0
#define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)

struct std_timing {
	u8 hsize; /* need to multiply by 8 then add 248 */
	u8 vfreq_aspect;
} __attribute__((packed));

#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
#define DRM_EDID_PT_STEREO         (1 << 5)
#define DRM_EDID_PT_INTERLACED     (1 << 7)

/* If detailed data is pixel timing */
struct detailed_pixel_timing {
	u8 hactive_lo;
	u8 hblank_lo;
	u8 hactive_hblank_hi;
	u8 vactive_lo;
	u8 vblank_lo;
	u8 vactive_vblank_hi;
	u8 hsync_offset_lo;
	u8 hsync_pulse_width_lo;
	u8 vsync_offset_pulse_width_lo;
	u8 hsync_vsync_offset_pulse_width_hi;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 width_height_mm_hi;
	u8 hborder;
	u8 vborder;
	u8 misc;
} __attribute__((packed));

/* If it's not pixel timing, it'll be one of the below */
struct detailed_data_string {
	u8 str[13];
} __attribute__((packed));

struct detailed_data_monitor_range {
	u8 min_vfreq;
	u8 max_vfreq;
	u8 min_hfreq_khz;
	u8 max_hfreq_khz;
	u8 pixel_clock_mhz; /* need to multiply by 10 */
	u8 flags;
	union {
		struct {
			u8 reserved;
			u8 hfreq_start_khz; /* need to multiply by 2 */
			u8 c; /* need to divide by 2 */
			__le16 m;
			u8 k;
			u8 j; /* need to divide by 2 */
		} __attribute__((packed)) gtf2;
		struct {
			u8 version;
			u8 data1; /* high 6 bits: extra clock resolution */
			u8 data2; /* plus low 2 of above: max hactive */
			u8 supported_aspects;
			u8 flags; /* preferred aspect and blanking support */
			u8 supported_scalings;
			u8 preferred_refresh;
		} __attribute__((packed)) cvt;
	} formula;
} __attribute__((packed));

struct detailed_data_wpindex {
	u8 white_yx_lo; /* Lower 2 bits each */
	u8 white_x_hi;
	u8 white_y_hi;
	u8 gamma; /* need to divide by 100 then add 1 */
} __attribute__((packed));

struct detailed_data_color_point {
	u8 windex1;
	u8 wpindex1[3];
	u8 windex2;
	u8 wpindex2[3];
} __attribute__((packed));

struct cvt_timing {
	u8 code[3];
} __attribute__((packed));

struct detailed_non_pixel {
	u8 pad1;
	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
		    fb=color point data, fa=standard timing data,
		    f9=undefined, f8=mfg. reserved */
	u8 pad2;
	union {
		struct detailed_data_string str;
		struct detailed_data_monitor_range range;
		struct detailed_data_wpindex color;
		struct std_timing timings[6];
		struct cvt_timing cvt[4];
	} data;
} __attribute__((packed));

#define EDID_DETAIL_EST_TIMINGS 0xf7
#define EDID_DETAIL_CVT_3BYTE 0xf8
#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
#define EDID_DETAIL_STD_MODES 0xfa
#define EDID_DETAIL_MONITOR_CPDATA 0xfb
#define EDID_DETAIL_MONITOR_NAME 0xfc
#define EDID_DETAIL_MONITOR_RANGE 0xfd
#define EDID_DETAIL_MONITOR_STRING 0xfe
#define EDID_DETAIL_MONITOR_SERIAL 0xff

struct detailed_timing {
	__le16 pixel_clock; /* need to multiply by 10 KHz */
	union {
		struct detailed_pixel_timing pixel_data;
		struct detailed_non_pixel other_data;
	} data;
} __attribute__((packed));

#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
#define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
#define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
#define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
#define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
#define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
#define DRM_EDID_INPUT_DIGITAL         (1 << 7)
#define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4)
#define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4)
#define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4)
#define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4)
#define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4)
#define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4)
#define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4)
#define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4)
#define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4)
#define DRM_EDID_DIGITAL_TYPE_UNDEF    (0)
#define DRM_EDID_DIGITAL_TYPE_DVI      (1)
#define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2)
#define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3)
#define DRM_EDID_DIGITAL_TYPE_MDDI     (4)
#define DRM_EDID_DIGITAL_TYPE_DP       (5)

#define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
/* If analog */
#define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
/* If digital */
#define DRM_EDID_FEATURE_COLOR_MASK	  (3 << 3)
#define DRM_EDID_FEATURE_RGB		  (0 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB444	  (1 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB422	  (2 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB	  (3 << 3) /* both 4:4:4 and 4:2:2 */

#define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)

#define DRM_EDID_HDMI_DC_48               (1 << 6)
#define DRM_EDID_HDMI_DC_36               (1 << 5)
#define DRM_EDID_HDMI_DC_30               (1 << 4)
#define DRM_EDID_HDMI_DC_Y444             (1 << 3)

/* ELD Header Block */
#define DRM_ELD_HEADER_BLOCK_SIZE	4

#define DRM_ELD_VER			0
# define DRM_ELD_VER_SHIFT		3
# define DRM_ELD_VER_MASK		(0x1f << 3)

#define DRM_ELD_BASELINE_ELD_LEN	2	/* in dwords! */

/* ELD Baseline Block for ELD_Ver == 2 */
#define DRM_ELD_CEA_EDID_VER_MNL	4
# define DRM_ELD_CEA_EDID_VER_SHIFT	5
# define DRM_ELD_CEA_EDID_VER_MASK	(7 << 5)
# define DRM_ELD_CEA_EDID_VER_NONE	(0 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861	(1 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861A	(2 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861BCD	(3 << 5)
# define DRM_ELD_MNL_SHIFT		0
# define DRM_ELD_MNL_MASK		(0x1f << 0)

#define DRM_ELD_SAD_COUNT_CONN_TYPE	5
# define DRM_ELD_SAD_COUNT_SHIFT	4
# define DRM_ELD_SAD_COUNT_MASK		(0xf << 4)
# define DRM_ELD_CONN_TYPE_SHIFT	2
# define DRM_ELD_CONN_TYPE_MASK		(3 << 2)
# define DRM_ELD_CONN_TYPE_HDMI		(0 << 2)
# define DRM_ELD_CONN_TYPE_DP		(1 << 2)
# define DRM_ELD_SUPPORTS_AI		(1 << 1)
# define DRM_ELD_SUPPORTS_HDCP		(1 << 0)

#define DRM_ELD_AUD_SYNCH_DELAY		6	/* in units of 2 ms */
# define DRM_ELD_AUD_SYNCH_DELAY_MAX	0xfa	/* 500 ms */

#define DRM_ELD_SPEAKER			7
# define DRM_ELD_SPEAKER_RLRC		(1 << 6)
# define DRM_ELD_SPEAKER_FLRC		(1 << 5)
# define DRM_ELD_SPEAKER_RC		(1 << 4)
# define DRM_ELD_SPEAKER_RLR		(1 << 3)
# define DRM_ELD_SPEAKER_FC		(1 << 2)
# define DRM_ELD_SPEAKER_LFE		(1 << 1)
# define DRM_ELD_SPEAKER_FLR		(1 << 0)

#define DRM_ELD_PORT_ID			8	/* offsets 8..15 inclusive */
# define DRM_ELD_PORT_ID_LEN		8

#define DRM_ELD_MANUFACTURER_NAME0	16
#define DRM_ELD_MANUFACTURER_NAME1	17

#define DRM_ELD_PRODUCT_CODE0		18
#define DRM_ELD_PRODUCT_CODE1		19

#define DRM_ELD_MONITOR_NAME_STRING	20	/* offsets 20..(20+mnl-1) inclusive */

#define DRM_ELD_CEA_SAD(mnl, sad)	(20 + (mnl) + 3 * (sad))

struct edid {
	u8 header[8];
	/* Vendor & product info */
	u8 mfg_id[2];
	u8 prod_code[2];
	u32 serial; /* FIXME: byte order */
	u8 mfg_week;
	u8 mfg_year;
	/* EDID version */
	u8 version;
	u8 revision;
	/* Display info: */
	u8 input;
	u8 width_cm;
	u8 height_cm;
	u8 gamma;
	u8 features;
	/* Color characteristics */
	u8 red_green_lo;
	u8 black_white_lo;
	u8 red_x;
	u8 red_y;
	u8 green_x;
	u8 green_y;
	u8 blue_x;
	u8 blue_y;
	u8 white_x;
	u8 white_y;
	/* Est. timings and mfg rsvd timings*/
	struct est_timings established_timings;
	/* Standard timings 1-8*/
	struct std_timing standard_timings[8];
	/* Detailing timings 1-4 */
	struct detailed_timing detailed_timings[4];
	/* Number of 128 byte ext. blocks */
	u8 extensions;
	/* Checksum */
	u8 checksum;
} __attribute__((packed));

#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))

/* Short Audio Descriptor */
struct cea_sad {
	u8 format;
	u8 channels; /* max number of channels - 1 */
	u8 freq;
	u8 byte2; /* meaning depends on format */
};

struct drm_encoder;
struct drm_connector;
struct drm_display_mode;
struct hdmi_avi_infoframe;
struct hdmi_vendor_infoframe;

void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
int drm_av_sync_delay(struct drm_connector *connector,
		      struct drm_display_mode *mode);
struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
				     struct drm_display_mode *mode);
int drm_load_edid_firmware(struct drm_connector *connector);

int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
					 const struct drm_display_mode *mode);
int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
					    const struct drm_display_mode *mode);

/**
 * drm_eld_mnl - Get ELD monitor name length in bytes.
 * @eld: pointer to an eld memory structure with mnl set
 */
static inline int drm_eld_mnl(const uint8_t *eld)
{
	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
}

/**
 * drm_eld_sad_count - Get ELD SAD count.
 * @eld: pointer to an eld memory structure with sad_count set
 */
static inline int drm_eld_sad_count(const uint8_t *eld)
{
	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
		DRM_ELD_SAD_COUNT_SHIFT;
}

/**
 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
 * @eld: pointer to an eld memory structure with mnl and sad_count set
 *
 * This is a helper for determining the payload size of the baseline block, in
 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
 */
static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
{
	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
		drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
}

/**
 * drm_eld_size - Get ELD size in bytes
 * @eld: pointer to a complete eld memory structure
 *
 * The returned value does not include the vendor block. It's vendor specific,
 * and comprises of the remaining bytes in the ELD memory buffer after
 * drm_eld_size() bytes of header and baseline block.
 *
 * The returned value is guaranteed to be a multiple of 4.
 */
static inline int drm_eld_size(const uint8_t *eld)
{
	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
}

#endif /* __DRM_EDID_H__ */
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright © 2007-2008 Intel Corporation
	3	* Jesse Barnes <jesse.barnes@intel.com>
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*/
	23	#ifndef __DRM_EDID_H__
	24	#define __DRM_EDID_H__
	25
	26	#include <linux/types.h>
	27
	28	#define EDID_LENGTH 128
	29	#define DDC_ADDR 0x50
	30
4d76a221 AJ	31	#define CEA_EXT 0x02
	32	#define VTB_EXT 0x10
	33	#define DI_EXT 0x40
	34	#define LS_EXT 0x50
	35	#define MI_EXT 0x60
	36
f453ba04 DA	37	struct est_timings {
	38	u8 t1;
	39	u8 t2;
	40	u8 mfg_rsvd;
	41	} __attribute__((packed));
	42
0454beab	43	/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
e14cbee4	44	#define EDID_TIMING_ASPECT_SHIFT 6
0454beab MD	45	#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
	46
	47	/* need to add 60 */
e14cbee4	48	#define EDID_TIMING_VFREQ_SHIFT 0
0454beab MD	49	#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
0454beab MD	50
f453ba04 DA	51	struct std_timing {
f453ba04 DA	52	u8 hsize; /* need to multiply by 8 then add 248 */
0454beab	53	u8 vfreq_aspect;
f453ba04 DA	54	} __attribute__((packed));
f453ba04 DA	55
e14cbee4 MD	56	#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
e14cbee4 MD	57	#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
0454beab	58	#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
e14cbee4 MD	59	#define DRM_EDID_PT_STEREO (1 << 5)
e14cbee4 MD	60	#define DRM_EDID_PT_INTERLACED (1 << 7)
0454beab	61
f453ba04 DA	62	/* If detailed data is pixel timing */
	63	struct detailed_pixel_timing {
	64	u8 hactive_lo;
	65	u8 hblank_lo;
0454beab	66	u8 hactive_hblank_hi;
f453ba04 DA	67	u8 vactive_lo;
f453ba04 DA	68	u8 vblank_lo;
0454beab	69	u8 vactive_vblank_hi;
f453ba04 DA	70	u8 hsync_offset_lo;
f453ba04 DA	71	u8 hsync_pulse_width_lo;
0454beab MD	72	u8 vsync_offset_pulse_width_lo;
0454beab MD	73	u8 hsync_vsync_offset_pulse_width_hi;
f453ba04 DA	74	u8 width_mm_lo;
f453ba04 DA	75	u8 height_mm_lo;
0454beab	76	u8 width_height_mm_hi;
f453ba04 DA	77	u8 hborder;
f453ba04 DA	78	u8 vborder;
0454beab	79	u8 misc;
f453ba04 DA	80	} __attribute__((packed));
	81
	82	/* If it's not pixel timing, it'll be one of the below */
	83	struct detailed_data_string {
	84	u8 str[13];
	85	} __attribute__((packed));
	86
	87	struct detailed_data_monitor_range {
	88	u8 min_vfreq;
	89	u8 max_vfreq;
	90	u8 min_hfreq_khz;
	91	u8 max_hfreq_khz;
	92	u8 pixel_clock_mhz; /* need to multiply by 10 */
eeefa4be AJ	93	u8 flags;
	94	union {
	95	struct {
	96	u8 reserved;
	97	u8 hfreq_start_khz; /* need to multiply by 2 */
	98	u8 c; /* need to divide by 2 */
	99	__le16 m;
	100	u8 k;
	101	u8 j; /* need to divide by 2 */
8353e6c6	102	} __attribute__((packed)) gtf2;
eeefa4be AJ	103	struct {
	104	u8 version;
	105	u8 data1; /* high 6 bits: extra clock resolution */
	106	u8 data2; /* plus low 2 of above: max hactive */
	107	u8 supported_aspects;
	108	u8 flags; /* preferred aspect and blanking support */
	109	u8 supported_scalings;
	110	u8 preferred_refresh;
8353e6c6	111	} __attribute__((packed)) cvt;
eeefa4be	112	} formula;
f453ba04 DA	113	} __attribute__((packed));
	114
	115	struct detailed_data_wpindex {
e14cbee4	116	u8 white_yx_lo; /* Lower 2 bits each */
f453ba04 DA	117	u8 white_x_hi;
	118	u8 white_y_hi;
	119	u8 gamma; /* need to divide by 100 then add 1 */
	120	} __attribute__((packed));
	121
	122	struct detailed_data_color_point {
	123	u8 windex1;
	124	u8 wpindex1[3];
	125	u8 windex2;
	126	u8 wpindex2[3];
	127	} __attribute__((packed));
	128
9340d8cf AJ	129	struct cvt_timing {
	130	u8 code[3];
	131	} __attribute__((packed));
	132
f453ba04 DA	133	struct detailed_non_pixel {
	134	u8 pad1;
	135	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
	136	fb=color point data, fa=standard timing data,
	137	f9=undefined, f8=mfg. reserved */
	138	u8 pad2;
	139	union {
	140	struct detailed_data_string str;
	141	struct detailed_data_monitor_range range;
	142	struct detailed_data_wpindex color;
96525a2f	143	struct std_timing timings[6];
9340d8cf	144	struct cvt_timing cvt[4];
f453ba04 DA	145	} data;
	146	} __attribute__((packed));
	147
2dbdc52c AJ	148	#define EDID_DETAIL_EST_TIMINGS 0xf7
	149	#define EDID_DETAIL_CVT_3BYTE 0xf8
	150	#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
f453ba04 DA	151	#define EDID_DETAIL_STD_MODES 0xfa
	152	#define EDID_DETAIL_MONITOR_CPDATA 0xfb
	153	#define EDID_DETAIL_MONITOR_NAME 0xfc
	154	#define EDID_DETAIL_MONITOR_RANGE 0xfd
	155	#define EDID_DETAIL_MONITOR_STRING 0xfe
	156	#define EDID_DETAIL_MONITOR_SERIAL 0xff
	157
	158	struct detailed_timing {
0454beab	159	__le16 pixel_clock; /* need to multiply by 10 KHz */
f453ba04 DA	160	union {
	161	struct detailed_pixel_timing pixel_data;
	162	struct detailed_non_pixel other_data;
	163	} data;
	164	} __attribute__((packed));
	165
e14cbee4 MD	166	#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
	167	#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
	168	#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
0454beab	169	#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
e14cbee4 MD	170	#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
e14cbee4 MD	171	#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
3b11228b JB	172	#define DRM_EDID_INPUT_DIGITAL (1 << 7)
	173	#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
	174	#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
	175	#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
	176	#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
	177	#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
	178	#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
	179	#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
	180	#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
	181	#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
	182	#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
	183	#define DRM_EDID_DIGITAL_TYPE_DVI (1)
	184	#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
	185	#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
	186	#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
	187	#define DRM_EDID_DIGITAL_TYPE_DP (5)
0454beab	188
e14cbee4 MD	189	#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
	190	#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
	191	#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
da05a5a7	192	/* If analog */
0454beab	193	#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
da05a5a7 JB	194	/* If digital */
	195	#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
	196	#define DRM_EDID_FEATURE_RGB (0 << 3)
	197	#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
	198	#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
	199	#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
	200
e14cbee4 MD	201	#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
	202	#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
	203	#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
0454beab	204
d0c94692 MK	205	#define DRM_EDID_HDMI_DC_48 (1 << 6)
	206	#define DRM_EDID_HDMI_DC_36 (1 << 5)
	207	#define DRM_EDID_HDMI_DC_30 (1 << 4)
	208	#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
	209
babc9493 JN	210	/* ELD Header Block */
	211	#define DRM_ELD_HEADER_BLOCK_SIZE 4
	212
	213	#define DRM_ELD_VER 0
	214	# define DRM_ELD_VER_SHIFT 3
	215	# define DRM_ELD_VER_MASK (0x1f << 3)
	216
	217	#define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
	218
	219	/* ELD Baseline Block for ELD_Ver == 2 */
	220	#define DRM_ELD_CEA_EDID_VER_MNL 4
	221	# define DRM_ELD_CEA_EDID_VER_SHIFT 5
	222	# define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
	223	# define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
	224	# define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
	225	# define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
	226	# define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
	227	# define DRM_ELD_MNL_SHIFT 0
	228	# define DRM_ELD_MNL_MASK (0x1f << 0)
	229
	230	#define DRM_ELD_SAD_COUNT_CONN_TYPE 5
	231	# define DRM_ELD_SAD_COUNT_SHIFT 4
	232	# define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
	233	# define DRM_ELD_CONN_TYPE_SHIFT 2
	234	# define DRM_ELD_CONN_TYPE_MASK (3 << 2)
	235	# define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
	236	# define DRM_ELD_CONN_TYPE_DP (1 << 2)
	237	# define DRM_ELD_SUPPORTS_AI (1 << 1)
	238	# define DRM_ELD_SUPPORTS_HDCP (1 << 0)
	239
	240	#define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
	241	# define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
	242
	243	#define DRM_ELD_SPEAKER 7
	244	# define DRM_ELD_SPEAKER_RLRC (1 << 6)
	245	# define DRM_ELD_SPEAKER_FLRC (1 << 5)
	246	# define DRM_ELD_SPEAKER_RC (1 << 4)
	247	# define DRM_ELD_SPEAKER_RLR (1 << 3)
	248	# define DRM_ELD_SPEAKER_FC (1 << 2)
	249	# define DRM_ELD_SPEAKER_LFE (1 << 1)
	250	# define DRM_ELD_SPEAKER_FLR (1 << 0)
	251
	252	#define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
	253	# define DRM_ELD_PORT_ID_LEN 8
	254
	255	#define DRM_ELD_MANUFACTURER_NAME0 16
	256	#define DRM_ELD_MANUFACTURER_NAME1 17
	257
	258	#define DRM_ELD_PRODUCT_CODE0 18
	259	#define DRM_ELD_PRODUCT_CODE1 19
	260
	261	#define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
	262
	263	#define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
	264
f453ba04 DA	265	struct edid {
	266	u8 header[8];
	267	/* Vendor & product info */
	268	u8 mfg_id[2];
	269	u8 prod_code[2];
	270	u32 serial; /* FIXME: byte order */
	271	u8 mfg_week;
	272	u8 mfg_year;
	273	/* EDID version */
	274	u8 version;
	275	u8 revision;
	276	/* Display info: */
0454beab	277	u8 input;
f453ba04 DA	278	u8 width_cm;
	279	u8 height_cm;
	280	u8 gamma;
0454beab	281	u8 features;
f453ba04 DA	282	/* Color characteristics */
	283	u8 red_green_lo;
	284	u8 black_white_lo;
	285	u8 red_x;
	286	u8 red_y;
	287	u8 green_x;
	288	u8 green_y;
	289	u8 blue_x;
	290	u8 blue_y;
	291	u8 white_x;
	292	u8 white_y;
	293	/* Est. timings and mfg rsvd timings*/
	294	struct est_timings established_timings;
	295	/* Standard timings 1-8*/
	296	struct std_timing standard_timings[8];
	297	/* Detailing timings 1-4 */
	298	struct detailed_timing detailed_timings[4];
	299	/* Number of 128 byte ext. blocks */
	300	u8 extensions;
	301	/* Checksum */
	302	u8 checksum;
	303	} __attribute__((packed));
	304
f453ba04 DA	305	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
f453ba04 DA	306
fe214163 RM	307	/* Short Audio Descriptor */
	308	struct cea_sad {
	309	u8 format;
	310	u8 channels; /* max number of channels - 1 */
	311	u8 freq;
	312	u8 byte2; /* meaning depends on format */
	313	};
	314
76adaa34 WF	315	struct drm_encoder;
	316	struct drm_connector;
	317	struct drm_display_mode;
10a85120	318	struct hdmi_avi_infoframe;
83dd0008	319	struct hdmi_vendor_infoframe;
10a85120	320
76adaa34	321	void drm_edid_to_eld(struct drm_connector connector, struct edid edid);
fe214163	322	int drm_edid_to_sad(struct edid edid, struct cea_sad *sads);
d105f476	323	int drm_edid_to_speaker_allocation(struct edid edid, u8 *sadb);
76adaa34 WF	324	int drm_av_sync_delay(struct drm_connector *connector,
	325	struct drm_display_mode *mode);
	326	struct drm_connector drm_select_eld(struct drm_encoder encoder,
	327	struct drm_display_mode *mode);
da0df92b	328	int drm_load_edid_firmware(struct drm_connector *connector);
76adaa34	329
10a85120 TR	330	int
	331	drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
	332	const struct drm_display_mode *mode);
83dd0008 LD	333	int
	334	drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
	335	const struct drm_display_mode *mode);
10a85120	336
babc9493 JN	337	/**
	338	* drm_eld_mnl - Get ELD monitor name length in bytes.
	339	* @eld: pointer to an eld memory structure with mnl set
	340	*/
	341	static inline int drm_eld_mnl(const uint8_t *eld)
	342	{
	343	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
	344	}
	345
	346	/**
	347	* drm_eld_sad_count - Get ELD SAD count.
	348	* @eld: pointer to an eld memory structure with sad_count set
	349	*/
	350	static inline int drm_eld_sad_count(const uint8_t *eld)
	351	{
	352	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
	353	DRM_ELD_SAD_COUNT_SHIFT;
	354	}
	355
	356	/**
	357	* drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
	358	* @eld: pointer to an eld memory structure with mnl and sad_count set
	359	*
	360	* This is a helper for determining the payload size of the baseline block, in
	361	* bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
	362	*/
	363	static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
	364	{
	365	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
	366	drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
	367	}
	368
	369	/**
	370	* drm_eld_size - Get ELD size in bytes
	371	* @eld: pointer to a complete eld memory structure
	372	*
	373	* The returned value does not include the vendor block. It's vendor specific,
	374	* and comprises of the remaining bytes in the ELD memory buffer after
	375	* drm_eld_size() bytes of header and baseline block.
	376	*
	377	* The returned value is guaranteed to be a multiple of 4.
	378	*/
	379	static inline int drm_eld_size(const uint8_t *eld)
	380	{
	381	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
	382	}
	383
f453ba04	384	#endif /* __DRM_EDID_H__ */