[mirror_ubuntu-bionic-kernel.git] / include / drm / drm_mode.h

/*
 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
 * Copyright (c) 2008 Red Hat Inc.
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * Copyright (c) 2007-2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef _DRM_MODE_H
#define _DRM_MODE_H

#include <linux/types.h>

#define DRM_DISPLAY_INFO_LEN	32
#define DRM_CONNECTOR_NAME_LEN	32
#define DRM_DISPLAY_MODE_LEN	32
#define DRM_PROP_NAME_LEN	32

#define DRM_MODE_TYPE_BUILTIN	(1<<0)
#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_PREFERRED	(1<<3)
#define DRM_MODE_TYPE_DEFAULT	(1<<4)
#define DRM_MODE_TYPE_USERDEF	(1<<5)
#define DRM_MODE_TYPE_DRIVER	(1<<6)

/* Video mode flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_FLAG_PHSYNC	(1<<0)
#define DRM_MODE_FLAG_NHSYNC	(1<<1)
#define DRM_MODE_FLAG_PVSYNC	(1<<2)
#define DRM_MODE_FLAG_NVSYNC	(1<<3)
#define DRM_MODE_FLAG_INTERLACE	(1<<4)
#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
#define DRM_MODE_FLAG_CSYNC	(1<<6)
#define DRM_MODE_FLAG_PCSYNC	(1<<7)
#define DRM_MODE_FLAG_NCSYNC	(1<<8)
#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
#define DRM_MODE_FLAG_BCAST	(1<<10)
#define DRM_MODE_FLAG_PIXMUX	(1<<11)
#define DRM_MODE_FLAG_DBLCLK	(1<<12)
#define DRM_MODE_FLAG_CLKDIV2	(1<<13)

/* DPMS flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_DPMS_ON	0
#define DRM_MODE_DPMS_STANDBY	1
#define DRM_MODE_DPMS_SUSPEND	2
#define DRM_MODE_DPMS_OFF	3

/* Scaling mode options */
#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
					     software can still scale) */
#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */

/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF	0
#define DRM_MODE_DITHERING_ON	1
#define DRM_MODE_DITHERING_AUTO 2

/* Dirty info options */
#define DRM_MODE_DIRTY_OFF      0
#define DRM_MODE_DIRTY_ON       1
#define DRM_MODE_DIRTY_ANNOTATE 2

struct drm_mode_modeinfo {
	__u32 clock;
	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;

	__u32 vrefresh;

	__u32 flags;
	__u32 type;
	char name[DRM_DISPLAY_MODE_LEN];
};

struct drm_mode_card_res {
	__u64 fb_id_ptr;
	__u64 crtc_id_ptr;
	__u64 connector_id_ptr;
	__u64 encoder_id_ptr;
	__u32 count_fbs;
	__u32 count_crtcs;
	__u32 count_connectors;
	__u32 count_encoders;
	__u32 min_width, max_width;
	__u32 min_height, max_height;
};

struct drm_mode_crtc {
	__u64 set_connectors_ptr;
	__u32 count_connectors;

	__u32 crtc_id; /**< Id */
	__u32 fb_id; /**< Id of framebuffer */

	__u32 x, y; /**< Position on the frameuffer */

	__u32 gamma_size;
	__u32 mode_valid;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_PRESENT_TOP_FIELD	(1<<0)
#define DRM_MODE_PRESENT_BOTTOM_FIELD	(1<<1)

/* Planes blend with or override other bits on the CRTC */
struct drm_mode_set_plane {
	__u32 plane_id;
	__u32 crtc_id;
	__u32 fb_id; /* fb object contains surface format type */
	__u32 flags; /* see above flags */

	/* Signed dest location allows it to be partially off screen */
	__s32 crtc_x, crtc_y;
	__u32 crtc_w, crtc_h;

	/* Source values are 16.16 fixed point */
	__u32 src_x, src_y;
	__u32 src_h, src_w;
};

struct drm_mode_get_plane {
	__u32 plane_id;

	__u32 crtc_id;
	__u32 fb_id;

	__u32 possible_crtcs;
	__u32 gamma_size;

	__u32 count_format_types;
	__u64 format_type_ptr;
};

struct drm_mode_get_plane_res {
	__u64 plane_id_ptr;
	__u32 count_planes;
};

#define DRM_MODE_ENCODER_NONE	0
#define DRM_MODE_ENCODER_DAC	1
#define DRM_MODE_ENCODER_TMDS	2
#define DRM_MODE_ENCODER_LVDS	3
#define DRM_MODE_ENCODER_TVDAC	4
#define DRM_MODE_ENCODER_VIRTUAL 5

struct drm_mode_get_encoder {
	__u32 encoder_id;
	__u32 encoder_type;

	__u32 crtc_id; /**< Id of crtc */

	__u32 possible_crtcs;
	__u32 possible_clones;
};

/* This is for connectors with multiple signal types. */
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
#define DRM_MODE_SUBCONNECTOR_Automatic	0
#define DRM_MODE_SUBCONNECTOR_Unknown	0
#define DRM_MODE_SUBCONNECTOR_DVID	3
#define DRM_MODE_SUBCONNECTOR_DVIA	4
#define DRM_MODE_SUBCONNECTOR_Composite	5
#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
#define DRM_MODE_SUBCONNECTOR_Component	8
#define DRM_MODE_SUBCONNECTOR_SCART	9

#define DRM_MODE_CONNECTOR_Unknown	0
#define DRM_MODE_CONNECTOR_VGA		1
#define DRM_MODE_CONNECTOR_DVII		2
#define DRM_MODE_CONNECTOR_DVID		3
#define DRM_MODE_CONNECTOR_DVIA		4
#define DRM_MODE_CONNECTOR_Composite	5
#define DRM_MODE_CONNECTOR_SVIDEO	6
#define DRM_MODE_CONNECTOR_LVDS		7
#define DRM_MODE_CONNECTOR_Component	8
#define DRM_MODE_CONNECTOR_9PinDIN	9
#define DRM_MODE_CONNECTOR_DisplayPort	10
#define DRM_MODE_CONNECTOR_HDMIA	11
#define DRM_MODE_CONNECTOR_HDMIB	12
#define DRM_MODE_CONNECTOR_TV		13
#define DRM_MODE_CONNECTOR_eDP		14
#define DRM_MODE_CONNECTOR_VIRTUAL      15

struct drm_mode_get_connector {

	__u64 encoders_ptr;
	__u64 modes_ptr;
	__u64 props_ptr;
	__u64 prop_values_ptr;

	__u32 count_modes;
	__u32 count_props;
	__u32 count_encoders;

	__u32 encoder_id; /**< Current Encoder */
	__u32 connector_id; /**< Id */
	__u32 connector_type;
	__u32 connector_type_id;

	__u32 connection;
	__u32 mm_width, mm_height; /**< HxW in millimeters */
	__u32 subpixel;
};

#define DRM_MODE_PROP_PENDING	(1<<0)
#define DRM_MODE_PROP_RANGE	(1<<1)
#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
#define DRM_MODE_PROP_BLOB	(1<<4)

struct drm_mode_property_enum {
	__u64 value;
	char name[DRM_PROP_NAME_LEN];
};

struct drm_mode_get_property {
	__u64 values_ptr; /* values and blob lengths */
	__u64 enum_blob_ptr; /* enum and blob id ptrs */

	__u32 prop_id;
	__u32 flags;
	char name[DRM_PROP_NAME_LEN];

	__u32 count_values;
	__u32 count_enum_blobs;
};

struct drm_mode_connector_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 connector_id;
};

struct drm_mode_get_blob {
	__u32 blob_id;
	__u32 length;
	__u64 data;
};

struct drm_mode_fb_cmd {
	__u32 fb_id;
	__u32 width, height;
	__u32 pitch;
	__u32 bpp;
	__u32 depth;
	/* driver specific handle */
	__u32 handle;
};

#define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */

struct drm_mode_fb_cmd2 {
	__u32 fb_id;
	__u32 width, height;
	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	__u32 flags; /* see above flags */

	/*
	 * In case of planar formats, this ioctl allows up to 4
	 * buffer objects with offets and pitches per plane.
	 * The pitch and offset order is dictated by the fourcc,
	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	 *
	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
	 *   followed by an interleaved U/V plane containing
	 *   8 bit 2x2 subsampled colour difference samples.
	 *
	 * So it would consist of Y as offset[0] and UV as
	 * offeset[1].  Note that offset[0] will generally
	 * be 0.
	 */
	__u32 handles[4];
	__u32 pitches[4]; /* pitch for each plane */
	__u32 offsets[4]; /* offset of each plane */
};

#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
#define DRM_MODE_FB_DIRTY_FLAGS         0x03

#define DRM_MODE_FB_DIRTY_MAX_CLIPS     256

/*
 * Mark a region of a framebuffer as dirty.
 *
 * Some hardware does not automatically update display contents
 * as a hardware or software draw to a framebuffer. This ioctl
 * allows userspace to tell the kernel and the hardware what
 * regions of the framebuffer have changed.
 *
 * The kernel or hardware is free to update more then just the
 * region specified by the clip rects. The kernel or hardware
 * may also delay and/or coalesce several calls to dirty into a
 * single update.
 *
 * Userspace may annotate the updates, the annotates are a
 * promise made by the caller that the change is either a copy
 * of pixels or a fill of a single color in the region specified.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 * the number of updated regions are half of num_clips given,
 * where the clip rects are paired in src and dst. The width and
 * height of each one of the pairs must match.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 * promises that the region specified of the clip rects is filled
 * completely with a single color as given in the color argument.
 */

struct drm_mode_fb_dirty_cmd {
	__u32 fb_id;
	__u32 flags;
	__u32 color;
	__u32 num_clips;
	__u64 clips_ptr;
};

struct drm_mode_mode_cmd {
	__u32 connector_id;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_CURSOR_BO	(1<<0)
#define DRM_MODE_CURSOR_MOVE	(1<<1)

/*
 * depending on the value in flags different members are used.
 *
 * CURSOR_BO uses
 *    crtc
 *    width
 *    height
 *    handle - if 0 turns the cursor of
 *
 * CURSOR_MOVE uses
 *    crtc
 *    x
 *    y
 */
struct drm_mode_cursor {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
};

struct drm_mode_crtc_lut {
	__u32 crtc_id;
	__u32 gamma_size;

	/* pointers to arrays */
	__u64 red;
	__u64 green;
	__u64 blue;
};

#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT

/*
 * Request a page flip on the specified crtc.
 *
 * This ioctl will ask KMS to schedule a page flip for the specified
 * crtc.  Once any pending rendering targeting the specified fb (as of
 * ioctl time) has completed, the crtc will be reprogrammed to display
 * that fb after the next vertical refresh.  The ioctl returns
 * immediately, but subsequent rendering to the current fb will block
 * in the execbuffer ioctl until the page flip happens.  If a page
 * flip is already pending as the ioctl is called, EBUSY will be
 * returned.
 *
 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
 * request that drm sends back a vblank event (see drm.h: struct
 * drm_event_vblank) when the page flip is done.  The user_data field
 * passed in with this ioctl will be returned as the user_data field
 * in the vblank event struct.
 *
 * The reserved field must be zero until we figure out something
 * clever to use it for.
 */

struct drm_mode_crtc_page_flip {
	__u32 crtc_id;
	__u32 fb_id;
	__u32 flags;
	__u32 reserved;
	__u64 user_data;
};

/* create a dumb scanout buffer */
struct drm_mode_create_dumb {
	uint32_t height;
	uint32_t width;
	uint32_t bpp;
	uint32_t flags;
	/* handle, pitch, size will be returned */
	uint32_t handle;
	uint32_t pitch;
	uint64_t size;
};

/* set up for mmap of a dumb scanout buffer */
struct drm_mode_map_dumb {
	/** Handle for the object being mapped. */
	__u32 handle;
	__u32 pad;
	/**
	 * Fake offset to use for subsequent mmap call
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 offset;
};

struct drm_mode_destroy_dumb {
	uint32_t handle;
};

#endif
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
	3	* Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
	4	* Copyright (c) 2008 Red Hat Inc.
	5	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
	6	* Copyright (c) 2007-2008 Intel Corporation
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	24	* IN THE SOFTWARE.
	25	*/
	26
	27	#ifndef _DRM_MODE_H
	28	#define _DRM_MODE_H
	29
10db4e1e BP	30	#include <linux/types.h>
10db4e1e BP	31
e0c8463a JB	32	#define DRM_DISPLAY_INFO_LEN 32
	33	#define DRM_CONNECTOR_NAME_LEN 32
	34	#define DRM_DISPLAY_MODE_LEN 32
	35	#define DRM_PROP_NAME_LEN 32
f453ba04 DA	36
	37	#define DRM_MODE_TYPE_BUILTIN (1<<0)
	38	#define DRM_MODE_TYPE_CLOCK_C ((1<<1) \| DRM_MODE_TYPE_BUILTIN)
	39	#define DRM_MODE_TYPE_CRTC_C ((1<<2) \| DRM_MODE_TYPE_BUILTIN)
	40	#define DRM_MODE_TYPE_PREFERRED (1<<3)
	41	#define DRM_MODE_TYPE_DEFAULT (1<<4)
	42	#define DRM_MODE_TYPE_USERDEF (1<<5)
	43	#define DRM_MODE_TYPE_DRIVER (1<<6)
	44
	45	/* Video mode flags */
	46	/* bit compatible with the xorg definitions. */
	47	#define DRM_MODE_FLAG_PHSYNC (1<<0)
	48	#define DRM_MODE_FLAG_NHSYNC (1<<1)
	49	#define DRM_MODE_FLAG_PVSYNC (1<<2)
	50	#define DRM_MODE_FLAG_NVSYNC (1<<3)
	51	#define DRM_MODE_FLAG_INTERLACE (1<<4)
	52	#define DRM_MODE_FLAG_DBLSCAN (1<<5)
	53	#define DRM_MODE_FLAG_CSYNC (1<<6)
	54	#define DRM_MODE_FLAG_PCSYNC (1<<7)
	55	#define DRM_MODE_FLAG_NCSYNC (1<<8)
	56	#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
	57	#define DRM_MODE_FLAG_BCAST (1<<10)
	58	#define DRM_MODE_FLAG_PIXMUX (1<<11)
	59	#define DRM_MODE_FLAG_DBLCLK (1<<12)
	60	#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
	61
	62	/* DPMS flags */
	63	/* bit compatible with the xorg definitions. */
e0c8463a JB	64	#define DRM_MODE_DPMS_ON 0
	65	#define DRM_MODE_DPMS_STANDBY 1
	66	#define DRM_MODE_DPMS_SUSPEND 2
	67	#define DRM_MODE_DPMS_OFF 3
f453ba04 DA	68
f453ba04 DA	69	/* Scaling mode options */
53bd8389 JB	70	#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
	71	software can still scale) */
	72	#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
	73	#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
	74	#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
f453ba04 DA	75
f453ba04 DA	76	/* Dithering mode options */
e0c8463a JB	77	#define DRM_MODE_DITHERING_OFF 0
e0c8463a JB	78	#define DRM_MODE_DITHERING_ON 1
92897b5c	79	#define DRM_MODE_DITHERING_AUTO 2
f453ba04	80
884840aa JB	81	/* Dirty info options */
	82	#define DRM_MODE_DIRTY_OFF 0
	83	#define DRM_MODE_DIRTY_ON 1
	84	#define DRM_MODE_DIRTY_ANNOTATE 2
	85
f453ba04	86	struct drm_mode_modeinfo {
1d7f83d5 AB	87	__u32 clock;
	88	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	89	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
f453ba04	90
fa5829b3	91	__u32 vrefresh;
f453ba04	92
1d7f83d5 AB	93	__u32 flags;
1d7f83d5 AB	94	__u32 type;
f453ba04 DA	95	char name[DRM_DISPLAY_MODE_LEN];
	96	};
	97
	98	struct drm_mode_card_res {
1d7f83d5 AB	99	__u64 fb_id_ptr;
	100	__u64 crtc_id_ptr;
	101	__u64 connector_id_ptr;
	102	__u64 encoder_id_ptr;
	103	__u32 count_fbs;
	104	__u32 count_crtcs;
	105	__u32 count_connectors;
	106	__u32 count_encoders;
	107	__u32 min_width, max_width;
	108	__u32 min_height, max_height;
f453ba04 DA	109	};
	110
	111	struct drm_mode_crtc {
1d7f83d5 AB	112	__u64 set_connectors_ptr;
1d7f83d5 AB	113	__u32 count_connectors;
f453ba04	114
1d7f83d5 AB	115	__u32 crtc_id; /*< Id /
1d7f83d5 AB	116	__u32 fb_id; /*< Id of framebuffer /
f453ba04	117
1d7f83d5	118	__u32 x, y; /*< Position on the frameuffer /
f453ba04	119
1d7f83d5 AB	120	__u32 gamma_size;
1d7f83d5 AB	121	__u32 mode_valid;
f453ba04 DA	122	struct drm_mode_modeinfo mode;
	123	};
	124
8cf5c917 JB	125	#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
	126	#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
	127
	128	/* Planes blend with or override other bits on the CRTC */
	129	struct drm_mode_set_plane {
	130	__u32 plane_id;
	131	__u32 crtc_id;
	132	__u32 fb_id; /* fb object contains surface format type */
	133	__u32 flags; /* see above flags */
	134
	135	/* Signed dest location allows it to be partially off screen */
	136	__s32 crtc_x, crtc_y;
	137	__u32 crtc_w, crtc_h;
	138
	139	/* Source values are 16.16 fixed point */
	140	__u32 src_x, src_y;
	141	__u32 src_h, src_w;
	142	};
	143
	144	struct drm_mode_get_plane {
	145	__u32 plane_id;
	146
	147	__u32 crtc_id;
	148	__u32 fb_id;
	149
	150	__u32 possible_crtcs;
	151	__u32 gamma_size;
	152
	153	__u32 count_format_types;
	154	__u64 format_type_ptr;
	155	};
	156
	157	struct drm_mode_get_plane_res {
	158	__u64 plane_id_ptr;
	159	__u32 count_planes;
	160	};
	161
	162	#define DRM_MODE_ENCODER_NONE 0
	163	#define DRM_MODE_ENCODER_DAC 1
	164	#define DRM_MODE_ENCODER_TMDS 2
	165	#define DRM_MODE_ENCODER_LVDS 3
	166	#define DRM_MODE_ENCODER_TVDAC 4
a7331e5c	167	#define DRM_MODE_ENCODER_VIRTUAL 5
f453ba04 DA	168
f453ba04 DA	169	struct drm_mode_get_encoder {
1d7f83d5 AB	170	__u32 encoder_id;
1d7f83d5 AB	171	__u32 encoder_type;
f453ba04	172
1d7f83d5	173	__u32 crtc_id; /*< Id of crtc /
f453ba04	174
1d7f83d5 AB	175	__u32 possible_crtcs;
1d7f83d5 AB	176	__u32 possible_clones;
f453ba04 DA	177	};
	178
	179	/* This is for connectors with multiple signal types. */
	180	/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
e0c8463a JB	181	#define DRM_MODE_SUBCONNECTOR_Automatic 0
	182	#define DRM_MODE_SUBCONNECTOR_Unknown 0
	183	#define DRM_MODE_SUBCONNECTOR_DVID 3
	184	#define DRM_MODE_SUBCONNECTOR_DVIA 4
	185	#define DRM_MODE_SUBCONNECTOR_Composite 5
	186	#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
	187	#define DRM_MODE_SUBCONNECTOR_Component 8
aeaa1ad3	188	#define DRM_MODE_SUBCONNECTOR_SCART 9
e0c8463a JB	189
	190	#define DRM_MODE_CONNECTOR_Unknown 0
	191	#define DRM_MODE_CONNECTOR_VGA 1
	192	#define DRM_MODE_CONNECTOR_DVII 2
	193	#define DRM_MODE_CONNECTOR_DVID 3
	194	#define DRM_MODE_CONNECTOR_DVIA 4
	195	#define DRM_MODE_CONNECTOR_Composite 5
	196	#define DRM_MODE_CONNECTOR_SVIDEO 6
	197	#define DRM_MODE_CONNECTOR_LVDS 7
	198	#define DRM_MODE_CONNECTOR_Component 8
	199	#define DRM_MODE_CONNECTOR_9PinDIN 9
	200	#define DRM_MODE_CONNECTOR_DisplayPort 10
	201	#define DRM_MODE_CONNECTOR_HDMIA 11
	202	#define DRM_MODE_CONNECTOR_HDMIB 12
74bd3c26	203	#define DRM_MODE_CONNECTOR_TV 13
7970e677	204	#define DRM_MODE_CONNECTOR_eDP 14
a7331e5c	205	#define DRM_MODE_CONNECTOR_VIRTUAL 15
f453ba04 DA	206
	207	struct drm_mode_get_connector {
	208
1d7f83d5 AB	209	__u64 encoders_ptr;
	210	__u64 modes_ptr;
	211	__u64 props_ptr;
	212	__u64 prop_values_ptr;
f453ba04	213
1d7f83d5 AB	214	__u32 count_modes;
	215	__u32 count_props;
	216	__u32 count_encoders;
f453ba04	217
1d7f83d5 AB	218	__u32 encoder_id; /*< Current Encoder /
	219	__u32 connector_id; /*< Id /
	220	__u32 connector_type;
	221	__u32 connector_type_id;
f453ba04	222
1d7f83d5 AB	223	__u32 connection;
	224	__u32 mm_width, mm_height; /*< HxW in millimeters /
	225	__u32 subpixel;
f453ba04 DA	226	};
f453ba04 DA	227
e0c8463a JB	228	#define DRM_MODE_PROP_PENDING (1<<0)
	229	#define DRM_MODE_PROP_RANGE (1<<1)
	230	#define DRM_MODE_PROP_IMMUTABLE (1<<2)
	231	#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
	232	#define DRM_MODE_PROP_BLOB (1<<4)
f453ba04 DA	233
f453ba04 DA	234	struct drm_mode_property_enum {
1d7f83d5	235	__u64 value;
e0c8463a	236	char name[DRM_PROP_NAME_LEN];
f453ba04 DA	237	};
	238
	239	struct drm_mode_get_property {
1d7f83d5 AB	240	__u64 values_ptr; /* values and blob lengths */
1d7f83d5 AB	241	__u64 enum_blob_ptr; /* enum and blob id ptrs */
f453ba04	242
1d7f83d5 AB	243	__u32 prop_id;
1d7f83d5 AB	244	__u32 flags;
e0c8463a	245	char name[DRM_PROP_NAME_LEN];
f453ba04	246
1d7f83d5 AB	247	__u32 count_values;
1d7f83d5 AB	248	__u32 count_enum_blobs;
f453ba04 DA	249	};
	250
	251	struct drm_mode_connector_set_property {
1d7f83d5 AB	252	__u64 value;
	253	__u32 prop_id;
	254	__u32 connector_id;
f453ba04 DA	255	};
	256
	257	struct drm_mode_get_blob {
1d7f83d5 AB	258	__u32 blob_id;
	259	__u32 length;
	260	__u64 data;
f453ba04 DA	261	};
	262
	263	struct drm_mode_fb_cmd {
1d7f83d5 AB	264	__u32 fb_id;
	265	__u32 width, height;
	266	__u32 pitch;
	267	__u32 bpp;
	268	__u32 depth;
e0c8463a	269	/* driver specific handle */
1d7f83d5	270	__u32 handle;
f453ba04 DA	271	};
f453ba04 DA	272
cc5b6f00	273	#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
308e5bcb JB	274
	275	struct drm_mode_fb_cmd2 {
	276	__u32 fb_id;
	277	__u32 width, height;
	278	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	279	__u32 flags; /* see above flags */
	280
	281	/*
	282	* In case of planar formats, this ioctl allows up to 4
	283	* buffer objects with offets and pitches per plane.
	284	* The pitch and offset order is dictated by the fourcc,
	285	* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	286	*
	287	* YUV 4:2:0 image with a plane of 8 bit Y samples
	288	* followed by an interleaved U/V plane containing
	289	* 8 bit 2x2 subsampled colour difference samples.
	290	*
	291	* So it would consist of Y as offset[0] and UV as
	292	* offeset[1]. Note that offset[0] will generally
	293	* be 0.
	294	*/
	295	__u32 handles[4];
	296	__u32 pitches[4]; /* pitch for each plane */
	297	__u32 offsets[4]; /* offset of each plane */
	298	};
	299
884840aa JB	300	#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
	301	#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
	302	#define DRM_MODE_FB_DIRTY_FLAGS 0x03
	303
a5cd3351 XW	304	#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
a5cd3351 XW	305
884840aa JB	306	/*
	307	* Mark a region of a framebuffer as dirty.
	308	*
	309	* Some hardware does not automatically update display contents
	310	* as a hardware or software draw to a framebuffer. This ioctl
	311	* allows userspace to tell the kernel and the hardware what
	312	* regions of the framebuffer have changed.
	313	*
	314	* The kernel or hardware is free to update more then just the
	315	* region specified by the clip rects. The kernel or hardware
	316	* may also delay and/or coalesce several calls to dirty into a
	317	* single update.
	318	*
	319	* Userspace may annotate the updates, the annotates are a
	320	* promise made by the caller that the change is either a copy
	321	* of pixels or a fill of a single color in the region specified.
	322	*
	323	* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
	324	* the number of updated regions are half of num_clips given,
	325	* where the clip rects are paired in src and dst. The width and
	326	* height of each one of the pairs must match.
	327	*
	328	* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
	329	* promises that the region specified of the clip rects is filled
	330	* completely with a single color as given in the color argument.
	331	*/
	332
	333	struct drm_mode_fb_dirty_cmd {
	334	__u32 fb_id;
	335	__u32 flags;
	336	__u32 color;
	337	__u32 num_clips;
	338	__u64 clips_ptr;
	339	};
	340
f453ba04	341	struct drm_mode_mode_cmd {
1d7f83d5	342	__u32 connector_id;
f453ba04 DA	343	struct drm_mode_modeinfo mode;
	344	};
	345
e0c8463a JB	346	#define DRM_MODE_CURSOR_BO (1<<0)
e0c8463a JB	347	#define DRM_MODE_CURSOR_MOVE (1<<1)
f453ba04 DA	348
f453ba04 DA	349	/*
25985edc	350	* depending on the value in flags different members are used.
f453ba04 DA	351	*
	352	* CURSOR_BO uses
	353	* crtc
	354	* width
	355	* height
	356	* handle - if 0 turns the cursor of
	357	*
	358	* CURSOR_MOVE uses
	359	* crtc
	360	* x
	361	* y
	362	*/
	363	struct drm_mode_cursor {
1d7f83d5 AB	364	__u32 flags;
	365	__u32 crtc_id;
	366	__s32 x;
	367	__s32 y;
	368	__u32 width;
	369	__u32 height;
e0c8463a	370	/* driver specific handle */
1d7f83d5	371	__u32 handle;
f453ba04 DA	372	};
	373
	374	struct drm_mode_crtc_lut {
1d7f83d5 AB	375	__u32 crtc_id;
1d7f83d5 AB	376	__u32 gamma_size;
f453ba04 DA	377
f453ba04 DA	378	/* pointers to arrays */
1d7f83d5 AB	379	__u64 red;
	380	__u64 green;
	381	__u64 blue;
f453ba04 DA	382	};
f453ba04 DA	383
d91d8a3f KH	384	#define DRM_MODE_PAGE_FLIP_EVENT 0x01
	385	#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
	386
	387	/*
	388	* Request a page flip on the specified crtc.
	389	*
	390	* This ioctl will ask KMS to schedule a page flip for the specified
	391	* crtc. Once any pending rendering targeting the specified fb (as of
	392	* ioctl time) has completed, the crtc will be reprogrammed to display
	393	* that fb after the next vertical refresh. The ioctl returns
	394	* immediately, but subsequent rendering to the current fb will block
	395	* in the execbuffer ioctl until the page flip happens. If a page
	396	* flip is already pending as the ioctl is called, EBUSY will be
	397	* returned.
	398	*
	399	* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
	400	* request that drm sends back a vblank event (see drm.h: struct
	401	* drm_event_vblank) when the page flip is done. The user_data field
	402	* passed in with this ioctl will be returned as the user_data field
	403	* in the vblank event struct.
	404	*
	405	* The reserved field must be zero until we figure out something
	406	* clever to use it for.
	407	*/
	408
	409	struct drm_mode_crtc_page_flip {
	410	__u32 crtc_id;
	411	__u32 fb_id;
	412	__u32 flags;
	413	__u32 reserved;
	414	__u64 user_data;
	415	};
	416
ff72145b DA	417	/* create a dumb scanout buffer */
	418	struct drm_mode_create_dumb {
	419	uint32_t height;
	420	uint32_t width;
	421	uint32_t bpp;
	422	uint32_t flags;
	423	/* handle, pitch, size will be returned */
	424	uint32_t handle;
	425	uint32_t pitch;
	426	uint64_t size;
	427	};
	428
	429	/* set up for mmap of a dumb scanout buffer */
	430	struct drm_mode_map_dumb {
	431	/** Handle for the object being mapped. */
	432	__u32 handle;
	433	__u32 pad;
	434	/**
	435	* Fake offset to use for subsequent mmap call
	436	*
	437	* This is a fixed-size type for 32/64 compatibility.
	438	*/
	439	__u64 offset;
	440	};
	441
	442	struct drm_mode_destroy_dumb {
	443	uint32_t handle;
	444	};
	445
f453ba04	446	#endif