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0d6aa60b | 1 | /* |
bc54fd1a DA |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
0d6aa60b | 25 | */ |
bc54fd1a | 26 | |
1da177e4 LT |
27 | #ifndef _I915_DRM_H_ |
28 | #define _I915_DRM_H_ | |
29 | ||
1a95916f KH |
30 | #include "drm.h" |
31 | ||
1da177e4 LT |
32 | /* Please note that modifications to all structs defined here are |
33 | * subject to backwards-compatibility constraints. | |
34 | */ | |
1da177e4 LT |
35 | |
36 | /* Each region is a minimum of 16k, and there are at most 255 of them. | |
37 | */ | |
38 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
39 | * of chars for next/prev indices */ | |
40 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
41 | ||
42 | typedef struct _drm_i915_init { | |
43 | enum { | |
44 | I915_INIT_DMA = 0x01, | |
45 | I915_CLEANUP_DMA = 0x02, | |
46 | I915_RESUME_DMA = 0x03 | |
47 | } func; | |
48 | unsigned int mmio_offset; | |
49 | int sarea_priv_offset; | |
50 | unsigned int ring_start; | |
51 | unsigned int ring_end; | |
52 | unsigned int ring_size; | |
53 | unsigned int front_offset; | |
54 | unsigned int back_offset; | |
55 | unsigned int depth_offset; | |
56 | unsigned int w; | |
57 | unsigned int h; | |
58 | unsigned int pitch; | |
59 | unsigned int pitch_bits; | |
60 | unsigned int back_pitch; | |
61 | unsigned int depth_pitch; | |
62 | unsigned int cpp; | |
63 | unsigned int chipset; | |
64 | } drm_i915_init_t; | |
65 | ||
66 | typedef struct _drm_i915_sarea { | |
c60ce623 | 67 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
1da177e4 LT |
68 | int last_upload; /* last time texture was uploaded */ |
69 | int last_enqueue; /* last time a buffer was enqueued */ | |
70 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
71 | int ctxOwner; /* last context to upload state */ | |
72 | int texAge; | |
73 | int pf_enabled; /* is pageflipping allowed? */ | |
74 | int pf_active; | |
75 | int pf_current_page; /* which buffer is being displayed? */ | |
76 | int perf_boxes; /* performance boxes to be displayed */ | |
de227f5f DA |
77 | int width, height; /* screen size in pixels */ |
78 | ||
79 | drm_handle_t front_handle; | |
80 | int front_offset; | |
81 | int front_size; | |
82 | ||
83 | drm_handle_t back_handle; | |
84 | int back_offset; | |
85 | int back_size; | |
86 | ||
87 | drm_handle_t depth_handle; | |
88 | int depth_offset; | |
89 | int depth_size; | |
90 | ||
91 | drm_handle_t tex_handle; | |
92 | int tex_offset; | |
93 | int tex_size; | |
94 | int log_tex_granularity; | |
95 | int pitch; | |
96 | int rotation; /* 0, 90, 180 or 270 */ | |
97 | int rotated_offset; | |
98 | int rotated_size; | |
99 | int rotated_pitch; | |
100 | int virtualX, virtualY; | |
c29b669c AH |
101 | |
102 | unsigned int front_tiled; | |
103 | unsigned int back_tiled; | |
104 | unsigned int depth_tiled; | |
105 | unsigned int rotated_tiled; | |
106 | unsigned int rotated2_tiled; | |
376642cf | 107 | |
af6061af DA |
108 | int pipeA_x; |
109 | int pipeA_y; | |
110 | int pipeA_w; | |
111 | int pipeA_h; | |
112 | int pipeB_x; | |
113 | int pipeB_y; | |
114 | int pipeB_w; | |
115 | int pipeB_h; | |
dfef2459 DA |
116 | |
117 | /* fill out some space for old userspace triple buffer */ | |
118 | drm_handle_t unused_handle; | |
1d7f83d5 | 119 | __u32 unused1, unused2, unused3; |
dfef2459 DA |
120 | |
121 | /* buffer object handles for static buffers. May change | |
122 | * over the lifetime of the client. | |
123 | */ | |
1d7f83d5 AB |
124 | __u32 front_bo_handle; |
125 | __u32 back_bo_handle; | |
126 | __u32 unused_bo_handle; | |
127 | __u32 depth_bo_handle; | |
dfef2459 | 128 | |
1da177e4 LT |
129 | } drm_i915_sarea_t; |
130 | ||
dfef2459 DA |
131 | /* due to userspace building against these headers we need some compat here */ |
132 | #define planeA_x pipeA_x | |
133 | #define planeA_y pipeA_y | |
134 | #define planeA_w pipeA_w | |
135 | #define planeA_h pipeA_h | |
136 | #define planeB_x pipeB_x | |
137 | #define planeB_y pipeB_y | |
138 | #define planeB_w pipeB_w | |
139 | #define planeB_h pipeB_h | |
140 | ||
1da177e4 LT |
141 | /* Flags for perf_boxes |
142 | */ | |
143 | #define I915_BOX_RING_EMPTY 0x1 | |
144 | #define I915_BOX_FLIP 0x2 | |
145 | #define I915_BOX_WAIT 0x4 | |
146 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
147 | #define I915_BOX_LOST_CONTEXT 0x10 | |
148 | ||
149 | /* I915 specific ioctls | |
150 | * The device specific ioctl range is 0x40 to 0x79. | |
151 | */ | |
152 | #define DRM_I915_INIT 0x00 | |
153 | #define DRM_I915_FLUSH 0x01 | |
154 | #define DRM_I915_FLIP 0x02 | |
155 | #define DRM_I915_BATCHBUFFER 0x03 | |
156 | #define DRM_I915_IRQ_EMIT 0x04 | |
157 | #define DRM_I915_IRQ_WAIT 0x05 | |
158 | #define DRM_I915_GETPARAM 0x06 | |
159 | #define DRM_I915_SETPARAM 0x07 | |
160 | #define DRM_I915_ALLOC 0x08 | |
161 | #define DRM_I915_FREE 0x09 | |
162 | #define DRM_I915_INIT_HEAP 0x0a | |
163 | #define DRM_I915_CMDBUFFER 0x0b | |
de227f5f | 164 | #define DRM_I915_DESTROY_HEAP 0x0c |
702880f2 DA |
165 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
166 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | |
a6b54f3f | 167 | #define DRM_I915_VBLANK_SWAP 0x0f |
dc7a9319 | 168 | #define DRM_I915_HWS_ADDR 0x11 |
673a394b EA |
169 | #define DRM_I915_GEM_INIT 0x13 |
170 | #define DRM_I915_GEM_EXECBUFFER 0x14 | |
171 | #define DRM_I915_GEM_PIN 0x15 | |
172 | #define DRM_I915_GEM_UNPIN 0x16 | |
173 | #define DRM_I915_GEM_BUSY 0x17 | |
174 | #define DRM_I915_GEM_THROTTLE 0x18 | |
175 | #define DRM_I915_GEM_ENTERVT 0x19 | |
176 | #define DRM_I915_GEM_LEAVEVT 0x1a | |
177 | #define DRM_I915_GEM_CREATE 0x1b | |
178 | #define DRM_I915_GEM_PREAD 0x1c | |
179 | #define DRM_I915_GEM_PWRITE 0x1d | |
180 | #define DRM_I915_GEM_MMAP 0x1e | |
181 | #define DRM_I915_GEM_SET_DOMAIN 0x1f | |
182 | #define DRM_I915_GEM_SW_FINISH 0x20 | |
183 | #define DRM_I915_GEM_SET_TILING 0x21 | |
184 | #define DRM_I915_GEM_GET_TILING 0x22 | |
5a125c3c | 185 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
de151cf6 | 186 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
08d7b3d1 | 187 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
3ef94daa | 188 | #define DRM_I915_GEM_MADVISE 0x26 |
02e792fb DV |
189 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
190 | #define DRM_I915_OVERLAY_ATTRS 0x28 | |
76446cac | 191 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
1da177e4 LT |
192 | |
193 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
194 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
af6061af | 195 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
1da177e4 LT |
196 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) |
197 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
198 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
199 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
200 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
201 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
202 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
203 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
204 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
de227f5f | 205 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
702880f2 DA |
206 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
207 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
541f29aa | 208 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) |
8d391aa4 EA |
209 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) |
210 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) | |
76446cac | 211 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) |
673a394b EA |
212 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) |
213 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) | |
214 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) | |
215 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) | |
216 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) | |
217 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) | |
218 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) | |
219 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) | |
220 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) | |
221 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) | |
de151cf6 | 222 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) |
673a394b EA |
223 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) |
224 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) | |
225 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) | |
226 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) | |
5a125c3c | 227 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) |
04b2d218 | 228 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) |
3ef94daa | 229 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) |
02e792fb DV |
230 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) |
231 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) | |
1da177e4 LT |
232 | |
233 | /* Allow drivers to submit batchbuffers directly to hardware, relying | |
234 | * on the security mechanisms provided by hardware. | |
235 | */ | |
79e53945 | 236 | typedef struct drm_i915_batchbuffer { |
1da177e4 LT |
237 | int start; /* agp offset */ |
238 | int used; /* nr bytes in use */ | |
239 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
240 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
241 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
c60ce623 | 242 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
1da177e4 LT |
243 | } drm_i915_batchbuffer_t; |
244 | ||
245 | /* As above, but pass a pointer to userspace buffer which can be | |
246 | * validated by the kernel prior to sending to hardware. | |
247 | */ | |
248 | typedef struct _drm_i915_cmdbuffer { | |
249 | char __user *buf; /* pointer to userspace command buffer */ | |
250 | int sz; /* nr bytes in buf */ | |
251 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
252 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
253 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
c60ce623 | 254 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
1da177e4 LT |
255 | } drm_i915_cmdbuffer_t; |
256 | ||
257 | /* Userspace can request & wait on irq's: | |
258 | */ | |
259 | typedef struct drm_i915_irq_emit { | |
260 | int __user *irq_seq; | |
261 | } drm_i915_irq_emit_t; | |
262 | ||
263 | typedef struct drm_i915_irq_wait { | |
264 | int irq_seq; | |
265 | } drm_i915_irq_wait_t; | |
266 | ||
267 | /* Ioctl to query kernel params: | |
268 | */ | |
269 | #define I915_PARAM_IRQ_ACTIVE 1 | |
270 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
0d6aa60b | 271 | #define I915_PARAM_LAST_DISPATCH 3 |
ed4c9c4a | 272 | #define I915_PARAM_CHIPSET_ID 4 |
673a394b | 273 | #define I915_PARAM_HAS_GEM 5 |
0f973f27 | 274 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
02e792fb | 275 | #define I915_PARAM_HAS_OVERLAY 7 |
e9560f7c | 276 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
76446cac | 277 | #define I915_PARAM_HAS_EXECBUF2 9 |
e3a815fc | 278 | #define I915_PARAM_HAS_BSD 10 |
1da177e4 LT |
279 | |
280 | typedef struct drm_i915_getparam { | |
281 | int param; | |
282 | int __user *value; | |
283 | } drm_i915_getparam_t; | |
284 | ||
285 | /* Ioctl to set kernel params: | |
286 | */ | |
287 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
288 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
289 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
0f973f27 | 290 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
1da177e4 LT |
291 | |
292 | typedef struct drm_i915_setparam { | |
293 | int param; | |
294 | int value; | |
295 | } drm_i915_setparam_t; | |
296 | ||
297 | /* A memory manager for regions of shared memory: | |
298 | */ | |
299 | #define I915_MEM_REGION_AGP 1 | |
300 | ||
301 | typedef struct drm_i915_mem_alloc { | |
302 | int region; | |
303 | int alignment; | |
304 | int size; | |
305 | int __user *region_offset; /* offset from start of fb or agp */ | |
306 | } drm_i915_mem_alloc_t; | |
307 | ||
308 | typedef struct drm_i915_mem_free { | |
309 | int region; | |
310 | int region_offset; | |
311 | } drm_i915_mem_free_t; | |
312 | ||
313 | typedef struct drm_i915_mem_init_heap { | |
314 | int region; | |
315 | int size; | |
316 | int start; | |
317 | } drm_i915_mem_init_heap_t; | |
318 | ||
de227f5f DA |
319 | /* Allow memory manager to be torn down and re-initialized (eg on |
320 | * rotate): | |
321 | */ | |
322 | typedef struct drm_i915_mem_destroy_heap { | |
323 | int region; | |
324 | } drm_i915_mem_destroy_heap_t; | |
325 | ||
702880f2 DA |
326 | /* Allow X server to configure which pipes to monitor for vblank signals |
327 | */ | |
328 | #define DRM_I915_VBLANK_PIPE_A 1 | |
329 | #define DRM_I915_VBLANK_PIPE_B 2 | |
330 | ||
331 | typedef struct drm_i915_vblank_pipe { | |
332 | int pipe; | |
333 | } drm_i915_vblank_pipe_t; | |
334 | ||
a6b54f3f MD |
335 | /* Schedule buffer swap at given vertical blank: |
336 | */ | |
337 | typedef struct drm_i915_vblank_swap { | |
338 | drm_drawable_t drawable; | |
c60ce623 | 339 | enum drm_vblank_seq_type seqtype; |
a6b54f3f MD |
340 | unsigned int sequence; |
341 | } drm_i915_vblank_swap_t; | |
342 | ||
dc7a9319 | 343 | typedef struct drm_i915_hws_addr { |
1d7f83d5 | 344 | __u64 addr; |
dc7a9319 WZ |
345 | } drm_i915_hws_addr_t; |
346 | ||
673a394b EA |
347 | struct drm_i915_gem_init { |
348 | /** | |
349 | * Beginning offset in the GTT to be managed by the DRM memory | |
350 | * manager. | |
351 | */ | |
1d7f83d5 | 352 | __u64 gtt_start; |
673a394b EA |
353 | /** |
354 | * Ending offset in the GTT to be managed by the DRM memory | |
355 | * manager. | |
356 | */ | |
1d7f83d5 | 357 | __u64 gtt_end; |
673a394b EA |
358 | }; |
359 | ||
360 | struct drm_i915_gem_create { | |
361 | /** | |
362 | * Requested size for the object. | |
363 | * | |
364 | * The (page-aligned) allocated size for the object will be returned. | |
365 | */ | |
1d7f83d5 | 366 | __u64 size; |
673a394b EA |
367 | /** |
368 | * Returned handle for the object. | |
369 | * | |
370 | * Object handles are nonzero. | |
371 | */ | |
1d7f83d5 AB |
372 | __u32 handle; |
373 | __u32 pad; | |
673a394b EA |
374 | }; |
375 | ||
376 | struct drm_i915_gem_pread { | |
377 | /** Handle for the object being read. */ | |
1d7f83d5 AB |
378 | __u32 handle; |
379 | __u32 pad; | |
673a394b | 380 | /** Offset into the object to read from */ |
1d7f83d5 | 381 | __u64 offset; |
673a394b | 382 | /** Length of data to read */ |
1d7f83d5 | 383 | __u64 size; |
673a394b EA |
384 | /** |
385 | * Pointer to write the data into. | |
386 | * | |
387 | * This is a fixed-size type for 32/64 compatibility. | |
388 | */ | |
1d7f83d5 | 389 | __u64 data_ptr; |
673a394b EA |
390 | }; |
391 | ||
392 | struct drm_i915_gem_pwrite { | |
393 | /** Handle for the object being written to. */ | |
1d7f83d5 AB |
394 | __u32 handle; |
395 | __u32 pad; | |
673a394b | 396 | /** Offset into the object to write to */ |
1d7f83d5 | 397 | __u64 offset; |
673a394b | 398 | /** Length of data to write */ |
1d7f83d5 | 399 | __u64 size; |
673a394b EA |
400 | /** |
401 | * Pointer to read the data from. | |
402 | * | |
403 | * This is a fixed-size type for 32/64 compatibility. | |
404 | */ | |
1d7f83d5 | 405 | __u64 data_ptr; |
673a394b EA |
406 | }; |
407 | ||
408 | struct drm_i915_gem_mmap { | |
409 | /** Handle for the object being mapped. */ | |
1d7f83d5 AB |
410 | __u32 handle; |
411 | __u32 pad; | |
673a394b | 412 | /** Offset in the object to map. */ |
1d7f83d5 | 413 | __u64 offset; |
673a394b EA |
414 | /** |
415 | * Length of data to map. | |
416 | * | |
417 | * The value will be page-aligned. | |
418 | */ | |
1d7f83d5 | 419 | __u64 size; |
673a394b EA |
420 | /** |
421 | * Returned pointer the data was mapped at. | |
422 | * | |
423 | * This is a fixed-size type for 32/64 compatibility. | |
424 | */ | |
1d7f83d5 | 425 | __u64 addr_ptr; |
673a394b EA |
426 | }; |
427 | ||
de151cf6 JB |
428 | struct drm_i915_gem_mmap_gtt { |
429 | /** Handle for the object being mapped. */ | |
1d7f83d5 AB |
430 | __u32 handle; |
431 | __u32 pad; | |
de151cf6 JB |
432 | /** |
433 | * Fake offset to use for subsequent mmap call | |
434 | * | |
435 | * This is a fixed-size type for 32/64 compatibility. | |
436 | */ | |
1d7f83d5 | 437 | __u64 offset; |
de151cf6 JB |
438 | }; |
439 | ||
673a394b EA |
440 | struct drm_i915_gem_set_domain { |
441 | /** Handle for the object */ | |
1d7f83d5 | 442 | __u32 handle; |
673a394b EA |
443 | |
444 | /** New read domains */ | |
1d7f83d5 | 445 | __u32 read_domains; |
673a394b EA |
446 | |
447 | /** New write domain */ | |
1d7f83d5 | 448 | __u32 write_domain; |
673a394b EA |
449 | }; |
450 | ||
451 | struct drm_i915_gem_sw_finish { | |
452 | /** Handle for the object */ | |
1d7f83d5 | 453 | __u32 handle; |
673a394b EA |
454 | }; |
455 | ||
456 | struct drm_i915_gem_relocation_entry { | |
457 | /** | |
458 | * Handle of the buffer being pointed to by this relocation entry. | |
459 | * | |
460 | * It's appealing to make this be an index into the mm_validate_entry | |
461 | * list to refer to the buffer, but this allows the driver to create | |
462 | * a relocation list for state buffers and not re-write it per | |
463 | * exec using the buffer. | |
464 | */ | |
1d7f83d5 | 465 | __u32 target_handle; |
673a394b EA |
466 | |
467 | /** | |
468 | * Value to be added to the offset of the target buffer to make up | |
469 | * the relocation entry. | |
470 | */ | |
1d7f83d5 | 471 | __u32 delta; |
673a394b EA |
472 | |
473 | /** Offset in the buffer the relocation entry will be written into */ | |
1d7f83d5 | 474 | __u64 offset; |
673a394b EA |
475 | |
476 | /** | |
477 | * Offset value of the target buffer that the relocation entry was last | |
478 | * written as. | |
479 | * | |
480 | * If the buffer has the same offset as last time, we can skip syncing | |
481 | * and writing the relocation. This value is written back out by | |
482 | * the execbuffer ioctl when the relocation is written. | |
483 | */ | |
1d7f83d5 | 484 | __u64 presumed_offset; |
673a394b EA |
485 | |
486 | /** | |
487 | * Target memory domains read by this operation. | |
488 | */ | |
1d7f83d5 | 489 | __u32 read_domains; |
673a394b EA |
490 | |
491 | /** | |
492 | * Target memory domains written by this operation. | |
493 | * | |
494 | * Note that only one domain may be written by the whole | |
495 | * execbuffer operation, so that where there are conflicts, | |
496 | * the application will get -EINVAL back. | |
497 | */ | |
1d7f83d5 | 498 | __u32 write_domain; |
673a394b EA |
499 | }; |
500 | ||
501 | /** @{ | |
502 | * Intel memory domains | |
503 | * | |
504 | * Most of these just align with the various caches in | |
505 | * the system and are used to flush and invalidate as | |
506 | * objects end up cached in different domains. | |
507 | */ | |
508 | /** CPU cache */ | |
509 | #define I915_GEM_DOMAIN_CPU 0x00000001 | |
510 | /** Render cache, used by 2D and 3D drawing */ | |
511 | #define I915_GEM_DOMAIN_RENDER 0x00000002 | |
512 | /** Sampler cache, used by texture engine */ | |
513 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 | |
514 | /** Command queue, used to load batch buffers */ | |
515 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 | |
516 | /** Instruction cache, used by shader programs */ | |
517 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 | |
518 | /** Vertex address cache */ | |
519 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 | |
520 | /** GTT domain - aperture and scanout */ | |
521 | #define I915_GEM_DOMAIN_GTT 0x00000040 | |
522 | /** @} */ | |
523 | ||
524 | struct drm_i915_gem_exec_object { | |
525 | /** | |
526 | * User's handle for a buffer to be bound into the GTT for this | |
527 | * operation. | |
528 | */ | |
1d7f83d5 | 529 | __u32 handle; |
673a394b EA |
530 | |
531 | /** Number of relocations to be performed on this buffer */ | |
1d7f83d5 | 532 | __u32 relocation_count; |
673a394b EA |
533 | /** |
534 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
535 | * the relocations to be performed in this buffer. | |
536 | */ | |
1d7f83d5 | 537 | __u64 relocs_ptr; |
673a394b EA |
538 | |
539 | /** Required alignment in graphics aperture */ | |
1d7f83d5 | 540 | __u64 alignment; |
673a394b EA |
541 | |
542 | /** | |
543 | * Returned value of the updated offset of the object, for future | |
544 | * presumed_offset writes. | |
545 | */ | |
1d7f83d5 | 546 | __u64 offset; |
673a394b EA |
547 | }; |
548 | ||
549 | struct drm_i915_gem_execbuffer { | |
550 | /** | |
551 | * List of buffers to be validated with their relocations to be | |
552 | * performend on them. | |
553 | * | |
554 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. | |
555 | * | |
556 | * These buffers must be listed in an order such that all relocations | |
557 | * a buffer is performing refer to buffers that have already appeared | |
558 | * in the validate list. | |
559 | */ | |
1d7f83d5 AB |
560 | __u64 buffers_ptr; |
561 | __u32 buffer_count; | |
673a394b EA |
562 | |
563 | /** Offset in the batchbuffer to start execution from. */ | |
1d7f83d5 | 564 | __u32 batch_start_offset; |
673a394b | 565 | /** Bytes used in batchbuffer from batch_start_offset */ |
1d7f83d5 AB |
566 | __u32 batch_len; |
567 | __u32 DR1; | |
568 | __u32 DR4; | |
569 | __u32 num_cliprects; | |
673a394b | 570 | /** This is a struct drm_clip_rect *cliprects */ |
1d7f83d5 | 571 | __u64 cliprects_ptr; |
673a394b EA |
572 | }; |
573 | ||
76446cac JB |
574 | struct drm_i915_gem_exec_object2 { |
575 | /** | |
576 | * User's handle for a buffer to be bound into the GTT for this | |
577 | * operation. | |
578 | */ | |
579 | __u32 handle; | |
580 | ||
581 | /** Number of relocations to be performed on this buffer */ | |
582 | __u32 relocation_count; | |
583 | /** | |
584 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
585 | * the relocations to be performed in this buffer. | |
586 | */ | |
587 | __u64 relocs_ptr; | |
588 | ||
589 | /** Required alignment in graphics aperture */ | |
590 | __u64 alignment; | |
591 | ||
592 | /** | |
593 | * Returned value of the updated offset of the object, for future | |
594 | * presumed_offset writes. | |
595 | */ | |
596 | __u64 offset; | |
597 | ||
598 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) | |
599 | __u64 flags; | |
600 | __u64 rsvd1; | |
601 | __u64 rsvd2; | |
602 | }; | |
603 | ||
604 | struct drm_i915_gem_execbuffer2 { | |
605 | /** | |
606 | * List of gem_exec_object2 structs | |
607 | */ | |
608 | __u64 buffers_ptr; | |
609 | __u32 buffer_count; | |
610 | ||
611 | /** Offset in the batchbuffer to start execution from. */ | |
612 | __u32 batch_start_offset; | |
613 | /** Bytes used in batchbuffer from batch_start_offset */ | |
614 | __u32 batch_len; | |
615 | __u32 DR1; | |
616 | __u32 DR4; | |
617 | __u32 num_cliprects; | |
618 | /** This is a struct drm_clip_rect *cliprects */ | |
619 | __u64 cliprects_ptr; | |
8187a2b7 ZN |
620 | #define I915_EXEC_RENDER (1<<0) |
621 | #define I915_EXEC_BSD (1<<1) | |
622 | __u64 flags; | |
76446cac JB |
623 | __u64 rsvd1; |
624 | __u64 rsvd2; | |
625 | }; | |
626 | ||
673a394b EA |
627 | struct drm_i915_gem_pin { |
628 | /** Handle of the buffer to be pinned. */ | |
1d7f83d5 AB |
629 | __u32 handle; |
630 | __u32 pad; | |
673a394b EA |
631 | |
632 | /** alignment required within the aperture */ | |
1d7f83d5 | 633 | __u64 alignment; |
673a394b EA |
634 | |
635 | /** Returned GTT offset of the buffer. */ | |
1d7f83d5 | 636 | __u64 offset; |
673a394b EA |
637 | }; |
638 | ||
639 | struct drm_i915_gem_unpin { | |
640 | /** Handle of the buffer to be unpinned. */ | |
1d7f83d5 AB |
641 | __u32 handle; |
642 | __u32 pad; | |
673a394b EA |
643 | }; |
644 | ||
645 | struct drm_i915_gem_busy { | |
646 | /** Handle of the buffer to check for busy */ | |
1d7f83d5 | 647 | __u32 handle; |
673a394b EA |
648 | |
649 | /** Return busy status (1 if busy, 0 if idle) */ | |
1d7f83d5 | 650 | __u32 busy; |
673a394b EA |
651 | }; |
652 | ||
653 | #define I915_TILING_NONE 0 | |
654 | #define I915_TILING_X 1 | |
655 | #define I915_TILING_Y 2 | |
656 | ||
657 | #define I915_BIT_6_SWIZZLE_NONE 0 | |
658 | #define I915_BIT_6_SWIZZLE_9 1 | |
659 | #define I915_BIT_6_SWIZZLE_9_10 2 | |
660 | #define I915_BIT_6_SWIZZLE_9_11 3 | |
661 | #define I915_BIT_6_SWIZZLE_9_10_11 4 | |
662 | /* Not seen by userland */ | |
663 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 | |
280b713b EA |
664 | /* Seen by userland. */ |
665 | #define I915_BIT_6_SWIZZLE_9_17 6 | |
666 | #define I915_BIT_6_SWIZZLE_9_10_17 7 | |
673a394b EA |
667 | |
668 | struct drm_i915_gem_set_tiling { | |
669 | /** Handle of the buffer to have its tiling state updated */ | |
1d7f83d5 | 670 | __u32 handle; |
673a394b EA |
671 | |
672 | /** | |
673 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
674 | * I915_TILING_Y). | |
675 | * | |
676 | * This value is to be set on request, and will be updated by the | |
677 | * kernel on successful return with the actual chosen tiling layout. | |
678 | * | |
679 | * The tiling mode may be demoted to I915_TILING_NONE when the system | |
680 | * has bit 6 swizzling that can't be managed correctly by GEM. | |
681 | * | |
682 | * Buffer contents become undefined when changing tiling_mode. | |
683 | */ | |
1d7f83d5 | 684 | __u32 tiling_mode; |
673a394b EA |
685 | |
686 | /** | |
687 | * Stride in bytes for the object when in I915_TILING_X or | |
688 | * I915_TILING_Y. | |
689 | */ | |
1d7f83d5 | 690 | __u32 stride; |
673a394b EA |
691 | |
692 | /** | |
693 | * Returned address bit 6 swizzling required for CPU access through | |
694 | * mmap mapping. | |
695 | */ | |
1d7f83d5 | 696 | __u32 swizzle_mode; |
673a394b EA |
697 | }; |
698 | ||
699 | struct drm_i915_gem_get_tiling { | |
700 | /** Handle of the buffer to get tiling state for. */ | |
1d7f83d5 | 701 | __u32 handle; |
673a394b EA |
702 | |
703 | /** | |
704 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
705 | * I915_TILING_Y). | |
706 | */ | |
1d7f83d5 | 707 | __u32 tiling_mode; |
673a394b EA |
708 | |
709 | /** | |
710 | * Returned address bit 6 swizzling required for CPU access through | |
711 | * mmap mapping. | |
712 | */ | |
1d7f83d5 | 713 | __u32 swizzle_mode; |
673a394b EA |
714 | }; |
715 | ||
5a125c3c EA |
716 | struct drm_i915_gem_get_aperture { |
717 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ | |
1d7f83d5 | 718 | __u64 aper_size; |
5a125c3c EA |
719 | |
720 | /** | |
721 | * Available space in the aperture used by i915_gem_execbuffer, in | |
722 | * bytes | |
723 | */ | |
1d7f83d5 | 724 | __u64 aper_available_size; |
5a125c3c EA |
725 | }; |
726 | ||
08d7b3d1 CW |
727 | struct drm_i915_get_pipe_from_crtc_id { |
728 | /** ID of CRTC being requested **/ | |
729 | __u32 crtc_id; | |
730 | ||
731 | /** pipe of requested CRTC **/ | |
732 | __u32 pipe; | |
733 | }; | |
734 | ||
3ef94daa CW |
735 | #define I915_MADV_WILLNEED 0 |
736 | #define I915_MADV_DONTNEED 1 | |
bb6baf76 | 737 | #define __I915_MADV_PURGED 2 /* internal state */ |
3ef94daa CW |
738 | |
739 | struct drm_i915_gem_madvise { | |
740 | /** Handle of the buffer to change the backing store advice */ | |
741 | __u32 handle; | |
742 | ||
743 | /* Advice: either the buffer will be needed again in the near future, | |
744 | * or wont be and could be discarded under memory pressure. | |
745 | */ | |
746 | __u32 madv; | |
747 | ||
748 | /** Whether the backing store still exists. */ | |
749 | __u32 retained; | |
750 | }; | |
751 | ||
02e792fb DV |
752 | /* flags */ |
753 | #define I915_OVERLAY_TYPE_MASK 0xff | |
754 | #define I915_OVERLAY_YUV_PLANAR 0x01 | |
755 | #define I915_OVERLAY_YUV_PACKED 0x02 | |
756 | #define I915_OVERLAY_RGB 0x03 | |
757 | ||
758 | #define I915_OVERLAY_DEPTH_MASK 0xff00 | |
759 | #define I915_OVERLAY_RGB24 0x1000 | |
760 | #define I915_OVERLAY_RGB16 0x2000 | |
761 | #define I915_OVERLAY_RGB15 0x3000 | |
762 | #define I915_OVERLAY_YUV422 0x0100 | |
763 | #define I915_OVERLAY_YUV411 0x0200 | |
764 | #define I915_OVERLAY_YUV420 0x0300 | |
765 | #define I915_OVERLAY_YUV410 0x0400 | |
766 | ||
767 | #define I915_OVERLAY_SWAP_MASK 0xff0000 | |
768 | #define I915_OVERLAY_NO_SWAP 0x000000 | |
769 | #define I915_OVERLAY_UV_SWAP 0x010000 | |
770 | #define I915_OVERLAY_Y_SWAP 0x020000 | |
771 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 | |
772 | ||
773 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 | |
774 | #define I915_OVERLAY_ENABLE 0x01000000 | |
775 | ||
776 | struct drm_intel_overlay_put_image { | |
777 | /* various flags and src format description */ | |
778 | __u32 flags; | |
779 | /* source picture description */ | |
780 | __u32 bo_handle; | |
781 | /* stride values and offsets are in bytes, buffer relative */ | |
782 | __u16 stride_Y; /* stride for packed formats */ | |
783 | __u16 stride_UV; | |
784 | __u32 offset_Y; /* offset for packet formats */ | |
785 | __u32 offset_U; | |
786 | __u32 offset_V; | |
787 | /* in pixels */ | |
788 | __u16 src_width; | |
789 | __u16 src_height; | |
790 | /* to compensate the scaling factors for partially covered surfaces */ | |
791 | __u16 src_scan_width; | |
792 | __u16 src_scan_height; | |
793 | /* output crtc description */ | |
794 | __u32 crtc_id; | |
795 | __u16 dst_x; | |
796 | __u16 dst_y; | |
797 | __u16 dst_width; | |
798 | __u16 dst_height; | |
799 | }; | |
800 | ||
801 | /* flags */ | |
802 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) | |
803 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) | |
804 | struct drm_intel_overlay_attrs { | |
805 | __u32 flags; | |
806 | __u32 color_key; | |
807 | __s32 brightness; | |
808 | __u32 contrast; | |
809 | __u32 saturation; | |
810 | __u32 gamma0; | |
811 | __u32 gamma1; | |
812 | __u32 gamma2; | |
813 | __u32 gamma3; | |
814 | __u32 gamma4; | |
815 | __u32 gamma5; | |
816 | }; | |
817 | ||
1da177e4 | 818 | #endif /* _I915_DRM_H_ */ |