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Commit | Line | Data |
---|---|---|
738f66d3 MT |
1 | /* |
2 | * GXBB clock tree IDs | |
3 | */ | |
4 | ||
5 | #ifndef __GXBB_CLKC_H | |
6 | #define __GXBB_CLKC_H | |
7 | ||
8 | #define CLKID_CPUCLK 1 | |
19a2a85d | 9 | #define CLKID_HDMI_PLL 2 |
33608dcd | 10 | #define CLKID_FCLK_DIV2 4 |
19a2a85d NA |
11 | #define CLKID_FCLK_DIV3 5 |
12 | #define CLKID_FCLK_DIV4 6 | |
738f66d3 | 13 | #define CLKID_CLK81 12 |
ed6f4b51 | 14 | #define CLKID_MPLL2 15 |
f2120a8b | 15 | #define CLKID_SPI 34 |
dfdd7d4a | 16 | #define CLKID_I2C 22 |
33d0fcdf | 17 | #define CLKID_SAR_ADC 23 |
738f66d3 | 18 | #define CLKID_ETH 36 |
5dbe7890 MB |
19 | #define CLKID_USB0 50 |
20 | #define CLKID_USB1 51 | |
21 | #define CLKID_USB 55 | |
5a582cff | 22 | #define CLKID_HDMI_PCLK 63 |
5dbe7890 MB |
23 | #define CLKID_USB1_DDR_BRIDGE 64 |
24 | #define CLKID_USB0_DDR_BRIDGE 65 | |
33d0fcdf | 25 | #define CLKID_SANA 69 |
5a582cff | 26 | #define CLKID_GCLK_VENCI_INT0 77 |
dfdd7d4a | 27 | #define CLKID_AO_I2C 93 |
33608dcd KH |
28 | #define CLKID_SD_EMMC_A 94 |
29 | #define CLKID_SD_EMMC_B 95 | |
30 | #define CLKID_SD_EMMC_C 96 | |
33d0fcdf MB |
31 | #define CLKID_SAR_ADC_CLK 97 |
32 | #define CLKID_SAR_ADC_SEL 98 | |
738f66d3 MT |
33 | |
34 | #endif /* __GXBB_CLKC_H */ |