[mirror_ubuntu-artful-kernel.git] / include / dt-bindings / clock / imx21-clock.h

/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __DT_BINDINGS_CLOCK_IMX21_H
#define __DT_BINDINGS_CLOCK_IMX21_H

#define IMX21_CLK_DUMMY			0
#define IMX21_CLK_CKIL			1
#define IMX21_CLK_CKIH			2
#define IMX21_CLK_FPM			3
#define IMX21_CLK_CKIH_DIV1P5		4
#define IMX21_CLK_MPLL_GATE		5
#define IMX21_CLK_SPLL_GATE		6
#define IMX21_CLK_FPM_GATE		7
#define IMX21_CLK_CKIH_GATE		8
#define IMX21_CLK_MPLL_OSC_SEL		9
#define IMX21_CLK_IPG			10
#define IMX21_CLK_HCLK			11
#define IMX21_CLK_MPLL_SEL		12
#define IMX21_CLK_SPLL_SEL		13
#define IMX21_CLK_SSI1_SEL		14
#define IMX21_CLK_SSI2_SEL		15
#define IMX21_CLK_USB_DIV		16
#define IMX21_CLK_FCLK			17
#define IMX21_CLK_MPLL			18
#define IMX21_CLK_SPLL			19
#define IMX21_CLK_NFC_DIV		20
#define IMX21_CLK_SSI1_DIV		21
#define IMX21_CLK_SSI2_DIV		22
#define IMX21_CLK_PER1			23
#define IMX21_CLK_PER2			24
#define IMX21_CLK_PER3			25
#define IMX21_CLK_PER4			26
#define IMX21_CLK_UART1_IPG_GATE	27
#define IMX21_CLK_UART2_IPG_GATE	28
#define IMX21_CLK_UART3_IPG_GATE	29
#define IMX21_CLK_UART4_IPG_GATE	30
#define IMX21_CLK_CSPI1_IPG_GATE	31
#define IMX21_CLK_CSPI2_IPG_GATE	32
#define IMX21_CLK_SSI1_GATE		33
#define IMX21_CLK_SSI2_GATE		34
#define IMX21_CLK_SDHC1_IPG_GATE	35
#define IMX21_CLK_SDHC2_IPG_GATE	36
#define IMX21_CLK_GPIO_GATE		37
#define IMX21_CLK_I2C_GATE		38
#define IMX21_CLK_DMA_GATE		39
#define IMX21_CLK_USB_GATE		40
#define IMX21_CLK_EMMA_GATE		41
#define IMX21_CLK_SSI2_BAUD_GATE	42
#define IMX21_CLK_SSI1_BAUD_GATE	43
#define IMX21_CLK_LCDC_IPG_GATE		44
#define IMX21_CLK_NFC_GATE		45
#define IMX21_CLK_LCDC_HCLK_GATE	46
#define IMX21_CLK_PER4_GATE		47
#define IMX21_CLK_BMI_GATE		48
#define IMX21_CLK_USB_HCLK_GATE		49
#define IMX21_CLK_SLCDC_GATE		50
#define IMX21_CLK_SLCDC_HCLK_GATE	51
#define IMX21_CLK_EMMA_HCLK_GATE	52
#define IMX21_CLK_BROM_GATE		53
#define IMX21_CLK_DMA_HCLK_GATE		54
#define IMX21_CLK_CSI_HCLK_GATE		55
#define IMX21_CLK_CSPI3_IPG_GATE	56
#define IMX21_CLK_WDOG_GATE		57
#define IMX21_CLK_GPT1_IPG_GATE		58
#define IMX21_CLK_GPT2_IPG_GATE		59
#define IMX21_CLK_GPT3_IPG_GATE		60
#define IMX21_CLK_PWM_IPG_GATE		61
#define IMX21_CLK_RTC_GATE		62
#define IMX21_CLK_KPP_GATE		63
#define IMX21_CLK_OWIRE_GATE		64
#define IMX21_CLK_MAX			65

#endif
Commit	Line	Data
35bcaf00 AS	1	/*
	2	* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	*/
	9
	10	#ifndef __DT_BINDINGS_CLOCK_IMX21_H
	11	#define __DT_BINDINGS_CLOCK_IMX21_H
	12
	13	#define IMX21_CLK_DUMMY 0
	14	#define IMX21_CLK_CKIL 1
	15	#define IMX21_CLK_CKIH 2
	16	#define IMX21_CLK_FPM 3
	17	#define IMX21_CLK_CKIH_DIV1P5 4
	18	#define IMX21_CLK_MPLL_GATE 5
	19	#define IMX21_CLK_SPLL_GATE 6
	20	#define IMX21_CLK_FPM_GATE 7
	21	#define IMX21_CLK_CKIH_GATE 8
	22	#define IMX21_CLK_MPLL_OSC_SEL 9
	23	#define IMX21_CLK_IPG 10
	24	#define IMX21_CLK_HCLK 11
	25	#define IMX21_CLK_MPLL_SEL 12
	26	#define IMX21_CLK_SPLL_SEL 13
	27	#define IMX21_CLK_SSI1_SEL 14
	28	#define IMX21_CLK_SSI2_SEL 15
	29	#define IMX21_CLK_USB_DIV 16
	30	#define IMX21_CLK_FCLK 17
	31	#define IMX21_CLK_MPLL 18
	32	#define IMX21_CLK_SPLL 19
	33	#define IMX21_CLK_NFC_DIV 20
	34	#define IMX21_CLK_SSI1_DIV 21
	35	#define IMX21_CLK_SSI2_DIV 22
	36	#define IMX21_CLK_PER1 23
	37	#define IMX21_CLK_PER2 24
	38	#define IMX21_CLK_PER3 25
	39	#define IMX21_CLK_PER4 26
	40	#define IMX21_CLK_UART1_IPG_GATE 27
	41	#define IMX21_CLK_UART2_IPG_GATE 28
	42	#define IMX21_CLK_UART3_IPG_GATE 29
	43	#define IMX21_CLK_UART4_IPG_GATE 30
	44	#define IMX21_CLK_CSPI1_IPG_GATE 31
	45	#define IMX21_CLK_CSPI2_IPG_GATE 32
	46	#define IMX21_CLK_SSI1_GATE 33
	47	#define IMX21_CLK_SSI2_GATE 34
	48	#define IMX21_CLK_SDHC1_IPG_GATE 35
	49	#define IMX21_CLK_SDHC2_IPG_GATE 36
	50	#define IMX21_CLK_GPIO_GATE 37
	51	#define IMX21_CLK_I2C_GATE 38
	52	#define IMX21_CLK_DMA_GATE 39
	53	#define IMX21_CLK_USB_GATE 40
	54	#define IMX21_CLK_EMMA_GATE 41
	55	#define IMX21_CLK_SSI2_BAUD_GATE 42
	56	#define IMX21_CLK_SSI1_BAUD_GATE 43
	57	#define IMX21_CLK_LCDC_IPG_GATE 44
	58	#define IMX21_CLK_NFC_GATE 45
	59	#define IMX21_CLK_LCDC_HCLK_GATE 46
	60	#define IMX21_CLK_PER4_GATE 47
	61	#define IMX21_CLK_BMI_GATE 48
	62	#define IMX21_CLK_USB_HCLK_GATE 49
	63	#define IMX21_CLK_SLCDC_GATE 50
	64	#define IMX21_CLK_SLCDC_HCLK_GATE 51
65	#define IMX21_CLK_EMMA_HCLK_GATE 52
66	#define IMX21_CLK_BROM_GATE 53
67	#define IMX21_CLK_DMA_HCLK_GATE 54
68	#define IMX21_CLK_CSI_HCLK_GATE 55
69	#define IMX21_CLK_CSPI3_IPG_GATE 56
70	#define IMX21_CLK_WDOG_GATE 57
71	#define IMX21_CLK_GPT1_IPG_GATE 58
72	#define IMX21_CLK_GPT2_IPG_GATE 59
73	#define IMX21_CLK_GPT3_IPG_GATE 60
74	#define IMX21_CLK_PWM_IPG_GATE 61
75	#define IMX21_CLK_RTC_GATE 62
76	#define IMX21_CLK_KPP_GATE 63
77	#define IMX21_CLK_OWIRE_GATE 64
78	#define IMX21_CLK_MAX 65
79
80	#endif