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c1e81a3b JL |
1 | /* |
2 | * Copyright (c) 2014 MediaTek Inc. | |
3 | * Author: James Liao <jamesjj.liao@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #ifndef _DT_BINDINGS_CLK_MT8173_H | |
16 | #define _DT_BINDINGS_CLK_MT8173_H | |
17 | ||
18 | /* TOPCKGEN */ | |
19 | ||
20 | #define CLK_TOP_CLKPH_MCK_O 1 | |
c1e81a3b JL |
21 | #define CLK_TOP_USB_SYSPLL_125M 3 |
22 | #define CLK_TOP_HDMITX_DIG_CTS 4 | |
23 | #define CLK_TOP_ARMCA7PLL_754M 5 | |
24 | #define CLK_TOP_ARMCA7PLL_502M 6 | |
25 | #define CLK_TOP_MAIN_H546M 7 | |
26 | #define CLK_TOP_MAIN_H364M 8 | |
27 | #define CLK_TOP_MAIN_H218P4M 9 | |
28 | #define CLK_TOP_MAIN_H156M 10 | |
29 | #define CLK_TOP_TVDPLL_445P5M 11 | |
30 | #define CLK_TOP_TVDPLL_594M 12 | |
31 | #define CLK_TOP_UNIV_624M 13 | |
32 | #define CLK_TOP_UNIV_416M 14 | |
33 | #define CLK_TOP_UNIV_249P6M 15 | |
34 | #define CLK_TOP_UNIV_178P3M 16 | |
35 | #define CLK_TOP_UNIV_48M 17 | |
36 | #define CLK_TOP_CLKRTC_EXT 18 | |
37 | #define CLK_TOP_CLKRTC_INT 19 | |
38 | #define CLK_TOP_FPC 20 | |
39 | #define CLK_TOP_HDMITXPLL_D2 21 | |
40 | #define CLK_TOP_HDMITXPLL_D3 22 | |
41 | #define CLK_TOP_ARMCA7PLL_D2 23 | |
42 | #define CLK_TOP_ARMCA7PLL_D3 24 | |
43 | #define CLK_TOP_APLL1 25 | |
44 | #define CLK_TOP_APLL2 26 | |
45 | #define CLK_TOP_DMPLL 27 | |
46 | #define CLK_TOP_DMPLL_D2 28 | |
47 | #define CLK_TOP_DMPLL_D4 29 | |
48 | #define CLK_TOP_DMPLL_D8 30 | |
49 | #define CLK_TOP_DMPLL_D16 31 | |
50 | #define CLK_TOP_LVDSPLL_D2 32 | |
51 | #define CLK_TOP_LVDSPLL_D4 33 | |
52 | #define CLK_TOP_LVDSPLL_D8 34 | |
53 | #define CLK_TOP_MMPLL 35 | |
54 | #define CLK_TOP_MMPLL_D2 36 | |
55 | #define CLK_TOP_MSDCPLL 37 | |
56 | #define CLK_TOP_MSDCPLL_D2 38 | |
57 | #define CLK_TOP_MSDCPLL_D4 39 | |
58 | #define CLK_TOP_MSDCPLL2 40 | |
59 | #define CLK_TOP_MSDCPLL2_D2 41 | |
60 | #define CLK_TOP_MSDCPLL2_D4 42 | |
61 | #define CLK_TOP_SYSPLL_D2 43 | |
62 | #define CLK_TOP_SYSPLL1_D2 44 | |
63 | #define CLK_TOP_SYSPLL1_D4 45 | |
64 | #define CLK_TOP_SYSPLL1_D8 46 | |
65 | #define CLK_TOP_SYSPLL1_D16 47 | |
66 | #define CLK_TOP_SYSPLL_D3 48 | |
67 | #define CLK_TOP_SYSPLL2_D2 49 | |
68 | #define CLK_TOP_SYSPLL2_D4 50 | |
69 | #define CLK_TOP_SYSPLL_D5 51 | |
70 | #define CLK_TOP_SYSPLL3_D2 52 | |
71 | #define CLK_TOP_SYSPLL3_D4 53 | |
72 | #define CLK_TOP_SYSPLL_D7 54 | |
73 | #define CLK_TOP_SYSPLL4_D2 55 | |
74 | #define CLK_TOP_SYSPLL4_D4 56 | |
75 | #define CLK_TOP_TVDPLL 57 | |
76 | #define CLK_TOP_TVDPLL_D2 58 | |
77 | #define CLK_TOP_TVDPLL_D4 59 | |
78 | #define CLK_TOP_TVDPLL_D8 60 | |
79 | #define CLK_TOP_TVDPLL_D16 61 | |
80 | #define CLK_TOP_UNIVPLL_D2 62 | |
81 | #define CLK_TOP_UNIVPLL1_D2 63 | |
82 | #define CLK_TOP_UNIVPLL1_D4 64 | |
83 | #define CLK_TOP_UNIVPLL1_D8 65 | |
84 | #define CLK_TOP_UNIVPLL_D3 66 | |
85 | #define CLK_TOP_UNIVPLL2_D2 67 | |
86 | #define CLK_TOP_UNIVPLL2_D4 68 | |
87 | #define CLK_TOP_UNIVPLL2_D8 69 | |
88 | #define CLK_TOP_UNIVPLL_D5 70 | |
89 | #define CLK_TOP_UNIVPLL3_D2 71 | |
90 | #define CLK_TOP_UNIVPLL3_D4 72 | |
91 | #define CLK_TOP_UNIVPLL3_D8 73 | |
92 | #define CLK_TOP_UNIVPLL_D7 74 | |
93 | #define CLK_TOP_UNIVPLL_D26 75 | |
94 | #define CLK_TOP_UNIVPLL_D52 76 | |
95 | #define CLK_TOP_VCODECPLL 77 | |
96 | #define CLK_TOP_VCODECPLL_370P5 78 | |
97 | #define CLK_TOP_VENCPLL 79 | |
98 | #define CLK_TOP_VENCPLL_D2 80 | |
99 | #define CLK_TOP_VENCPLL_D4 81 | |
100 | #define CLK_TOP_AXI_SEL 82 | |
101 | #define CLK_TOP_MEM_SEL 83 | |
102 | #define CLK_TOP_DDRPHYCFG_SEL 84 | |
103 | #define CLK_TOP_MM_SEL 85 | |
104 | #define CLK_TOP_PWM_SEL 86 | |
105 | #define CLK_TOP_VDEC_SEL 87 | |
106 | #define CLK_TOP_VENC_SEL 88 | |
107 | #define CLK_TOP_MFG_SEL 89 | |
108 | #define CLK_TOP_CAMTG_SEL 90 | |
109 | #define CLK_TOP_UART_SEL 91 | |
110 | #define CLK_TOP_SPI_SEL 92 | |
111 | #define CLK_TOP_USB20_SEL 93 | |
112 | #define CLK_TOP_USB30_SEL 94 | |
113 | #define CLK_TOP_MSDC50_0_H_SEL 95 | |
114 | #define CLK_TOP_MSDC50_0_SEL 96 | |
115 | #define CLK_TOP_MSDC30_1_SEL 97 | |
116 | #define CLK_TOP_MSDC30_2_SEL 98 | |
117 | #define CLK_TOP_MSDC30_3_SEL 99 | |
118 | #define CLK_TOP_AUDIO_SEL 100 | |
119 | #define CLK_TOP_AUD_INTBUS_SEL 101 | |
120 | #define CLK_TOP_PMICSPI_SEL 102 | |
121 | #define CLK_TOP_SCP_SEL 103 | |
122 | #define CLK_TOP_ATB_SEL 104 | |
123 | #define CLK_TOP_VENC_LT_SEL 105 | |
124 | #define CLK_TOP_DPI0_SEL 106 | |
125 | #define CLK_TOP_IRDA_SEL 107 | |
126 | #define CLK_TOP_CCI400_SEL 108 | |
127 | #define CLK_TOP_AUD_1_SEL 109 | |
128 | #define CLK_TOP_AUD_2_SEL 110 | |
129 | #define CLK_TOP_MEM_MFG_IN_SEL 111 | |
130 | #define CLK_TOP_AXI_MFG_IN_SEL 112 | |
131 | #define CLK_TOP_SCAM_SEL 113 | |
132 | #define CLK_TOP_SPINFI_IFR_SEL 114 | |
133 | #define CLK_TOP_HDMI_SEL 115 | |
134 | #define CLK_TOP_DPILVDS_SEL 116 | |
135 | #define CLK_TOP_MSDC50_2_H_SEL 117 | |
136 | #define CLK_TOP_HDCP_SEL 118 | |
137 | #define CLK_TOP_HDCP_24M_SEL 119 | |
138 | #define CLK_TOP_RTC_SEL 120 | |
139 | #define CLK_TOP_APLL1_DIV0 121 | |
140 | #define CLK_TOP_APLL1_DIV1 122 | |
141 | #define CLK_TOP_APLL1_DIV2 123 | |
142 | #define CLK_TOP_APLL1_DIV3 124 | |
143 | #define CLK_TOP_APLL1_DIV4 125 | |
144 | #define CLK_TOP_APLL1_DIV5 126 | |
145 | #define CLK_TOP_APLL2_DIV0 127 | |
146 | #define CLK_TOP_APLL2_DIV1 128 | |
147 | #define CLK_TOP_APLL2_DIV2 129 | |
148 | #define CLK_TOP_APLL2_DIV3 130 | |
149 | #define CLK_TOP_APLL2_DIV4 131 | |
150 | #define CLK_TOP_APLL2_DIV5 132 | |
151 | #define CLK_TOP_I2S0_M_SEL 133 | |
152 | #define CLK_TOP_I2S1_M_SEL 134 | |
153 | #define CLK_TOP_I2S2_M_SEL 135 | |
154 | #define CLK_TOP_I2S3_M_SEL 136 | |
155 | #define CLK_TOP_I2S3_B_SEL 137 | |
29859d93 JL |
156 | #define CLK_TOP_DSI0_DIG 138 |
157 | #define CLK_TOP_DSI1_DIG 139 | |
158 | #define CLK_TOP_LVDS_PXL 140 | |
159 | #define CLK_TOP_LVDS_CTS 141 | |
160 | #define CLK_TOP_NR_CLK 142 | |
c1e81a3b JL |
161 | |
162 | /* APMIXED_SYS */ | |
163 | ||
29859d93 JL |
164 | #define CLK_APMIXED_ARMCA15PLL 1 |
165 | #define CLK_APMIXED_ARMCA7PLL 2 | |
c1e81a3b JL |
166 | #define CLK_APMIXED_MAINPLL 3 |
167 | #define CLK_APMIXED_UNIVPLL 4 | |
168 | #define CLK_APMIXED_MMPLL 5 | |
169 | #define CLK_APMIXED_MSDCPLL 6 | |
170 | #define CLK_APMIXED_VENCPLL 7 | |
171 | #define CLK_APMIXED_TVDPLL 8 | |
172 | #define CLK_APMIXED_MPLL 9 | |
173 | #define CLK_APMIXED_VCODECPLL 10 | |
174 | #define CLK_APMIXED_APLL1 11 | |
175 | #define CLK_APMIXED_APLL2 12 | |
176 | #define CLK_APMIXED_LVDSPLL 13 | |
177 | #define CLK_APMIXED_MSDCPLL2 14 | |
cdb2bab7 | 178 | #define CLK_APMIXED_REF2USB_TX 15 |
4585945b PZ |
179 | #define CLK_APMIXED_HDMI_REF 16 |
180 | #define CLK_APMIXED_NR_CLK 17 | |
c1e81a3b JL |
181 | |
182 | /* INFRA_SYS */ | |
183 | ||
184 | #define CLK_INFRA_DBGCLK 1 | |
185 | #define CLK_INFRA_SMI 2 | |
186 | #define CLK_INFRA_AUDIO 3 | |
187 | #define CLK_INFRA_GCE 4 | |
188 | #define CLK_INFRA_L2C_SRAM 5 | |
189 | #define CLK_INFRA_M4U 6 | |
190 | #define CLK_INFRA_CPUM 7 | |
191 | #define CLK_INFRA_KP 8 | |
192 | #define CLK_INFRA_CEC 9 | |
193 | #define CLK_INFRA_PMICSPI 10 | |
194 | #define CLK_INFRA_PMICWRAP 11 | |
2d61fe0f | 195 | #define CLK_INFRA_CLK_13M 12 |
567bf2ed SW |
196 | #define CLK_INFRA_CA53SEL 13 |
197 | #define CLK_INFRA_CA57SEL 14 | |
198 | #define CLK_INFRA_NR_CLK 15 | |
c1e81a3b JL |
199 | |
200 | /* PERI_SYS */ | |
201 | ||
202 | #define CLK_PERI_NFI 1 | |
203 | #define CLK_PERI_THERM 2 | |
204 | #define CLK_PERI_PWM1 3 | |
205 | #define CLK_PERI_PWM2 4 | |
206 | #define CLK_PERI_PWM3 5 | |
207 | #define CLK_PERI_PWM4 6 | |
208 | #define CLK_PERI_PWM5 7 | |
209 | #define CLK_PERI_PWM6 8 | |
210 | #define CLK_PERI_PWM7 9 | |
211 | #define CLK_PERI_PWM 10 | |
212 | #define CLK_PERI_USB0 11 | |
213 | #define CLK_PERI_USB1 12 | |
214 | #define CLK_PERI_AP_DMA 13 | |
215 | #define CLK_PERI_MSDC30_0 14 | |
216 | #define CLK_PERI_MSDC30_1 15 | |
217 | #define CLK_PERI_MSDC30_2 16 | |
218 | #define CLK_PERI_MSDC30_3 17 | |
219 | #define CLK_PERI_NLI_ARB 18 | |
220 | #define CLK_PERI_IRDA 19 | |
221 | #define CLK_PERI_UART0 20 | |
222 | #define CLK_PERI_UART1 21 | |
223 | #define CLK_PERI_UART2 22 | |
224 | #define CLK_PERI_UART3 23 | |
225 | #define CLK_PERI_I2C0 24 | |
226 | #define CLK_PERI_I2C1 25 | |
227 | #define CLK_PERI_I2C2 26 | |
228 | #define CLK_PERI_I2C3 27 | |
229 | #define CLK_PERI_I2C4 28 | |
230 | #define CLK_PERI_AUXADC 29 | |
231 | #define CLK_PERI_SPI0 30 | |
232 | #define CLK_PERI_I2C5 31 | |
233 | #define CLK_PERI_NFIECC 32 | |
234 | #define CLK_PERI_SPI 33 | |
235 | #define CLK_PERI_IRRX 34 | |
236 | #define CLK_PERI_I2C6 35 | |
237 | #define CLK_PERI_UART0_SEL 36 | |
238 | #define CLK_PERI_UART1_SEL 37 | |
239 | #define CLK_PERI_UART2_SEL 38 | |
240 | #define CLK_PERI_UART3_SEL 39 | |
241 | #define CLK_PERI_NR_CLK 40 | |
242 | ||
29859d93 JL |
243 | /* IMG_SYS */ |
244 | ||
245 | #define CLK_IMG_LARB2_SMI 1 | |
246 | #define CLK_IMG_CAM_SMI 2 | |
247 | #define CLK_IMG_CAM_CAM 3 | |
248 | #define CLK_IMG_SEN_TG 4 | |
249 | #define CLK_IMG_SEN_CAM 5 | |
250 | #define CLK_IMG_CAM_SV 6 | |
251 | #define CLK_IMG_FD 7 | |
252 | #define CLK_IMG_NR_CLK 8 | |
253 | ||
254 | /* MM_SYS */ | |
255 | ||
256 | #define CLK_MM_SMI_COMMON 1 | |
257 | #define CLK_MM_SMI_LARB0 2 | |
258 | #define CLK_MM_CAM_MDP 3 | |
259 | #define CLK_MM_MDP_RDMA0 4 | |
260 | #define CLK_MM_MDP_RDMA1 5 | |
261 | #define CLK_MM_MDP_RSZ0 6 | |
262 | #define CLK_MM_MDP_RSZ1 7 | |
263 | #define CLK_MM_MDP_RSZ2 8 | |
264 | #define CLK_MM_MDP_TDSHP0 9 | |
265 | #define CLK_MM_MDP_TDSHP1 10 | |
266 | #define CLK_MM_MDP_WDMA 11 | |
267 | #define CLK_MM_MDP_WROT0 12 | |
268 | #define CLK_MM_MDP_WROT1 13 | |
269 | #define CLK_MM_FAKE_ENG 14 | |
270 | #define CLK_MM_MUTEX_32K 15 | |
271 | #define CLK_MM_DISP_OVL0 16 | |
272 | #define CLK_MM_DISP_OVL1 17 | |
273 | #define CLK_MM_DISP_RDMA0 18 | |
274 | #define CLK_MM_DISP_RDMA1 19 | |
275 | #define CLK_MM_DISP_RDMA2 20 | |
276 | #define CLK_MM_DISP_WDMA0 21 | |
277 | #define CLK_MM_DISP_WDMA1 22 | |
278 | #define CLK_MM_DISP_COLOR0 23 | |
279 | #define CLK_MM_DISP_COLOR1 24 | |
280 | #define CLK_MM_DISP_AAL 25 | |
281 | #define CLK_MM_DISP_GAMMA 26 | |
282 | #define CLK_MM_DISP_UFOE 27 | |
283 | #define CLK_MM_DISP_SPLIT0 28 | |
284 | #define CLK_MM_DISP_SPLIT1 29 | |
285 | #define CLK_MM_DISP_MERGE 30 | |
286 | #define CLK_MM_DISP_OD 31 | |
287 | #define CLK_MM_DISP_PWM0MM 32 | |
288 | #define CLK_MM_DISP_PWM026M 33 | |
289 | #define CLK_MM_DISP_PWM1MM 34 | |
290 | #define CLK_MM_DISP_PWM126M 35 | |
291 | #define CLK_MM_DSI0_ENGINE 36 | |
292 | #define CLK_MM_DSI0_DIGITAL 37 | |
293 | #define CLK_MM_DSI1_ENGINE 38 | |
294 | #define CLK_MM_DSI1_DIGITAL 39 | |
295 | #define CLK_MM_DPI_PIXEL 40 | |
296 | #define CLK_MM_DPI_ENGINE 41 | |
297 | #define CLK_MM_DPI1_PIXEL 42 | |
298 | #define CLK_MM_DPI1_ENGINE 43 | |
299 | #define CLK_MM_HDMI_PIXEL 44 | |
300 | #define CLK_MM_HDMI_PLLCK 45 | |
301 | #define CLK_MM_HDMI_AUDIO 46 | |
302 | #define CLK_MM_HDMI_SPDIF 47 | |
303 | #define CLK_MM_LVDS_PIXEL 48 | |
304 | #define CLK_MM_LVDS_CTS 49 | |
305 | #define CLK_MM_SMI_LARB4 50 | |
306 | #define CLK_MM_HDMI_HDCP 51 | |
307 | #define CLK_MM_HDMI_HDCP24M 52 | |
308 | #define CLK_MM_NR_CLK 53 | |
309 | ||
310 | /* VDEC_SYS */ | |
311 | ||
312 | #define CLK_VDEC_CKEN 1 | |
313 | #define CLK_VDEC_LARB_CKEN 2 | |
314 | #define CLK_VDEC_NR_CLK 3 | |
315 | ||
316 | /* VENC_SYS */ | |
317 | ||
318 | #define CLK_VENC_CKE0 1 | |
319 | #define CLK_VENC_CKE1 2 | |
320 | #define CLK_VENC_CKE2 3 | |
321 | #define CLK_VENC_CKE3 4 | |
322 | #define CLK_VENC_NR_CLK 5 | |
323 | ||
324 | /* VENCLT_SYS */ | |
325 | ||
326 | #define CLK_VENCLT_CKE0 1 | |
327 | #define CLK_VENCLT_CKE1 2 | |
328 | #define CLK_VENCLT_NR_CLK 3 | |
329 | ||
c1e81a3b | 330 | #endif /* _DT_BINDINGS_CLK_MT8173_H */ |