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1 | /* |
2 | * Copyright 2014 Linaro Ltd. | |
3 | * Copyright (C) 2014 ZTE Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef __DT_BINDINGS_CLOCK_ZX296702_H | |
11 | #define __DT_BINDINGS_CLOCK_ZX296702_H | |
12 | ||
13 | #define ZX296702_OSC 0 | |
14 | #define ZX296702_PLL_A9 1 | |
15 | #define ZX296702_PLL_A9_350M 2 | |
16 | #define ZX296702_PLL_MAC_1000M 3 | |
17 | #define ZX296702_PLL_MAC_333M 4 | |
18 | #define ZX296702_PLL_MM0_1188M 5 | |
19 | #define ZX296702_PLL_MM0_396M 6 | |
20 | #define ZX296702_PLL_MM0_198M 7 | |
21 | #define ZX296702_PLL_MM1_108M 8 | |
22 | #define ZX296702_PLL_MM1_72M 9 | |
23 | #define ZX296702_PLL_MM1_54M 10 | |
24 | #define ZX296702_PLL_LSP_104M 11 | |
25 | #define ZX296702_PLL_LSP_26M 12 | |
26 | #define ZX296702_PLL_AUDIO_294M912 13 | |
27 | #define ZX296702_PLL_DDR_266M 14 | |
28 | #define ZX296702_CLK_148M5 15 | |
29 | #define ZX296702_MATRIX_ACLK 16 | |
30 | #define ZX296702_MAIN_HCLK 17 | |
31 | #define ZX296702_MAIN_PCLK 18 | |
32 | #define ZX296702_CLK_500 19 | |
33 | #define ZX296702_CLK_250 20 | |
34 | #define ZX296702_CLK_125 21 | |
35 | #define ZX296702_CLK_74M25 22 | |
36 | #define ZX296702_A9_WCLK 23 | |
37 | #define ZX296702_A9_AS1_ACLK_MUX 24 | |
38 | #define ZX296702_A9_TRACE_CLKIN_MUX 25 | |
39 | #define ZX296702_A9_AS1_ACLK_DIV 26 | |
40 | #define ZX296702_CLK_2 27 | |
41 | #define ZX296702_CLK_27 28 | |
42 | #define ZX296702_DECPPU_ACLK_MUX 29 | |
43 | #define ZX296702_PPU_ACLK_MUX 30 | |
44 | #define ZX296702_MALI400_ACLK_MUX 31 | |
45 | #define ZX296702_VOU_ACLK_MUX 32 | |
46 | #define ZX296702_VOU_MAIN_WCLK_MUX 33 | |
47 | #define ZX296702_VOU_AUX_WCLK_MUX 34 | |
48 | #define ZX296702_VOU_SCALER_WCLK_MUX 35 | |
49 | #define ZX296702_R2D_ACLK_MUX 36 | |
50 | #define ZX296702_R2D_WCLK_MUX 37 | |
51 | #define ZX296702_CLK_50 38 | |
52 | #define ZX296702_CLK_25 39 | |
53 | #define ZX296702_CLK_12 40 | |
54 | #define ZX296702_CLK_16M384 41 | |
55 | #define ZX296702_CLK_32K768 42 | |
56 | #define ZX296702_SEC_WCLK_DIV 43 | |
57 | #define ZX296702_DDR_WCLK_MUX 44 | |
58 | #define ZX296702_NAND_WCLK_MUX 45 | |
59 | #define ZX296702_LSP_26_WCLK_MUX 46 | |
60 | #define ZX296702_A9_AS0_ACLK 47 | |
61 | #define ZX296702_A9_AS1_ACLK 48 | |
62 | #define ZX296702_A9_TRACE_CLKIN 49 | |
63 | #define ZX296702_DECPPU_AXI_M_ACLK 50 | |
64 | #define ZX296702_DECPPU_AHB_S_HCLK 51 | |
65 | #define ZX296702_PPU_AXI_M_ACLK 52 | |
66 | #define ZX296702_PPU_AHB_S_HCLK 53 | |
67 | #define ZX296702_VOU_AXI_M_ACLK 54 | |
68 | #define ZX296702_VOU_APB_PCLK 55 | |
69 | #define ZX296702_VOU_MAIN_CHANNEL_WCLK 56 | |
70 | #define ZX296702_VOU_AUX_CHANNEL_WCLK 57 | |
71 | #define ZX296702_VOU_HDMI_OSCLK_CEC 58 | |
72 | #define ZX296702_VOU_SCALER_WCLK 59 | |
73 | #define ZX296702_MALI400_AXI_M_ACLK 60 | |
74 | #define ZX296702_MALI400_APB_PCLK 61 | |
75 | #define ZX296702_R2D_WCLK 62 | |
76 | #define ZX296702_R2D_AXI_M_ACLK 63 | |
77 | #define ZX296702_R2D_AHB_HCLK 64 | |
78 | #define ZX296702_DDR3_AXI_S0_ACLK 65 | |
79 | #define ZX296702_DDR3_APB_PCLK 66 | |
80 | #define ZX296702_DDR3_WCLK 67 | |
81 | #define ZX296702_USB20_0_AHB_HCLK 68 | |
82 | #define ZX296702_USB20_0_EXTREFCLK 69 | |
83 | #define ZX296702_USB20_1_AHB_HCLK 70 | |
84 | #define ZX296702_USB20_1_EXTREFCLK 71 | |
85 | #define ZX296702_USB20_2_AHB_HCLK 72 | |
86 | #define ZX296702_USB20_2_EXTREFCLK 73 | |
87 | #define ZX296702_GMAC_AXI_M_ACLK 74 | |
88 | #define ZX296702_GMAC_APB_PCLK 75 | |
89 | #define ZX296702_GMAC_125_CLKIN 76 | |
90 | #define ZX296702_GMAC_RMII_CLKIN 77 | |
91 | #define ZX296702_GMAC_25M_CLK 78 | |
92 | #define ZX296702_NANDFLASH_AHB_HCLK 79 | |
93 | #define ZX296702_NANDFLASH_WCLK 80 | |
94 | #define ZX296702_LSP0_APB_PCLK 81 | |
95 | #define ZX296702_LSP0_AHB_HCLK 82 | |
96 | #define ZX296702_LSP0_26M_WCLK 83 | |
97 | #define ZX296702_LSP0_104M_WCLK 84 | |
98 | #define ZX296702_LSP0_16M384_WCLK 85 | |
99 | #define ZX296702_LSP1_APB_PCLK 86 | |
100 | #define ZX296702_LSP1_26M_WCLK 87 | |
101 | #define ZX296702_LSP1_104M_WCLK 88 | |
102 | #define ZX296702_LSP1_32K_CLK 89 | |
103 | #define ZX296702_AON_HCLK 90 | |
104 | #define ZX296702_SYS_CTRL_PCLK 91 | |
105 | #define ZX296702_DMA_PCLK 92 | |
106 | #define ZX296702_DMA_ACLK 93 | |
107 | #define ZX296702_SEC_HCLK 94 | |
108 | #define ZX296702_AES_WCLK 95 | |
109 | #define ZX296702_DES_WCLK 96 | |
110 | #define ZX296702_IRAM_ACLK 97 | |
111 | #define ZX296702_IROM_ACLK 98 | |
112 | #define ZX296702_BOOT_CTRL_HCLK 99 | |
113 | #define ZX296702_EFUSE_CLK_30 100 | |
114 | #define ZX296702_VOU_MAIN_CHANNEL_DIV 101 | |
115 | #define ZX296702_VOU_AUX_CHANNEL_DIV 102 | |
116 | #define ZX296702_VOU_TV_ENC_HD_DIV 103 | |
117 | #define ZX296702_VOU_TV_ENC_SD_DIV 104 | |
118 | #define ZX296702_VL0_MUX 105 | |
119 | #define ZX296702_VL1_MUX 106 | |
120 | #define ZX296702_VL2_MUX 107 | |
121 | #define ZX296702_GL0_MUX 108 | |
122 | #define ZX296702_GL1_MUX 109 | |
123 | #define ZX296702_GL2_MUX 110 | |
124 | #define ZX296702_WB_MUX 111 | |
125 | #define ZX296702_HDMI_MUX 112 | |
126 | #define ZX296702_VOU_TV_ENC_HD_MUX 113 | |
127 | #define ZX296702_VOU_TV_ENC_SD_MUX 114 | |
128 | #define ZX296702_VL0_CLK 115 | |
129 | #define ZX296702_VL1_CLK 116 | |
130 | #define ZX296702_VL2_CLK 117 | |
131 | #define ZX296702_GL0_CLK 118 | |
132 | #define ZX296702_GL1_CLK 119 | |
133 | #define ZX296702_GL2_CLK 120 | |
134 | #define ZX296702_WB_CLK 121 | |
135 | #define ZX296702_CL_CLK 122 | |
136 | #define ZX296702_MAIN_MIX_CLK 123 | |
137 | #define ZX296702_AUX_MIX_CLK 124 | |
138 | #define ZX296702_HDMI_CLK 125 | |
139 | #define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126 | |
140 | #define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127 | |
141 | #define ZX296702_A9_PERIPHCLK 128 | |
142 | #define ZX296702_TOPCLK_END 129 | |
143 | ||
144 | #define ZX296702_SDMMC1_WCLK_MUX 0 | |
145 | #define ZX296702_SDMMC1_WCLK_DIV 1 | |
146 | #define ZX296702_SDMMC1_WCLK 2 | |
147 | #define ZX296702_SDMMC1_PCLK 3 | |
148 | #define ZX296702_SPDIF0_WCLK_MUX 4 | |
149 | #define ZX296702_SPDIF0_WCLK 5 | |
150 | #define ZX296702_SPDIF0_PCLK 6 | |
151 | #define ZX296702_SPDIF0_DIV 7 | |
152 | #define ZX296702_I2S0_WCLK_MUX 8 | |
153 | #define ZX296702_I2S0_WCLK 9 | |
154 | #define ZX296702_I2S0_PCLK 10 | |
155 | #define ZX296702_I2S0_DIV 11 | |
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156 | #define ZX296702_I2S1_WCLK_MUX 12 |
157 | #define ZX296702_I2S1_WCLK 13 | |
158 | #define ZX296702_I2S1_PCLK 14 | |
159 | #define ZX296702_I2S1_DIV 15 | |
160 | #define ZX296702_I2S2_WCLK_MUX 16 | |
161 | #define ZX296702_I2S2_WCLK 17 | |
162 | #define ZX296702_I2S2_PCLK 18 | |
163 | #define ZX296702_I2S2_DIV 19 | |
164 | #define ZX296702_GPIO_CLK 20 | |
165 | #define ZX296702_LSP0CLK_END 21 | |
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166 | |
167 | #define ZX296702_UART0_WCLK_MUX 0 | |
168 | #define ZX296702_UART0_WCLK 1 | |
169 | #define ZX296702_UART0_PCLK 2 | |
170 | #define ZX296702_UART1_WCLK_MUX 3 | |
171 | #define ZX296702_UART1_WCLK 4 | |
172 | #define ZX296702_UART1_PCLK 5 | |
173 | #define ZX296702_SDMMC0_WCLK_MUX 6 | |
174 | #define ZX296702_SDMMC0_WCLK_DIV 7 | |
175 | #define ZX296702_SDMMC0_WCLK 8 | |
176 | #define ZX296702_SDMMC0_PCLK 9 | |
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177 | #define ZX296702_SPDIF1_WCLK_MUX 10 |
178 | #define ZX296702_SPDIF1_WCLK 11 | |
179 | #define ZX296702_SPDIF1_PCLK 12 | |
180 | #define ZX296702_SPDIF1_DIV 13 | |
181 | #define ZX296702_LSP1CLK_END 14 | |
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182 | |
183 | #endif /* __DT_BINDINGS_CLOCK_ZX296702_H */ |