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5a9fdfec FB |
1 | /* |
2 | * defines common to all virtual CPUs | |
5fafdf24 | 3 | * |
5a9fdfec FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
5a9fdfec FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
5a9fdfec FB |
18 | */ |
19 | #ifndef CPU_ALL_H | |
20 | #define CPU_ALL_H | |
21 | ||
022c62cb | 22 | #include "exec/cpu-common.h" |
1ab4c8ce | 23 | #include "exec/memory.h" |
24be3369 | 24 | #include "exec/tswap.h" |
b2a8658e | 25 | #include "qemu/thread.h" |
2e5b09fd | 26 | #include "hw/core/cpu.h" |
43771539 | 27 | #include "qemu/rcu.h" |
0ac4bd56 | 28 | |
48805df9 | 29 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
9e0dc48c PC |
30 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
31 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ | |
32 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ | |
33 | #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ | |
fdbc2b57 | 34 | #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ |
9e0dc48c | 35 | |
5fafdf24 | 36 | /* some important defines: |
5fafdf24 | 37 | * |
e03b5686 | 38 | * HOST_BIG_ENDIAN : whether the host cpu is big endian and |
0ac4bd56 | 39 | * otherwise little endian. |
5fafdf24 | 40 | * |
ee3eb3a7 | 41 | * TARGET_BIG_ENDIAN : same for the target cpu |
0ac4bd56 FB |
42 | */ |
43 | ||
ee3eb3a7 | 44 | #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN |
f193c797 FB |
45 | #define BSWAP_NEEDED |
46 | #endif | |
47 | ||
f193c797 FB |
48 | #if TARGET_LONG_SIZE == 4 |
49 | #define tswapl(s) tswap32(s) | |
50 | #define tswapls(s) tswap32s((uint32_t *)(s)) | |
0a962c02 | 51 | #define bswaptls(s) bswap32s(s) |
f193c797 FB |
52 | #else |
53 | #define tswapl(s) tswap64(s) | |
54 | #define tswapls(s) tswap64s((uint64_t *)(s)) | |
0a962c02 | 55 | #define bswaptls(s) bswap64s(s) |
f193c797 FB |
56 | #endif |
57 | ||
db5fd8d7 PM |
58 | /* Target-endianness CPU memory access functions. These fit into the |
59 | * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. | |
83d73968 | 60 | */ |
ee3eb3a7 | 61 | #if TARGET_BIG_ENDIAN |
2df3b95d FB |
62 | #define lduw_p(p) lduw_be_p(p) |
63 | #define ldsw_p(p) ldsw_be_p(p) | |
64 | #define ldl_p(p) ldl_be_p(p) | |
65 | #define ldq_p(p) ldq_be_p(p) | |
2df3b95d FB |
66 | #define stw_p(p, v) stw_be_p(p, v) |
67 | #define stl_p(p, v) stl_be_p(p, v) | |
68 | #define stq_p(p, v) stq_be_p(p, v) | |
afa4f665 PM |
69 | #define ldn_p(p, sz) ldn_be_p(p, sz) |
70 | #define stn_p(p, sz, v) stn_be_p(p, sz, v) | |
2df3b95d FB |
71 | #else |
72 | #define lduw_p(p) lduw_le_p(p) | |
73 | #define ldsw_p(p) ldsw_le_p(p) | |
74 | #define ldl_p(p) ldl_le_p(p) | |
75 | #define ldq_p(p) ldq_le_p(p) | |
2df3b95d FB |
76 | #define stw_p(p, v) stw_le_p(p, v) |
77 | #define stl_p(p, v) stl_le_p(p, v) | |
78 | #define stq_p(p, v) stq_le_p(p, v) | |
afa4f665 PM |
79 | #define ldn_p(p, sz) ldn_le_p(p, sz) |
80 | #define stn_p(p, sz, v) stn_le_p(p, sz, v) | |
5a9fdfec FB |
81 | #endif |
82 | ||
61382a50 FB |
83 | /* MMU memory access macros */ |
84 | ||
53a5960a | 85 | #if defined(CONFIG_USER_ONLY) |
022c62cb | 86 | #include "exec/user/abitypes.h" |
7d478306 | 87 | #include "exec/user/guest-base.h" |
0e62fd79 | 88 | |
e307c192 | 89 | extern bool have_guest_base; |
95059f9c RH |
90 | |
91 | /* | |
92 | * If non-zero, the guest virtual address space is a contiguous subset | |
93 | * of the host virtual address space, i.e. '-R reserved_va' is in effect | |
94 | * either from the command-line or by default. The value is the last | |
95 | * byte of the guest address space e.g. UINT32_MAX. | |
96 | * | |
97 | * If zero, the host and guest virtual address spaces are intermingled. | |
98 | */ | |
68a1c816 | 99 | extern unsigned long reserved_va; |
53a5960a | 100 | |
7d8cbbab RH |
101 | /* |
102 | * Limit the guest addresses as best we can. | |
103 | * | |
104 | * When not using -R reserved_va, we cannot really limit the guest | |
105 | * to less address space than the host. For 32-bit guests, this | |
106 | * acts as a sanity check that we're not giving the guest an address | |
107 | * that it cannot even represent. For 64-bit guests... the address | |
108 | * might not be what the real kernel would give, but it is at least | |
109 | * representable in the guest. | |
110 | * | |
111 | * TODO: Improve address allocation to avoid this problem, and to | |
112 | * avoid setting bits at the top of guest addresses that might need | |
113 | * to be used for tags. | |
114 | */ | |
f9919116 EB |
115 | #define GUEST_ADDR_MAX_ \ |
116 | ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ | |
117 | UINT32_MAX : ~0ul) | |
95059f9c | 118 | #define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) |
7d8cbbab | 119 | |
a7d6039c PB |
120 | #else |
121 | ||
122 | #include "exec/hwaddr.h" | |
4269c82b PB |
123 | |
124 | #define SUFFIX | |
125 | #define ARG1 as | |
126 | #define ARG1_DECL AddressSpace *as | |
127 | #define TARGET_ENDIANNESS | |
0979ed01 | 128 | #include "exec/memory_ldst.h.inc" |
4269c82b | 129 | |
48564041 | 130 | #define SUFFIX _cached_slow |
4269c82b PB |
131 | #define ARG1 cache |
132 | #define ARG1_DECL MemoryRegionCache *cache | |
133 | #define TARGET_ENDIANNESS | |
0979ed01 | 134 | #include "exec/memory_ldst.h.inc" |
4269c82b PB |
135 | |
136 | static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) | |
137 | { | |
138 | address_space_stl_notdirty(as, addr, val, | |
139 | MEMTXATTRS_UNSPECIFIED, NULL); | |
140 | } | |
141 | ||
142 | #define SUFFIX | |
143 | #define ARG1 as | |
144 | #define ARG1_DECL AddressSpace *as | |
145 | #define TARGET_ENDIANNESS | |
0979ed01 | 146 | #include "exec/memory_ldst_phys.h.inc" |
4269c82b | 147 | |
48564041 PB |
148 | /* Inline fast path for direct RAM access. */ |
149 | #define ENDIANNESS | |
0979ed01 | 150 | #include "exec/memory_ldst_cached.h.inc" |
48564041 | 151 | |
4269c82b PB |
152 | #define SUFFIX _cached |
153 | #define ARG1 cache | |
154 | #define ARG1_DECL MemoryRegionCache *cache | |
155 | #define TARGET_ENDIANNESS | |
0979ed01 | 156 | #include "exec/memory_ldst_phys.h.inc" |
53a5960a PB |
157 | #endif |
158 | ||
5a9fdfec FB |
159 | /* page related stuff */ |
160 | ||
20bccb82 | 161 | #ifdef TARGET_PAGE_BITS_VARY |
27eb9d65 | 162 | # include "exec/page-vary.h" |
bbc17caf | 163 | extern const TargetPageBits target_page; |
639044b5 | 164 | #ifdef CONFIG_DEBUG_TCG |
bbc17caf | 165 | #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) |
27eb9d65 RH |
166 | #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ |
167 | (target_long)target_page.mask; }) | |
20bccb82 | 168 | #else |
639044b5 | 169 | #define TARGET_PAGE_BITS target_page.bits |
27eb9d65 | 170 | #define TARGET_PAGE_MASK ((target_long)target_page.mask) |
639044b5 | 171 | #endif |
bb8e3ea6 | 172 | #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) |
639044b5 | 173 | #else |
20bccb82 | 174 | #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS |
bb8e3ea6 RH |
175 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
176 | #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) | |
20bccb82 PM |
177 | #endif |
178 | ||
50276a79 | 179 | #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) |
5a9fdfec | 180 | |
5a9fdfec FB |
181 | /* same as PROT_xxx */ |
182 | #define PAGE_READ 0x0001 | |
183 | #define PAGE_WRITE 0x0002 | |
184 | #define PAGE_EXEC 0x0004 | |
185 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) | |
186 | #define PAGE_VALID 0x0008 | |
d9c58585 RH |
187 | /* |
188 | * Original state of the write flag (used when tracking self-modifying code) | |
189 | */ | |
5fafdf24 | 190 | #define PAGE_WRITE_ORG 0x0010 |
d9c58585 RH |
191 | /* |
192 | * Invalidate the TLB entry immediately, helpful for s390x | |
193 | * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() | |
194 | */ | |
195 | #define PAGE_WRITE_INV 0x0020 | |
196 | /* For use with page_set_flags: page is being replaced; target_data cleared. */ | |
197 | #define PAGE_RESET 0x0040 | |
26bab757 RH |
198 | /* For linux-user, indicates that the page is MAP_ANON. */ |
199 | #define PAGE_ANON 0x0080 | |
d9c58585 | 200 | |
2e9a5713 PB |
201 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
202 | /* FIXME: Code that sets/uses this is broken and needs to go away. */ | |
d9c58585 | 203 | #define PAGE_RESERVED 0x0100 |
2e9a5713 | 204 | #endif |
be5d6f48 | 205 | /* Target-specific bits that will be used via page_get_flags(). */ |
52c01ada RH |
206 | #define PAGE_TARGET_1 0x0200 |
207 | #define PAGE_TARGET_2 0x0400 | |
5a9fdfec | 208 | |
f93b7695 IL |
209 | /* |
210 | * For linux-user, indicates that the page is mapped with the same semantics | |
211 | * in both guest and host. | |
212 | */ | |
213 | #define PAGE_PASSTHROUGH 0x0800 | |
214 | ||
b480d9b7 | 215 | #if defined(CONFIG_USER_ONLY) |
5a9fdfec | 216 | void page_dump(FILE *f); |
5cd2c5b6 | 217 | |
1a1c4db9 MI |
218 | typedef int (*walk_memory_regions_fn)(void *, target_ulong, |
219 | target_ulong, unsigned long); | |
5cd2c5b6 RH |
220 | int walk_memory_regions(void *, walk_memory_regions_fn); |
221 | ||
53a5960a | 222 | int page_get_flags(target_ulong address); |
49840a4a | 223 | void page_set_flags(target_ulong start, target_ulong last, int flags); |
10310cbd | 224 | void page_reset_target_data(target_ulong start, target_ulong last); |
3d97b40b | 225 | int page_check_range(target_ulong start, target_ulong len, int flags); |
d9c58585 RH |
226 | |
227 | /** | |
8269c014 | 228 | * page_get_target_data(address) |
d9c58585 | 229 | * @address: guest virtual address |
d9c58585 | 230 | * |
8269c014 RH |
231 | * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate |
232 | * with the guest page at @address, allocating it if necessary. The | |
233 | * caller should already have verified that the address is valid. | |
d9c58585 RH |
234 | * |
235 | * The memory will be freed when the guest page is deallocated, | |
236 | * e.g. with the munmap system call. | |
237 | */ | |
8269c014 RH |
238 | void *page_get_target_data(target_ulong address) |
239 | __attribute__((returns_nonnull)); | |
b480d9b7 | 240 | #endif |
5a9fdfec | 241 | |
9349b4f9 | 242 | CPUArchState *cpu_copy(CPUArchState *env); |
c5be9f08 | 243 | |
9c76219e RH |
244 | /* Flags for use in ENV->INTERRUPT_PENDING. |
245 | ||
246 | The numbers assigned here are non-sequential in order to preserve | |
247 | binary compatibility with the vmstate dump. Bit 0 (0x0001) was | |
248 | previously used for CPU_INTERRUPT_EXIT, and is cleared when loading | |
249 | the vmstate dump. */ | |
250 | ||
251 | /* External hardware interrupt pending. This is typically used for | |
252 | interrupts from devices. */ | |
253 | #define CPU_INTERRUPT_HARD 0x0002 | |
254 | ||
255 | /* Exit the current TB. This is typically used when some system-level device | |
256 | makes some change to the memory mapping. E.g. the a20 line change. */ | |
257 | #define CPU_INTERRUPT_EXITTB 0x0004 | |
258 | ||
259 | /* Halt the CPU. */ | |
260 | #define CPU_INTERRUPT_HALT 0x0020 | |
261 | ||
262 | /* Debug event pending. */ | |
263 | #define CPU_INTERRUPT_DEBUG 0x0080 | |
264 | ||
4a92a558 PB |
265 | /* Reset signal. */ |
266 | #define CPU_INTERRUPT_RESET 0x0400 | |
267 | ||
9c76219e RH |
268 | /* Several target-specific external hardware interrupts. Each target/cpu.h |
269 | should define proper names based on these defines. */ | |
270 | #define CPU_INTERRUPT_TGT_EXT_0 0x0008 | |
271 | #define CPU_INTERRUPT_TGT_EXT_1 0x0010 | |
272 | #define CPU_INTERRUPT_TGT_EXT_2 0x0040 | |
273 | #define CPU_INTERRUPT_TGT_EXT_3 0x0200 | |
274 | #define CPU_INTERRUPT_TGT_EXT_4 0x1000 | |
275 | ||
276 | /* Several target-specific internal interrupts. These differ from the | |
07f35073 | 277 | preceding target-specific interrupts in that they are intended to |
9c76219e RH |
278 | originate from within the cpu itself, typically in response to some |
279 | instruction being executed. These, therefore, are not masked while | |
280 | single-stepping within the debugger. */ | |
281 | #define CPU_INTERRUPT_TGT_INT_0 0x0100 | |
4a92a558 PB |
282 | #define CPU_INTERRUPT_TGT_INT_1 0x0800 |
283 | #define CPU_INTERRUPT_TGT_INT_2 0x2000 | |
9c76219e | 284 | |
d362e757 | 285 | /* First unused bit: 0x4000. */ |
9c76219e | 286 | |
3125f763 RH |
287 | /* The set of all bits that should be masked when single-stepping. */ |
288 | #define CPU_INTERRUPT_SSTEP_MASK \ | |
289 | (CPU_INTERRUPT_HARD \ | |
290 | | CPU_INTERRUPT_TGT_EXT_0 \ | |
291 | | CPU_INTERRUPT_TGT_EXT_1 \ | |
292 | | CPU_INTERRUPT_TGT_EXT_2 \ | |
293 | | CPU_INTERRUPT_TGT_EXT_3 \ | |
294 | | CPU_INTERRUPT_TGT_EXT_4) | |
98699967 | 295 | |
069cfe77 RH |
296 | #ifdef CONFIG_USER_ONLY |
297 | ||
298 | /* | |
299 | * Allow some level of source compatibility with softmmu. We do not | |
300 | * support any of the more exotic features, so only invalid pages may | |
301 | * be signaled by probe_access_flags(). | |
302 | */ | |
303 | #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) | |
304 | #define TLB_MMIO 0 | |
305 | #define TLB_WATCHPOINT 0 | |
306 | ||
307 | #else | |
b3755a91 | 308 | |
1f6f2b34 RH |
309 | /* |
310 | * Flags stored in the low bits of the TLB virtual address. | |
311 | * These are defined so that fast path ram access is all zeros. | |
1f00b27f SS |
312 | * The flags all must be between TARGET_PAGE_BITS and |
313 | * maximum address alignment bit. | |
1f6f2b34 RH |
314 | * |
315 | * Use TARGET_PAGE_BITS_MIN so that these bits are constant | |
316 | * when TARGET_PAGE_BITS_VARY is in effect. | |
1f00b27f | 317 | */ |
0f459d16 | 318 | /* Zero if TLB entry is valid. */ |
1f6f2b34 | 319 | #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) |
0f459d16 PB |
320 | /* Set if TLB entry references a clean RAM page. The iotlb entry will |
321 | contain the page physical address. */ | |
1f6f2b34 | 322 | #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) |
0f459d16 | 323 | /* Set if TLB entry is an IO callback. */ |
1f6f2b34 | 324 | #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) |
50b107c5 | 325 | /* Set if TLB entry contains a watchpoint. */ |
1f6f2b34 | 326 | #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) |
5b87b3e6 RH |
327 | /* Set if TLB entry requires byte swap. */ |
328 | #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) | |
7b0d792c RH |
329 | /* Set if TLB entry writes ignored. */ |
330 | #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) | |
1f00b27f SS |
331 | |
332 | /* Use this mask to check interception with an alignment mask | |
333 | * in a TCG backend. | |
334 | */ | |
50b107c5 | 335 | #define TLB_FLAGS_MASK \ |
7b0d792c RH |
336 | (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ |
337 | | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) | |
0f459d16 | 338 | |
334692bc PM |
339 | /** |
340 | * tlb_hit_page: return true if page aligned @addr is a hit against the | |
341 | * TLB entry @tlb_addr | |
342 | * | |
343 | * @addr: virtual address to test (must be page aligned) | |
344 | * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) | |
345 | */ | |
346 | static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) | |
347 | { | |
348 | return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); | |
349 | } | |
350 | ||
351 | /** | |
352 | * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr | |
353 | * | |
354 | * @addr: virtual address to test (need not be page aligned) | |
355 | * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) | |
356 | */ | |
357 | static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) | |
358 | { | |
359 | return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); | |
360 | } | |
361 | ||
740b1759 | 362 | #ifdef CONFIG_TCG |
7df5e3d6 | 363 | /* accel/tcg/translate-all.c */ |
3a841ab5 | 364 | void dump_exec_info(GString *buf); |
740b1759 CF |
365 | #endif /* CONFIG_TCG */ |
366 | ||
b3755a91 PB |
367 | #endif /* !CONFIG_USER_ONLY */ |
368 | ||
7df5e3d6 CF |
369 | /* accel/tcg/cpu-exec.c */ |
370 | int cpu_exec(CPUState *cpu); | |
371 | void tcg_exec_realizefn(CPUState *cpu, Error **errp); | |
372 | void tcg_exec_unrealizefn(CPUState *cpu); | |
7df5e3d6 | 373 | |
7506ed90 RH |
374 | /** |
375 | * cpu_set_cpustate_pointers(cpu) | |
376 | * @cpu: The cpu object | |
377 | * | |
378 | * Set the generic pointers in CPUState into the outer object. | |
379 | */ | |
380 | static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) | |
381 | { | |
382 | cpu->parent_obj.env_ptr = &cpu->env; | |
5e140196 | 383 | cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; |
7506ed90 RH |
384 | } |
385 | ||
083dc73d RH |
386 | /** |
387 | * env_archcpu(env) | |
388 | * @env: The architecture environment | |
389 | * | |
390 | * Return the ArchCPU associated with the environment. | |
391 | */ | |
392 | static inline ArchCPU *env_archcpu(CPUArchState *env) | |
393 | { | |
394 | return container_of(env, ArchCPU, env); | |
395 | } | |
396 | ||
29a0af61 RH |
397 | /** |
398 | * env_cpu(env) | |
399 | * @env: The architecture environment | |
400 | * | |
401 | * Return the CPUState associated with the environment. | |
402 | */ | |
403 | static inline CPUState *env_cpu(CPUArchState *env) | |
404 | { | |
083dc73d | 405 | return &env_archcpu(env)->parent_obj; |
29a0af61 RH |
406 | } |
407 | ||
5b146dc7 RH |
408 | /** |
409 | * env_neg(env) | |
410 | * @env: The architecture environment | |
411 | * | |
412 | * Return the CPUNegativeOffsetState associated with the environment. | |
413 | */ | |
414 | static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) | |
415 | { | |
416 | ArchCPU *arch_cpu = container_of(env, ArchCPU, env); | |
417 | return &arch_cpu->neg; | |
418 | } | |
419 | ||
420 | /** | |
421 | * cpu_neg(cpu) | |
422 | * @cpu: The generic CPUState | |
423 | * | |
424 | * Return the CPUNegativeOffsetState associated with the cpu. | |
425 | */ | |
426 | static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) | |
427 | { | |
428 | ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); | |
429 | return &arch_cpu->neg; | |
430 | } | |
431 | ||
269bd5d8 RH |
432 | /** |
433 | * env_tlb(env) | |
434 | * @env: The architecture environment | |
435 | * | |
436 | * Return the CPUTLB state associated with the environment. | |
437 | */ | |
438 | static inline CPUTLB *env_tlb(CPUArchState *env) | |
439 | { | |
440 | return &env_neg(env)->tlb; | |
441 | } | |
442 | ||
5a9fdfec | 443 | #endif /* CPU_ALL_H */ |