[mirror_qemu.git] / include / exec / cpu-all.h

/*
 * defines common to all virtual CPUs
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_ALL_H
#define CPU_ALL_H

#include "qemu-common.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"

/* some important defines:
 *
 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
 * memory accesses.
 *
 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
 * otherwise little endian.
 *
 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
 *
 * TARGET_WORDS_BIGENDIAN : same for target cpu
 */

#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
#define BSWAP_NEEDED
#endif

#ifdef BSWAP_NEEDED

static inline uint16_t tswap16(uint16_t s)
{
    return bswap16(s);
}

static inline uint32_t tswap32(uint32_t s)
{
    return bswap32(s);
}

static inline uint64_t tswap64(uint64_t s)
{
    return bswap64(s);
}

static inline void tswap16s(uint16_t *s)
{
    *s = bswap16(*s);
}

static inline void tswap32s(uint32_t *s)
{
    *s = bswap32(*s);
}

static inline void tswap64s(uint64_t *s)
{
    *s = bswap64(*s);
}

#else

static inline uint16_t tswap16(uint16_t s)
{
    return s;
}

static inline uint32_t tswap32(uint32_t s)
{
    return s;
}

static inline uint64_t tswap64(uint64_t s)
{
    return s;
}

static inline void tswap16s(uint16_t *s)
{
}

static inline void tswap32s(uint32_t *s)
{
}

static inline void tswap64s(uint64_t *s)
{
}

#endif

#if TARGET_LONG_SIZE == 4
#define tswapl(s) tswap32(s)
#define tswapls(s) tswap32s((uint32_t *)(s))
#define bswaptls(s) bswap32s(s)
#else
#define tswapl(s) tswap64(s)
#define tswapls(s) tswap64s((uint64_t *)(s))
#define bswaptls(s) bswap64s(s)
#endif

/* CPU memory access without any memory or io remapping */

/*
 * the generic syntax for the memory accesses is:
 *
 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 *
 * store: st{type}{size}{endian}_{access_type}(ptr, val)
 *
 * type is:
 * (empty): integer access
 *   f    : float access
 *
 * sign is:
 * (empty): for floats or 32 bit size
 *   u    : unsigned
 *   s    : signed
 *
 * size is:
 *   b: 8 bits
 *   w: 16 bits
 *   l: 32 bits
 *   q: 64 bits
 *
 * endian is:
 * (empty): target cpu endianness or 8 bit access
 *   r    : reversed target cpu endianness (not implemented yet)
 *   be   : big endian (not implemented yet)
 *   le   : little endian (not implemented yet)
 *
 * access_type is:
 *   raw    : host memory access
 *   user   : user mode access using soft MMU
 *   kernel : kernel mode access using soft MMU
 */

/* target-endianness CPU memory access functions */
#if defined(TARGET_WORDS_BIGENDIAN)
#define lduw_p(p) lduw_be_p(p)
#define ldsw_p(p) ldsw_be_p(p)
#define ldl_p(p) ldl_be_p(p)
#define ldq_p(p) ldq_be_p(p)
#define ldfl_p(p) ldfl_be_p(p)
#define ldfq_p(p) ldfq_be_p(p)
#define stw_p(p, v) stw_be_p(p, v)
#define stl_p(p, v) stl_be_p(p, v)
#define stq_p(p, v) stq_be_p(p, v)
#define stfl_p(p, v) stfl_be_p(p, v)
#define stfq_p(p, v) stfq_be_p(p, v)
#else
#define lduw_p(p) lduw_le_p(p)
#define ldsw_p(p) ldsw_le_p(p)
#define ldl_p(p) ldl_le_p(p)
#define ldq_p(p) ldq_le_p(p)
#define ldfl_p(p) ldfl_le_p(p)
#define ldfq_p(p) ldfq_le_p(p)
#define stw_p(p, v) stw_le_p(p, v)
#define stl_p(p, v) stl_le_p(p, v)
#define stq_p(p, v) stq_le_p(p, v)
#define stfl_p(p, v) stfl_le_p(p, v)
#define stfq_p(p, v) stfq_le_p(p, v)
#endif

/* MMU memory access macros */

#if defined(CONFIG_USER_ONLY)
#include <assert.h>
#include "exec/user/abitypes.h"

/* On some host systems the guest address space is reserved on the host.
 * This allows the guest address space to be offset to a convenient location.
 */
#if defined(CONFIG_USE_GUEST_BASE)
extern unsigned long guest_base;
extern int have_guest_base;
extern unsigned long reserved_va;
#define GUEST_BASE guest_base
#define RESERVED_VA reserved_va
#else
#define GUEST_BASE 0ul
#define RESERVED_VA 0ul
#endif

/* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))

#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
#define h2g_valid(x) 1
#else
#define h2g_valid(x) ({ \
    unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
    (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
    (!RESERVED_VA || (__guest < RESERVED_VA)); \
})
#endif

#define h2g(x) ({ \
    unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
    /* Check if given address fits target address space */ \
    assert(h2g_valid(x)); \
    (abi_ulong)__ret; \
})

#define saddr(x) g2h(x)
#define laddr(x) g2h(x)

#else /* !CONFIG_USER_ONLY */
/* NOTE: we use double casts if pointers and target_ulong have
   different sizes */
#define saddr(x) (uint8_t *)(intptr_t)(x)
#define laddr(x) (uint8_t *)(intptr_t)(x)
#endif

#define ldub_raw(p) ldub_p(laddr((p)))
#define ldsb_raw(p) ldsb_p(laddr((p)))
#define lduw_raw(p) lduw_p(laddr((p)))
#define ldsw_raw(p) ldsw_p(laddr((p)))
#define ldl_raw(p) ldl_p(laddr((p)))
#define ldq_raw(p) ldq_p(laddr((p)))
#define ldfl_raw(p) ldfl_p(laddr((p)))
#define ldfq_raw(p) ldfq_p(laddr((p)))
#define stb_raw(p, v) stb_p(saddr((p)), v)
#define stw_raw(p, v) stw_p(saddr((p)), v)
#define stl_raw(p, v) stl_p(saddr((p)), v)
#define stq_raw(p, v) stq_p(saddr((p)), v)
#define stfl_raw(p, v) stfl_p(saddr((p)), v)
#define stfq_raw(p, v) stfq_p(saddr((p)), v)


#if defined(CONFIG_USER_ONLY)

/* if user mode, no other memory access functions */
#define ldub(p) ldub_raw(p)
#define ldsb(p) ldsb_raw(p)
#define lduw(p) lduw_raw(p)
#define ldsw(p) ldsw_raw(p)
#define ldl(p) ldl_raw(p)
#define ldq(p) ldq_raw(p)
#define ldfl(p) ldfl_raw(p)
#define ldfq(p) ldfq_raw(p)
#define stb(p, v) stb_raw(p, v)
#define stw(p, v) stw_raw(p, v)
#define stl(p, v) stl_raw(p, v)
#define stq(p, v) stq_raw(p, v)
#define stfl(p, v) stfl_raw(p, v)
#define stfq(p, v) stfq_raw(p, v)

#define cpu_ldub_code(env1, p) ldub_raw(p)
#define cpu_ldsb_code(env1, p) ldsb_raw(p)
#define cpu_lduw_code(env1, p) lduw_raw(p)
#define cpu_ldsw_code(env1, p) ldsw_raw(p)
#define cpu_ldl_code(env1, p) ldl_raw(p)
#define cpu_ldq_code(env1, p) ldq_raw(p)

#define cpu_ldub_data(env, addr) ldub_raw(addr)
#define cpu_lduw_data(env, addr) lduw_raw(addr)
#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
#define cpu_ldl_data(env, addr) ldl_raw(addr)
#define cpu_ldq_data(env, addr) ldq_raw(addr)

#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
#define cpu_stq_data(env, addr, data) stq_raw(addr, data)

#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
#define cpu_ldq_kernel(env, addr) ldq_raw(addr)

#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)

#define ldub_kernel(p) ldub_raw(p)
#define ldsb_kernel(p) ldsb_raw(p)
#define lduw_kernel(p) lduw_raw(p)
#define ldsw_kernel(p) ldsw_raw(p)
#define ldl_kernel(p) ldl_raw(p)
#define ldq_kernel(p) ldq_raw(p)
#define ldfl_kernel(p) ldfl_raw(p)
#define ldfq_kernel(p) ldfq_raw(p)
#define stb_kernel(p, v) stb_raw(p, v)
#define stw_kernel(p, v) stw_raw(p, v)
#define stl_kernel(p, v) stl_raw(p, v)
#define stq_kernel(p, v) stq_raw(p, v)
#define stfl_kernel(p, v) stfl_raw(p, v)
#define stfq_kernel(p, vt) stfq_raw(p, v)

#define cpu_ldub_data(env, addr) ldub_raw(addr)
#define cpu_lduw_data(env, addr) lduw_raw(addr)
#define cpu_ldl_data(env, addr) ldl_raw(addr)

#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
#endif /* defined(CONFIG_USER_ONLY) */

/* page related stuff */

#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)

/* ??? These should be the larger of uintptr_t and target_ulong.  */
extern uintptr_t qemu_real_host_page_size;
extern uintptr_t qemu_host_page_size;
extern uintptr_t qemu_host_page_mask;

#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)

/* same as PROT_xxx */
#define PAGE_READ      0x0001
#define PAGE_WRITE     0x0002
#define PAGE_EXEC      0x0004
#define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
#define PAGE_VALID     0x0008
/* original state of the write flag (used when tracking self-modifying
   code */
#define PAGE_WRITE_ORG 0x0010
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
/* FIXME: Code that sets/uses this is broken and needs to go away.  */
#define PAGE_RESERVED  0x0020
#endif

#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);

typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
                                      abi_ulong, unsigned long);
int walk_memory_regions(void *, walk_memory_regions_fn);

int page_get_flags(target_ulong address);
void page_set_flags(target_ulong start, target_ulong end, int flags);
int page_check_range(target_ulong start, target_ulong len, int flags);
#endif

CPUArchState *cpu_copy(CPUArchState *env);

void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
    GCC_FMT_ATTR(2, 3);

/* Flags for use in ENV->INTERRUPT_PENDING.

   The numbers assigned here are non-sequential in order to preserve
   binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
   previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
   the vmstate dump.  */

/* External hardware interrupt pending.  This is typically used for
   interrupts from devices.  */
#define CPU_INTERRUPT_HARD        0x0002

/* Exit the current TB.  This is typically used when some system-level device
   makes some change to the memory mapping.  E.g. the a20 line change.  */
#define CPU_INTERRUPT_EXITTB      0x0004

/* Halt the CPU.  */
#define CPU_INTERRUPT_HALT        0x0020

/* Debug event pending.  */
#define CPU_INTERRUPT_DEBUG       0x0080

/* Several target-specific external hardware interrupts.  Each target/cpu.h
   should define proper names based on these defines.  */
#define CPU_INTERRUPT_TGT_EXT_0   0x0008
#define CPU_INTERRUPT_TGT_EXT_1   0x0010
#define CPU_INTERRUPT_TGT_EXT_2   0x0040
#define CPU_INTERRUPT_TGT_EXT_3   0x0200
#define CPU_INTERRUPT_TGT_EXT_4   0x1000

/* Several target-specific internal interrupts.  These differ from the
   preceding target-specific interrupts in that they are intended to
   originate from within the cpu itself, typically in response to some
   instruction being executed.  These, therefore, are not masked while
   single-stepping within the debugger.  */
#define CPU_INTERRUPT_TGT_INT_0   0x0100
#define CPU_INTERRUPT_TGT_INT_1   0x0400
#define CPU_INTERRUPT_TGT_INT_2   0x0800
#define CPU_INTERRUPT_TGT_INT_3   0x2000

/* First unused bit: 0x4000.  */

/* The set of all bits that should be masked when single-stepping.  */
#define CPU_INTERRUPT_SSTEP_MASK \
    (CPU_INTERRUPT_HARD          \
     | CPU_INTERRUPT_TGT_EXT_0   \
     | CPU_INTERRUPT_TGT_EXT_1   \
     | CPU_INTERRUPT_TGT_EXT_2   \
     | CPU_INTERRUPT_TGT_EXT_3   \
     | CPU_INTERRUPT_TGT_EXT_4)

/* Breakpoint/watchpoint flags */
#define BP_MEM_READ           0x01
#define BP_MEM_WRITE          0x02
#define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
#define BP_STOP_BEFORE_ACCESS 0x04
#define BP_WATCHPOINT_HIT     0x08
#define BP_GDB                0x10
#define BP_CPU                0x20

int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
                          CPUBreakpoint **breakpoint);
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
                          int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
                          target_ulong len, int flags);
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUArchState *env, int mask);

#if !defined(CONFIG_USER_ONLY)

/* memory API */

extern ram_addr_t ram_size;

/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
#define RAM_PREALLOC_MASK   (1 << 0)

typedef struct RAMBlock {
    struct MemoryRegion *mr;
    uint8_t *host;
    ram_addr_t offset;
    ram_addr_t length;
    uint32_t flags;
    char idstr[256];
    /* Reads can take either the iothread or the ramlist lock.
     * Writes must take both locks.
     */
    QTAILQ_ENTRY(RAMBlock) next;
#if defined(__linux__) && !defined(TARGET_S390X)
    int fd;
#endif
} RAMBlock;

typedef struct RAMList {
    QemuMutex mutex;
    /* Protected by the iothread lock.  */
    uint8_t *phys_dirty;
    RAMBlock *mru_block;
    /* Protected by the ramlist lock.  */
    QTAILQ_HEAD(, RAMBlock) blocks;
    uint32_t version;
} RAMList;
extern RAMList ram_list;

extern const char *mem_path;
extern int mem_prealloc;

/* Flags stored in the low bits of the TLB virtual address.  These are
   defined so that fast path ram access is all zeros.  */
/* Zero if TLB entry is valid.  */
#define TLB_INVALID_MASK   (1 << 3)
/* Set if TLB entry references a clean RAM page.  The iotlb entry will
   contain the page physical address.  */
#define TLB_NOTDIRTY    (1 << 4)
/* Set if TLB entry is an IO callback.  */
#define TLB_MMIO        (1 << 5)

void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
ram_addr_t last_ram_offset(void);
void qemu_mutex_lock_ramlist(void);
void qemu_mutex_unlock_ramlist(void);
#endif /* !CONFIG_USER_ONLY */

int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
                        uint8_t *buf, int len, int is_write);

#endif /* CPU_ALL_H */
Commit	Line	Data
5a9fdfec FB	1	/*
5a9fdfec FB	2	* defines common to all virtual CPUs
5fafdf24	3	*
5a9fdfec FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
5a9fdfec FB	18	*/
	19	#ifndef CPU_ALL_H
	20	#define CPU_ALL_H
	21
7d99a001	22	#include "qemu-common.h"
022c62cb	23	#include "exec/cpu-common.h"
b2a8658e	24	#include "qemu/thread.h"
0ac4bd56	25
5fafdf24 TS	26	/* some important defines:
5fafdf24 TS	27	*
0ac4bd56 FB	28	* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
0ac4bd56 FB	29	* memory accesses.
5fafdf24	30	*
e2542fe2	31	* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
0ac4bd56	32	* otherwise little endian.
5fafdf24	33	*
0ac4bd56	34	* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
5fafdf24	35	*
0ac4bd56 FB	36	* TARGET_WORDS_BIGENDIAN : same for target cpu
	37	*/
	38
e2542fe2	39	#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
f193c797 FB	40	#define BSWAP_NEEDED
	41	#endif
	42
	43	#ifdef BSWAP_NEEDED
	44
	45	static inline uint16_t tswap16(uint16_t s)
	46	{
	47	return bswap16(s);
	48	}
	49
	50	static inline uint32_t tswap32(uint32_t s)
	51	{
	52	return bswap32(s);
	53	}
	54
	55	static inline uint64_t tswap64(uint64_t s)
	56	{
	57	return bswap64(s);
	58	}
	59
	60	static inline void tswap16s(uint16_t *s)
	61	{
	62	s = bswap16(s);
	63	}
	64
	65	static inline void tswap32s(uint32_t *s)
	66	{
	67	s = bswap32(s);
	68	}
	69
	70	static inline void tswap64s(uint64_t *s)
	71	{
	72	s = bswap64(s);
	73	}
	74
	75	#else
	76
	77	static inline uint16_t tswap16(uint16_t s)
	78	{
	79	return s;
	80	}
	81
	82	static inline uint32_t tswap32(uint32_t s)
	83	{
	84	return s;
	85	}
	86
	87	static inline uint64_t tswap64(uint64_t s)
	88	{
	89	return s;
	90	}
	91
	92	static inline void tswap16s(uint16_t *s)
	93	{
	94	}
	95
	96	static inline void tswap32s(uint32_t *s)
	97	{
	98	}
	99
	100	static inline void tswap64s(uint64_t *s)
	101	{
	102	}
	103
104	#endif
105
106	#if TARGET_LONG_SIZE == 4
107	#define tswapl(s) tswap32(s)
108	#define tswapls(s) tswap32s((uint32_t *)(s))
0a962c02	109	#define bswaptls(s) bswap32s(s)
f193c797 FB	110	#else
	111	#define tswapl(s) tswap64(s)
	112	#define tswapls(s) tswap64s((uint64_t *)(s))
0a962c02	113	#define bswaptls(s) bswap64s(s)
f193c797 FB	114	#endif
f193c797 FB	115
61382a50 FB	116	/* CPU memory access without any memory or io remapping */
61382a50 FB	117
83d73968 FB	118	/*
	119	* the generic syntax for the memory accesses is:
	120	*
	121	* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
	122	*
	123	* store: st{type}{size}{endian}_{access_type}(ptr, val)
	124	*
	125	* type is:
	126	* (empty): integer access
	127	* f : float access
5fafdf24	128	*
83d73968 FB	129	* sign is:
	130	* (empty): for floats or 32 bit size
	131	* u : unsigned
	132	* s : signed
	133	*
	134	* size is:
	135	* b: 8 bits
	136	* w: 16 bits
	137	* l: 32 bits
	138	* q: 64 bits
5fafdf24	139	*
83d73968 FB	140	* endian is:
	141	* (empty): target cpu endianness or 8 bit access
	142	* r : reversed target cpu endianness (not implemented yet)
	143	* be : big endian (not implemented yet)
	144	* le : little endian (not implemented yet)
	145	*
	146	* access_type is:
	147	* raw : host memory access
	148	* user : user mode access using soft MMU
	149	* kernel : kernel mode access using soft MMU
	150	*/
2df3b95d	151
cbbab922	152	/* target-endianness CPU memory access functions */
2df3b95d FB	153	#if defined(TARGET_WORDS_BIGENDIAN)
	154	#define lduw_p(p) lduw_be_p(p)
	155	#define ldsw_p(p) ldsw_be_p(p)
	156	#define ldl_p(p) ldl_be_p(p)
	157	#define ldq_p(p) ldq_be_p(p)
	158	#define ldfl_p(p) ldfl_be_p(p)
	159	#define ldfq_p(p) ldfq_be_p(p)
	160	#define stw_p(p, v) stw_be_p(p, v)
	161	#define stl_p(p, v) stl_be_p(p, v)
	162	#define stq_p(p, v) stq_be_p(p, v)
	163	#define stfl_p(p, v) stfl_be_p(p, v)
	164	#define stfq_p(p, v) stfq_be_p(p, v)
	165	#else
	166	#define lduw_p(p) lduw_le_p(p)
	167	#define ldsw_p(p) ldsw_le_p(p)
	168	#define ldl_p(p) ldl_le_p(p)
	169	#define ldq_p(p) ldq_le_p(p)
	170	#define ldfl_p(p) ldfl_le_p(p)
	171	#define ldfq_p(p) ldfq_le_p(p)
	172	#define stw_p(p, v) stw_le_p(p, v)
	173	#define stl_p(p, v) stl_le_p(p, v)
	174	#define stq_p(p, v) stq_le_p(p, v)
	175	#define stfl_p(p, v) stfl_le_p(p, v)
	176	#define stfq_p(p, v) stfq_le_p(p, v)
5a9fdfec FB	177	#endif
5a9fdfec FB	178
61382a50 FB	179	/* MMU memory access macros */
61382a50 FB	180
53a5960a	181	#if defined(CONFIG_USER_ONLY)
0e62fd79	182	#include <assert.h>
022c62cb	183	#include "exec/user/abitypes.h"
0e62fd79	184
53a5960a PB	185	/* On some host systems the guest address space is reserved on the host.
	186	* This allows the guest address space to be offset to a convenient location.
	187	*/
379f6698 PB	188	#if defined(CONFIG_USE_GUEST_BASE)
	189	extern unsigned long guest_base;
	190	extern int have_guest_base;
68a1c816	191	extern unsigned long reserved_va;
379f6698	192	#define GUEST_BASE guest_base
18e9ea8a	193	#define RESERVED_VA reserved_va
379f6698 PB	194	#else
379f6698 PB	195	#define GUEST_BASE 0ul
18e9ea8a	196	#define RESERVED_VA 0ul
379f6698	197	#endif
53a5960a PB	198
53a5960a PB	199	/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
8d9dde94	200	#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
b9f83121 RH	201
	202	#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
	203	#define h2g_valid(x) 1
	204	#else
	205	#define h2g_valid(x) ({ \
	206	unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
39879bbb AG	207	(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
39879bbb AG	208	(!RESERVED_VA \|\| (__guest < RESERVED_VA)); \
b9f83121 RH	209	})
	210	#endif
	211
0e62fd79 AJ	212	#define h2g(x) ({ \
	213	unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
	214	/* Check if given address fits target address space */ \
b9f83121	215	assert(h2g_valid(x)); \
0e62fd79 AJ	216	(abi_ulong)__ret; \
0e62fd79 AJ	217	})
53a5960a PB	218
	219	#define saddr(x) g2h(x)
	220	#define laddr(x) g2h(x)
	221
	222	#else /* !CONFIG_USER_ONLY */
c27004ec FB	223	/* NOTE: we use double casts if pointers and target_ulong have
c27004ec FB	224	different sizes */
27b0dc16 SW	225	#define saddr(x) (uint8_t *)(intptr_t)(x)
27b0dc16 SW	226	#define laddr(x) (uint8_t *)(intptr_t)(x)
53a5960a PB	227	#endif
	228
	229	#define ldub_raw(p) ldub_p(laddr((p)))
	230	#define ldsb_raw(p) ldsb_p(laddr((p)))
	231	#define lduw_raw(p) lduw_p(laddr((p)))
	232	#define ldsw_raw(p) ldsw_p(laddr((p)))
	233	#define ldl_raw(p) ldl_p(laddr((p)))
	234	#define ldq_raw(p) ldq_p(laddr((p)))
	235	#define ldfl_raw(p) ldfl_p(laddr((p)))
	236	#define ldfq_raw(p) ldfq_p(laddr((p)))
	237	#define stb_raw(p, v) stb_p(saddr((p)), v)
	238	#define stw_raw(p, v) stw_p(saddr((p)), v)
	239	#define stl_raw(p, v) stl_p(saddr((p)), v)
	240	#define stq_raw(p, v) stq_p(saddr((p)), v)
	241	#define stfl_raw(p, v) stfl_p(saddr((p)), v)
	242	#define stfq_raw(p, v) stfq_p(saddr((p)), v)
c27004ec FB	243
c27004ec FB	244
5fafdf24	245	#if defined(CONFIG_USER_ONLY)
61382a50 FB	246
	247	/* if user mode, no other memory access functions */
	248	#define ldub(p) ldub_raw(p)
	249	#define ldsb(p) ldsb_raw(p)
	250	#define lduw(p) lduw_raw(p)
	251	#define ldsw(p) ldsw_raw(p)
	252	#define ldl(p) ldl_raw(p)
	253	#define ldq(p) ldq_raw(p)
	254	#define ldfl(p) ldfl_raw(p)
	255	#define ldfq(p) ldfq_raw(p)
	256	#define stb(p, v) stb_raw(p, v)
	257	#define stw(p, v) stw_raw(p, v)
	258	#define stl(p, v) stl_raw(p, v)
	259	#define stq(p, v) stq_raw(p, v)
	260	#define stfl(p, v) stfl_raw(p, v)
	261	#define stfq(p, v) stfq_raw(p, v)
	262
e141ab52 BS	263	#define cpu_ldub_code(env1, p) ldub_raw(p)
	264	#define cpu_ldsb_code(env1, p) ldsb_raw(p)
	265	#define cpu_lduw_code(env1, p) lduw_raw(p)
	266	#define cpu_ldsw_code(env1, p) ldsw_raw(p)
	267	#define cpu_ldl_code(env1, p) ldl_raw(p)
	268	#define cpu_ldq_code(env1, p) ldq_raw(p)
92fc4b58 BS	269
	270	#define cpu_ldub_data(env, addr) ldub_raw(addr)
	271	#define cpu_lduw_data(env, addr) lduw_raw(addr)
	272	#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
	273	#define cpu_ldl_data(env, addr) ldl_raw(addr)
	274	#define cpu_ldq_data(env, addr) ldq_raw(addr)
	275
	276	#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
	277	#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
	278	#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
	279	#define cpu_stq_data(env, addr, data) stq_raw(addr, data)
	280
	281	#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
	282	#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
	283	#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
	284	#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
	285	#define cpu_ldq_kernel(env, addr) ldq_raw(addr)
	286
	287	#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
	288	#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
	289	#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
	290	#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
61382a50 FB	291
	292	#define ldub_kernel(p) ldub_raw(p)
	293	#define ldsb_kernel(p) ldsb_raw(p)
	294	#define lduw_kernel(p) lduw_raw(p)
	295	#define ldsw_kernel(p) ldsw_raw(p)
	296	#define ldl_kernel(p) ldl_raw(p)
bc98a7ef	297	#define ldq_kernel(p) ldq_raw(p)
0ac4bd56 FB	298	#define ldfl_kernel(p) ldfl_raw(p)
0ac4bd56 FB	299	#define ldfq_kernel(p) ldfq_raw(p)
61382a50 FB	300	#define stb_kernel(p, v) stb_raw(p, v)
	301	#define stw_kernel(p, v) stw_raw(p, v)
	302	#define stl_kernel(p, v) stl_raw(p, v)
	303	#define stq_kernel(p, v) stq_raw(p, v)
0ac4bd56 FB	304	#define stfl_kernel(p, v) stfl_raw(p, v)
0ac4bd56 FB	305	#define stfq_kernel(p, vt) stfq_raw(p, v)
61382a50	306
2f5a189c BS	307	#define cpu_ldub_data(env, addr) ldub_raw(addr)
	308	#define cpu_lduw_data(env, addr) lduw_raw(addr)
	309	#define cpu_ldl_data(env, addr) ldl_raw(addr)
	310
	311	#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
	312	#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
	313	#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
61382a50 FB	314	#endif /* defined(CONFIG_USER_ONLY) */
61382a50 FB	315
5a9fdfec FB	316	/* page related stuff */
5a9fdfec FB	317
03875444	318	#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
5a9fdfec FB	319	#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
	320	#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
	321
c6d50674 SW	322	/* ??? These should be the larger of uintptr_t and target_ulong. */
	323	extern uintptr_t qemu_real_host_page_size;
	324	extern uintptr_t qemu_host_page_size;
	325	extern uintptr_t qemu_host_page_mask;
5a9fdfec	326
83fb7adf	327	#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
5a9fdfec FB	328
	329	/* same as PROT_xxx */
	330	#define PAGE_READ 0x0001
	331	#define PAGE_WRITE 0x0002
	332	#define PAGE_EXEC 0x0004
	333	#define PAGE_BITS (PAGE_READ \| PAGE_WRITE \| PAGE_EXEC)
	334	#define PAGE_VALID 0x0008
	335	/* original state of the write flag (used when tracking self-modifying
	336	code */
5fafdf24	337	#define PAGE_WRITE_ORG 0x0010
2e9a5713 PB	338	#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
2e9a5713 PB	339	/* FIXME: Code that sets/uses this is broken and needs to go away. */
50a9569b	340	#define PAGE_RESERVED 0x0020
2e9a5713	341	#endif
5a9fdfec	342
b480d9b7	343	#if defined(CONFIG_USER_ONLY)
5a9fdfec	344	void page_dump(FILE *f);
5cd2c5b6	345
b480d9b7 PB	346	typedef int (walk_memory_regions_fn)(void , abi_ulong,
b480d9b7 PB	347	abi_ulong, unsigned long);
5cd2c5b6 RH	348	int walk_memory_regions(void *, walk_memory_regions_fn);
5cd2c5b6 RH	349
53a5960a PB	350	int page_get_flags(target_ulong address);
53a5960a PB	351	void page_set_flags(target_ulong start, target_ulong end, int flags);
3d97b40b	352	int page_check_range(target_ulong start, target_ulong len, int flags);
b480d9b7	353	#endif
5a9fdfec	354
9349b4f9	355	CPUArchState cpu_copy(CPUArchState env);
c5be9f08	356
9349b4f9	357	void QEMU_NORETURN cpu_abort(CPUArchState env, const char fmt, ...)
2c80e423	358	GCC_FMT_ATTR(2, 3);
db1a4972	359
9c76219e RH	360	/* Flags for use in ENV->INTERRUPT_PENDING.
	361
	362	The numbers assigned here are non-sequential in order to preserve
	363	binary compatibility with the vmstate dump. Bit 0 (0x0001) was
	364	previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
	365	the vmstate dump. */
	366
	367	/* External hardware interrupt pending. This is typically used for
	368	interrupts from devices. */
	369	#define CPU_INTERRUPT_HARD 0x0002
	370
	371	/* Exit the current TB. This is typically used when some system-level device
	372	makes some change to the memory mapping. E.g. the a20 line change. */
	373	#define CPU_INTERRUPT_EXITTB 0x0004
	374
	375	/* Halt the CPU. */
	376	#define CPU_INTERRUPT_HALT 0x0020
	377
	378	/* Debug event pending. */
	379	#define CPU_INTERRUPT_DEBUG 0x0080
	380
	381	/* Several target-specific external hardware interrupts. Each target/cpu.h
	382	should define proper names based on these defines. */
	383	#define CPU_INTERRUPT_TGT_EXT_0 0x0008
	384	#define CPU_INTERRUPT_TGT_EXT_1 0x0010
	385	#define CPU_INTERRUPT_TGT_EXT_2 0x0040
	386	#define CPU_INTERRUPT_TGT_EXT_3 0x0200
	387	#define CPU_INTERRUPT_TGT_EXT_4 0x1000
	388
	389	/* Several target-specific internal interrupts. These differ from the
07f35073	390	preceding target-specific interrupts in that they are intended to
9c76219e RH	391	originate from within the cpu itself, typically in response to some
	392	instruction being executed. These, therefore, are not masked while
	393	single-stepping within the debugger. */
	394	#define CPU_INTERRUPT_TGT_INT_0 0x0100
	395	#define CPU_INTERRUPT_TGT_INT_1 0x0400
	396	#define CPU_INTERRUPT_TGT_INT_2 0x0800
d362e757	397	#define CPU_INTERRUPT_TGT_INT_3 0x2000
9c76219e	398
d362e757	399	/* First unused bit: 0x4000. */
9c76219e	400
3125f763 RH	401	/* The set of all bits that should be masked when single-stepping. */
	402	#define CPU_INTERRUPT_SSTEP_MASK \
	403	(CPU_INTERRUPT_HARD \
	404	\| CPU_INTERRUPT_TGT_EXT_0 \
	405	\| CPU_INTERRUPT_TGT_EXT_1 \
	406	\| CPU_INTERRUPT_TGT_EXT_2 \
	407	\| CPU_INTERRUPT_TGT_EXT_3 \
	408	\| CPU_INTERRUPT_TGT_EXT_4)
98699967	409
a1d1bb31 AL	410	/* Breakpoint/watchpoint flags */
	411	#define BP_MEM_READ 0x01
	412	#define BP_MEM_WRITE 0x02
	413	#define BP_MEM_ACCESS (BP_MEM_READ \| BP_MEM_WRITE)
06d55cc1	414	#define BP_STOP_BEFORE_ACCESS 0x04
6e140f28	415	#define BP_WATCHPOINT_HIT 0x08
a1d1bb31	416	#define BP_GDB 0x10
2dc9f411	417	#define BP_CPU 0x20
a1d1bb31	418
9349b4f9	419	int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
a1d1bb31	420	CPUBreakpoint **breakpoint);
9349b4f9 AF	421	int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
	422	void cpu_breakpoint_remove_by_ref(CPUArchState env, CPUBreakpoint breakpoint);
	423	void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
	424	int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
a1d1bb31	425	int flags, CPUWatchpoint **watchpoint);
9349b4f9	426	int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
a1d1bb31	427	target_ulong len, int flags);
9349b4f9 AF	428	void cpu_watchpoint_remove_by_ref(CPUArchState env, CPUWatchpoint watchpoint);
9349b4f9 AF	429	void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
60897d36	430
b3755a91 PB	431	#if !defined(CONFIG_USER_ONLY)
b3755a91 PB	432
33417e70 FB	433	/* memory API */
33417e70 FB	434
c227f099	435	extern ram_addr_t ram_size;
f471a17e	436
cd19cfa2 HY	437	/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
	438	#define RAM_PREALLOC_MASK (1 << 0)
	439
f471a17e	440	typedef struct RAMBlock {
7c637366	441	struct MemoryRegion *mr;
f471a17e AW	442	uint8_t *host;
	443	ram_addr_t offset;
	444	ram_addr_t length;
cd19cfa2	445	uint32_t flags;
cc9e98cb	446	char idstr[256];
b2a8658e UD	447	/* Reads can take either the iothread or the ramlist lock.
	448	* Writes must take both locks.
	449	*/
a3161038	450	QTAILQ_ENTRY(RAMBlock) next;
04b16653 AW	451	#if defined(__linux__) && !defined(TARGET_S390X)
	452	int fd;
	453	#endif
f471a17e AW	454	} RAMBlock;
	455
	456	typedef struct RAMList {
b2a8658e UD	457	QemuMutex mutex;
b2a8658e UD	458	/* Protected by the iothread lock. */
f471a17e	459	uint8_t *phys_dirty;
0d6d3c87	460	RAMBlock *mru_block;
b2a8658e	461	/* Protected by the ramlist lock. */
a3161038	462	QTAILQ_HEAD(, RAMBlock) blocks;
f798b07f	463	uint32_t version;
f471a17e AW	464	} RAMList;
f471a17e AW	465	extern RAMList ram_list;
edf75d59	466
c902760f MT	467	extern const char *mem_path;
	468	extern int mem_prealloc;
	469
0f459d16 PB	470	/* Flags stored in the low bits of the TLB virtual address. These are
	471	defined so that fast path ram access is all zeros. */
	472	/* Zero if TLB entry is valid. */
	473	#define TLB_INVALID_MASK (1 << 3)
	474	/* Set if TLB entry references a clean RAM page. The iotlb entry will
	475	contain the page physical address. */
	476	#define TLB_NOTDIRTY (1 << 4)
	477	/* Set if TLB entry is an IO callback. */
	478	#define TLB_MMIO (1 << 5)
	479
055403b2	480	void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
652d7ec2	481	ram_addr_t last_ram_offset(void);
b2a8658e UD	482	void qemu_mutex_lock_ramlist(void);
b2a8658e UD	483	void qemu_mutex_unlock_ramlist(void);
b3755a91 PB	484	#endif /* !CONFIG_USER_ONLY */
b3755a91 PB	485
9349b4f9	486	int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
b3755a91 PB	487	uint8_t *buf, int len, int is_write);
b3755a91 PB	488
5a9fdfec	489	#endif /* CPU_ALL_H */