]>
Commit | Line | Data |
---|---|---|
5a9fdfec FB |
1 | /* |
2 | * defines common to all virtual CPUs | |
5fafdf24 | 3 | * |
5a9fdfec FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
5a9fdfec FB |
18 | */ |
19 | #ifndef CPU_ALL_H | |
20 | #define CPU_ALL_H | |
21 | ||
7d99a001 | 22 | #include "qemu-common.h" |
022c62cb | 23 | #include "exec/cpu-common.h" |
1ab4c8ce | 24 | #include "exec/memory.h" |
b2a8658e | 25 | #include "qemu/thread.h" |
f17ec444 | 26 | #include "qom/cpu.h" |
43771539 | 27 | #include "qemu/rcu.h" |
0ac4bd56 | 28 | |
9e0dc48c PC |
29 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
30 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ | |
31 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ | |
32 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ | |
33 | #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ | |
34 | ||
5fafdf24 | 35 | /* some important defines: |
5fafdf24 | 36 | * |
e2542fe2 | 37 | * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
0ac4bd56 | 38 | * otherwise little endian. |
5fafdf24 | 39 | * |
0ac4bd56 FB |
40 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
41 | */ | |
42 | ||
e2542fe2 | 43 | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
f193c797 FB |
44 | #define BSWAP_NEEDED |
45 | #endif | |
46 | ||
47 | #ifdef BSWAP_NEEDED | |
48 | ||
49 | static inline uint16_t tswap16(uint16_t s) | |
50 | { | |
51 | return bswap16(s); | |
52 | } | |
53 | ||
54 | static inline uint32_t tswap32(uint32_t s) | |
55 | { | |
56 | return bswap32(s); | |
57 | } | |
58 | ||
59 | static inline uint64_t tswap64(uint64_t s) | |
60 | { | |
61 | return bswap64(s); | |
62 | } | |
63 | ||
64 | static inline void tswap16s(uint16_t *s) | |
65 | { | |
66 | *s = bswap16(*s); | |
67 | } | |
68 | ||
69 | static inline void tswap32s(uint32_t *s) | |
70 | { | |
71 | *s = bswap32(*s); | |
72 | } | |
73 | ||
74 | static inline void tswap64s(uint64_t *s) | |
75 | { | |
76 | *s = bswap64(*s); | |
77 | } | |
78 | ||
79 | #else | |
80 | ||
81 | static inline uint16_t tswap16(uint16_t s) | |
82 | { | |
83 | return s; | |
84 | } | |
85 | ||
86 | static inline uint32_t tswap32(uint32_t s) | |
87 | { | |
88 | return s; | |
89 | } | |
90 | ||
91 | static inline uint64_t tswap64(uint64_t s) | |
92 | { | |
93 | return s; | |
94 | } | |
95 | ||
96 | static inline void tswap16s(uint16_t *s) | |
97 | { | |
98 | } | |
99 | ||
100 | static inline void tswap32s(uint32_t *s) | |
101 | { | |
102 | } | |
103 | ||
104 | static inline void tswap64s(uint64_t *s) | |
105 | { | |
106 | } | |
107 | ||
108 | #endif | |
109 | ||
110 | #if TARGET_LONG_SIZE == 4 | |
111 | #define tswapl(s) tswap32(s) | |
112 | #define tswapls(s) tswap32s((uint32_t *)(s)) | |
0a962c02 | 113 | #define bswaptls(s) bswap32s(s) |
f193c797 FB |
114 | #else |
115 | #define tswapl(s) tswap64(s) | |
116 | #define tswapls(s) tswap64s((uint64_t *)(s)) | |
0a962c02 | 117 | #define bswaptls(s) bswap64s(s) |
f193c797 FB |
118 | #endif |
119 | ||
db5fd8d7 PM |
120 | /* Target-endianness CPU memory access functions. These fit into the |
121 | * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. | |
83d73968 | 122 | */ |
2df3b95d FB |
123 | #if defined(TARGET_WORDS_BIGENDIAN) |
124 | #define lduw_p(p) lduw_be_p(p) | |
125 | #define ldsw_p(p) ldsw_be_p(p) | |
126 | #define ldl_p(p) ldl_be_p(p) | |
127 | #define ldq_p(p) ldq_be_p(p) | |
128 | #define ldfl_p(p) ldfl_be_p(p) | |
129 | #define ldfq_p(p) ldfq_be_p(p) | |
130 | #define stw_p(p, v) stw_be_p(p, v) | |
131 | #define stl_p(p, v) stl_be_p(p, v) | |
132 | #define stq_p(p, v) stq_be_p(p, v) | |
133 | #define stfl_p(p, v) stfl_be_p(p, v) | |
134 | #define stfq_p(p, v) stfq_be_p(p, v) | |
135 | #else | |
136 | #define lduw_p(p) lduw_le_p(p) | |
137 | #define ldsw_p(p) ldsw_le_p(p) | |
138 | #define ldl_p(p) ldl_le_p(p) | |
139 | #define ldq_p(p) ldq_le_p(p) | |
140 | #define ldfl_p(p) ldfl_le_p(p) | |
141 | #define ldfq_p(p) ldfq_le_p(p) | |
142 | #define stw_p(p, v) stw_le_p(p, v) | |
143 | #define stl_p(p, v) stl_le_p(p, v) | |
144 | #define stq_p(p, v) stq_le_p(p, v) | |
145 | #define stfl_p(p, v) stfl_le_p(p, v) | |
146 | #define stfq_p(p, v) stfq_le_p(p, v) | |
5a9fdfec FB |
147 | #endif |
148 | ||
61382a50 FB |
149 | /* MMU memory access macros */ |
150 | ||
53a5960a | 151 | #if defined(CONFIG_USER_ONLY) |
022c62cb | 152 | #include "exec/user/abitypes.h" |
0e62fd79 | 153 | |
53a5960a PB |
154 | /* On some host systems the guest address space is reserved on the host. |
155 | * This allows the guest address space to be offset to a convenient location. | |
156 | */ | |
379f6698 PB |
157 | extern unsigned long guest_base; |
158 | extern int have_guest_base; | |
68a1c816 | 159 | extern unsigned long reserved_va; |
53a5960a | 160 | |
b76f21a7 | 161 | #define GUEST_ADDR_MAX (reserved_va ? reserved_va : \ |
d67f4aaa | 162 | (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1) |
a7d6039c PB |
163 | #else |
164 | ||
165 | #include "exec/hwaddr.h" | |
166 | uint32_t lduw_phys(AddressSpace *as, hwaddr addr); | |
167 | uint32_t ldl_phys(AddressSpace *as, hwaddr addr); | |
168 | uint64_t ldq_phys(AddressSpace *as, hwaddr addr); | |
169 | void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val); | |
170 | void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
171 | void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
172 | void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val); | |
173 | ||
174 | uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, | |
175 | MemTxAttrs attrs, MemTxResult *result); | |
176 | uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, | |
177 | MemTxAttrs attrs, MemTxResult *result); | |
178 | uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, | |
179 | MemTxAttrs attrs, MemTxResult *result); | |
180 | void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, | |
181 | MemTxAttrs attrs, MemTxResult *result); | |
182 | void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, | |
183 | MemTxAttrs attrs, MemTxResult *result); | |
184 | void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, | |
185 | MemTxAttrs attrs, MemTxResult *result); | |
186 | void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, | |
187 | MemTxAttrs attrs, MemTxResult *result); | |
53a5960a PB |
188 | #endif |
189 | ||
5a9fdfec FB |
190 | /* page related stuff */ |
191 | ||
20bccb82 PM |
192 | #ifdef TARGET_PAGE_BITS_VARY |
193 | extern bool target_page_bits_decided; | |
194 | extern int target_page_bits; | |
195 | #define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \ | |
196 | target_page_bits; }) | |
197 | #else | |
198 | #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS | |
199 | #endif | |
200 | ||
03875444 | 201 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
5a9fdfec FB |
202 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
203 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) | |
204 | ||
0c2d70c4 PB |
205 | /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even |
206 | * when intptr_t is 32-bit and we are aligning a long long. | |
207 | */ | |
c6d50674 | 208 | extern uintptr_t qemu_real_host_page_size; |
0c2d70c4 | 209 | extern intptr_t qemu_real_host_page_mask; |
c6d50674 | 210 | extern uintptr_t qemu_host_page_size; |
0c2d70c4 | 211 | extern intptr_t qemu_host_page_mask; |
5a9fdfec | 212 | |
83fb7adf | 213 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
4e51361d PC |
214 | #define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \ |
215 | qemu_real_host_page_mask) | |
5a9fdfec FB |
216 | |
217 | /* same as PROT_xxx */ | |
218 | #define PAGE_READ 0x0001 | |
219 | #define PAGE_WRITE 0x0002 | |
220 | #define PAGE_EXEC 0x0004 | |
221 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) | |
222 | #define PAGE_VALID 0x0008 | |
223 | /* original state of the write flag (used when tracking self-modifying | |
224 | code */ | |
5fafdf24 | 225 | #define PAGE_WRITE_ORG 0x0010 |
2e9a5713 PB |
226 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
227 | /* FIXME: Code that sets/uses this is broken and needs to go away. */ | |
50a9569b | 228 | #define PAGE_RESERVED 0x0020 |
2e9a5713 | 229 | #endif |
5a9fdfec | 230 | |
b480d9b7 | 231 | #if defined(CONFIG_USER_ONLY) |
5a9fdfec | 232 | void page_dump(FILE *f); |
5cd2c5b6 | 233 | |
1a1c4db9 MI |
234 | typedef int (*walk_memory_regions_fn)(void *, target_ulong, |
235 | target_ulong, unsigned long); | |
5cd2c5b6 RH |
236 | int walk_memory_regions(void *, walk_memory_regions_fn); |
237 | ||
53a5960a PB |
238 | int page_get_flags(target_ulong address); |
239 | void page_set_flags(target_ulong start, target_ulong end, int flags); | |
3d97b40b | 240 | int page_check_range(target_ulong start, target_ulong len, int flags); |
b480d9b7 | 241 | #endif |
5a9fdfec | 242 | |
9349b4f9 | 243 | CPUArchState *cpu_copy(CPUArchState *env); |
c5be9f08 | 244 | |
9c76219e RH |
245 | /* Flags for use in ENV->INTERRUPT_PENDING. |
246 | ||
247 | The numbers assigned here are non-sequential in order to preserve | |
248 | binary compatibility with the vmstate dump. Bit 0 (0x0001) was | |
249 | previously used for CPU_INTERRUPT_EXIT, and is cleared when loading | |
250 | the vmstate dump. */ | |
251 | ||
252 | /* External hardware interrupt pending. This is typically used for | |
253 | interrupts from devices. */ | |
254 | #define CPU_INTERRUPT_HARD 0x0002 | |
255 | ||
256 | /* Exit the current TB. This is typically used when some system-level device | |
257 | makes some change to the memory mapping. E.g. the a20 line change. */ | |
258 | #define CPU_INTERRUPT_EXITTB 0x0004 | |
259 | ||
260 | /* Halt the CPU. */ | |
261 | #define CPU_INTERRUPT_HALT 0x0020 | |
262 | ||
263 | /* Debug event pending. */ | |
264 | #define CPU_INTERRUPT_DEBUG 0x0080 | |
265 | ||
4a92a558 PB |
266 | /* Reset signal. */ |
267 | #define CPU_INTERRUPT_RESET 0x0400 | |
268 | ||
9c76219e RH |
269 | /* Several target-specific external hardware interrupts. Each target/cpu.h |
270 | should define proper names based on these defines. */ | |
271 | #define CPU_INTERRUPT_TGT_EXT_0 0x0008 | |
272 | #define CPU_INTERRUPT_TGT_EXT_1 0x0010 | |
273 | #define CPU_INTERRUPT_TGT_EXT_2 0x0040 | |
274 | #define CPU_INTERRUPT_TGT_EXT_3 0x0200 | |
275 | #define CPU_INTERRUPT_TGT_EXT_4 0x1000 | |
276 | ||
277 | /* Several target-specific internal interrupts. These differ from the | |
07f35073 | 278 | preceding target-specific interrupts in that they are intended to |
9c76219e RH |
279 | originate from within the cpu itself, typically in response to some |
280 | instruction being executed. These, therefore, are not masked while | |
281 | single-stepping within the debugger. */ | |
282 | #define CPU_INTERRUPT_TGT_INT_0 0x0100 | |
4a92a558 PB |
283 | #define CPU_INTERRUPT_TGT_INT_1 0x0800 |
284 | #define CPU_INTERRUPT_TGT_INT_2 0x2000 | |
9c76219e | 285 | |
d362e757 | 286 | /* First unused bit: 0x4000. */ |
9c76219e | 287 | |
3125f763 RH |
288 | /* The set of all bits that should be masked when single-stepping. */ |
289 | #define CPU_INTERRUPT_SSTEP_MASK \ | |
290 | (CPU_INTERRUPT_HARD \ | |
291 | | CPU_INTERRUPT_TGT_EXT_0 \ | |
292 | | CPU_INTERRUPT_TGT_EXT_1 \ | |
293 | | CPU_INTERRUPT_TGT_EXT_2 \ | |
294 | | CPU_INTERRUPT_TGT_EXT_3 \ | |
295 | | CPU_INTERRUPT_TGT_EXT_4) | |
98699967 | 296 | |
b3755a91 PB |
297 | #if !defined(CONFIG_USER_ONLY) |
298 | ||
0f459d16 | 299 | /* Flags stored in the low bits of the TLB virtual address. These are |
1f00b27f SS |
300 | * defined so that fast path ram access is all zeros. |
301 | * The flags all must be between TARGET_PAGE_BITS and | |
302 | * maximum address alignment bit. | |
303 | */ | |
0f459d16 | 304 | /* Zero if TLB entry is valid. */ |
1f00b27f | 305 | #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) |
0f459d16 PB |
306 | /* Set if TLB entry references a clean RAM page. The iotlb entry will |
307 | contain the page physical address. */ | |
1f00b27f | 308 | #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) |
0f459d16 | 309 | /* Set if TLB entry is an IO callback. */ |
1f00b27f SS |
310 | #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) |
311 | ||
312 | /* Use this mask to check interception with an alignment mask | |
313 | * in a TCG backend. | |
314 | */ | |
315 | #define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) | |
0f459d16 | 316 | |
055403b2 | 317 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); |
246ae24d | 318 | void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); |
b3755a91 PB |
319 | #endif /* !CONFIG_USER_ONLY */ |
320 | ||
f17ec444 | 321 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
b3755a91 PB |
322 | uint8_t *buf, int len, int is_write); |
323 | ||
8642c1b8 PC |
324 | int cpu_exec(CPUState *cpu); |
325 | ||
5a9fdfec | 326 | #endif /* CPU_ALL_H */ |