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5a9fdfec
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1/*
2 * defines common to all virtual CPUs
5fafdf24 3 *
5a9fdfec
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4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 */
19#ifndef CPU_ALL_H
20#define CPU_ALL_H
21
7d99a001 22#include "qemu-common.h"
022c62cb 23#include "exec/cpu-common.h"
1ab4c8ce 24#include "exec/memory.h"
b2a8658e 25#include "qemu/thread.h"
f17ec444 26#include "qom/cpu.h"
43771539 27#include "qemu/rcu.h"
0ac4bd56 28
9e0dc48c
PC
29#define EXCP_INTERRUPT 0x10000 /* async interruption */
30#define EXCP_HLT 0x10001 /* hlt instruction reached */
31#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
32#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
33#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
34
5fafdf24
TS
35/* some important defines:
36 *
0ac4bd56
FB
37 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
38 * memory accesses.
5fafdf24 39 *
e2542fe2 40 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
0ac4bd56 41 * otherwise little endian.
5fafdf24 42 *
0ac4bd56 43 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
5fafdf24 44 *
0ac4bd56
FB
45 * TARGET_WORDS_BIGENDIAN : same for target cpu
46 */
47
e2542fe2 48#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
f193c797
FB
49#define BSWAP_NEEDED
50#endif
51
52#ifdef BSWAP_NEEDED
53
54static inline uint16_t tswap16(uint16_t s)
55{
56 return bswap16(s);
57}
58
59static inline uint32_t tswap32(uint32_t s)
60{
61 return bswap32(s);
62}
63
64static inline uint64_t tswap64(uint64_t s)
65{
66 return bswap64(s);
67}
68
69static inline void tswap16s(uint16_t *s)
70{
71 *s = bswap16(*s);
72}
73
74static inline void tswap32s(uint32_t *s)
75{
76 *s = bswap32(*s);
77}
78
79static inline void tswap64s(uint64_t *s)
80{
81 *s = bswap64(*s);
82}
83
84#else
85
86static inline uint16_t tswap16(uint16_t s)
87{
88 return s;
89}
90
91static inline uint32_t tswap32(uint32_t s)
92{
93 return s;
94}
95
96static inline uint64_t tswap64(uint64_t s)
97{
98 return s;
99}
100
101static inline void tswap16s(uint16_t *s)
102{
103}
104
105static inline void tswap32s(uint32_t *s)
106{
107}
108
109static inline void tswap64s(uint64_t *s)
110{
111}
112
113#endif
114
115#if TARGET_LONG_SIZE == 4
116#define tswapl(s) tswap32(s)
117#define tswapls(s) tswap32s((uint32_t *)(s))
0a962c02 118#define bswaptls(s) bswap32s(s)
f193c797
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119#else
120#define tswapl(s) tswap64(s)
121#define tswapls(s) tswap64s((uint64_t *)(s))
0a962c02 122#define bswaptls(s) bswap64s(s)
f193c797
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123#endif
124
db5fd8d7
PM
125/* Target-endianness CPU memory access functions. These fit into the
126 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
83d73968 127 */
2df3b95d
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128#if defined(TARGET_WORDS_BIGENDIAN)
129#define lduw_p(p) lduw_be_p(p)
130#define ldsw_p(p) ldsw_be_p(p)
131#define ldl_p(p) ldl_be_p(p)
132#define ldq_p(p) ldq_be_p(p)
133#define ldfl_p(p) ldfl_be_p(p)
134#define ldfq_p(p) ldfq_be_p(p)
135#define stw_p(p, v) stw_be_p(p, v)
136#define stl_p(p, v) stl_be_p(p, v)
137#define stq_p(p, v) stq_be_p(p, v)
138#define stfl_p(p, v) stfl_be_p(p, v)
139#define stfq_p(p, v) stfq_be_p(p, v)
140#else
141#define lduw_p(p) lduw_le_p(p)
142#define ldsw_p(p) ldsw_le_p(p)
143#define ldl_p(p) ldl_le_p(p)
144#define ldq_p(p) ldq_le_p(p)
145#define ldfl_p(p) ldfl_le_p(p)
146#define ldfq_p(p) ldfq_le_p(p)
147#define stw_p(p, v) stw_le_p(p, v)
148#define stl_p(p, v) stl_le_p(p, v)
149#define stq_p(p, v) stq_le_p(p, v)
150#define stfl_p(p, v) stfl_le_p(p, v)
151#define stfq_p(p, v) stfq_le_p(p, v)
5a9fdfec
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152#endif
153
61382a50
FB
154/* MMU memory access macros */
155
53a5960a 156#if defined(CONFIG_USER_ONLY)
0e62fd79 157#include <assert.h>
022c62cb 158#include "exec/user/abitypes.h"
0e62fd79 159
53a5960a
PB
160/* On some host systems the guest address space is reserved on the host.
161 * This allows the guest address space to be offset to a convenient location.
162 */
379f6698
PB
163extern unsigned long guest_base;
164extern int have_guest_base;
68a1c816 165extern unsigned long reserved_va;
53a5960a 166
b76f21a7 167#define GUEST_ADDR_MAX (reserved_va ? reserved_va : \
d67f4aaa 168 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1)
53a5960a
PB
169#endif
170
5a9fdfec
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171/* page related stuff */
172
03875444 173#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
5a9fdfec
FB
174#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
175#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
176
c6d50674
SW
177/* ??? These should be the larger of uintptr_t and target_ulong. */
178extern uintptr_t qemu_real_host_page_size;
4e51361d 179extern uintptr_t qemu_real_host_page_mask;
c6d50674
SW
180extern uintptr_t qemu_host_page_size;
181extern uintptr_t qemu_host_page_mask;
5a9fdfec 182
83fb7adf 183#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
4e51361d
PC
184#define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \
185 qemu_real_host_page_mask)
5a9fdfec
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186
187/* same as PROT_xxx */
188#define PAGE_READ 0x0001
189#define PAGE_WRITE 0x0002
190#define PAGE_EXEC 0x0004
191#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
192#define PAGE_VALID 0x0008
193/* original state of the write flag (used when tracking self-modifying
194 code */
5fafdf24 195#define PAGE_WRITE_ORG 0x0010
2e9a5713
PB
196#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
197/* FIXME: Code that sets/uses this is broken and needs to go away. */
50a9569b 198#define PAGE_RESERVED 0x0020
2e9a5713 199#endif
5a9fdfec 200
b480d9b7 201#if defined(CONFIG_USER_ONLY)
5a9fdfec 202void page_dump(FILE *f);
5cd2c5b6 203
1a1c4db9
MI
204typedef int (*walk_memory_regions_fn)(void *, target_ulong,
205 target_ulong, unsigned long);
5cd2c5b6
RH
206int walk_memory_regions(void *, walk_memory_regions_fn);
207
53a5960a
PB
208int page_get_flags(target_ulong address);
209void page_set_flags(target_ulong start, target_ulong end, int flags);
3d97b40b 210int page_check_range(target_ulong start, target_ulong len, int flags);
b480d9b7 211#endif
5a9fdfec 212
9349b4f9 213CPUArchState *cpu_copy(CPUArchState *env);
c5be9f08 214
9c76219e
RH
215/* Flags for use in ENV->INTERRUPT_PENDING.
216
217 The numbers assigned here are non-sequential in order to preserve
218 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
219 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
220 the vmstate dump. */
221
222/* External hardware interrupt pending. This is typically used for
223 interrupts from devices. */
224#define CPU_INTERRUPT_HARD 0x0002
225
226/* Exit the current TB. This is typically used when some system-level device
227 makes some change to the memory mapping. E.g. the a20 line change. */
228#define CPU_INTERRUPT_EXITTB 0x0004
229
230/* Halt the CPU. */
231#define CPU_INTERRUPT_HALT 0x0020
232
233/* Debug event pending. */
234#define CPU_INTERRUPT_DEBUG 0x0080
235
4a92a558
PB
236/* Reset signal. */
237#define CPU_INTERRUPT_RESET 0x0400
238
9c76219e
RH
239/* Several target-specific external hardware interrupts. Each target/cpu.h
240 should define proper names based on these defines. */
241#define CPU_INTERRUPT_TGT_EXT_0 0x0008
242#define CPU_INTERRUPT_TGT_EXT_1 0x0010
243#define CPU_INTERRUPT_TGT_EXT_2 0x0040
244#define CPU_INTERRUPT_TGT_EXT_3 0x0200
245#define CPU_INTERRUPT_TGT_EXT_4 0x1000
246
247/* Several target-specific internal interrupts. These differ from the
07f35073 248 preceding target-specific interrupts in that they are intended to
9c76219e
RH
249 originate from within the cpu itself, typically in response to some
250 instruction being executed. These, therefore, are not masked while
251 single-stepping within the debugger. */
252#define CPU_INTERRUPT_TGT_INT_0 0x0100
4a92a558
PB
253#define CPU_INTERRUPT_TGT_INT_1 0x0800
254#define CPU_INTERRUPT_TGT_INT_2 0x2000
9c76219e 255
d362e757 256/* First unused bit: 0x4000. */
9c76219e 257
3125f763
RH
258/* The set of all bits that should be masked when single-stepping. */
259#define CPU_INTERRUPT_SSTEP_MASK \
260 (CPU_INTERRUPT_HARD \
261 | CPU_INTERRUPT_TGT_EXT_0 \
262 | CPU_INTERRUPT_TGT_EXT_1 \
263 | CPU_INTERRUPT_TGT_EXT_2 \
264 | CPU_INTERRUPT_TGT_EXT_3 \
265 | CPU_INTERRUPT_TGT_EXT_4)
98699967 266
b3755a91
PB
267#if !defined(CONFIG_USER_ONLY)
268
0f459d16
PB
269/* Flags stored in the low bits of the TLB virtual address. These are
270 defined so that fast path ram access is all zeros. */
271/* Zero if TLB entry is valid. */
272#define TLB_INVALID_MASK (1 << 3)
273/* Set if TLB entry references a clean RAM page. The iotlb entry will
274 contain the page physical address. */
275#define TLB_NOTDIRTY (1 << 4)
276/* Set if TLB entry is an IO callback. */
277#define TLB_MMIO (1 << 5)
278
055403b2 279void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
246ae24d 280void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);
b3755a91
PB
281#endif /* !CONFIG_USER_ONLY */
282
f17ec444 283int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
b3755a91
PB
284 uint8_t *buf, int len, int is_write);
285
5a9fdfec 286#endif /* CPU_ALL_H */