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Commit | Line | Data |
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5a9fdfec FB |
1 | /* |
2 | * defines common to all virtual CPUs | |
5fafdf24 | 3 | * |
5a9fdfec FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
5a9fdfec FB |
18 | */ |
19 | #ifndef CPU_ALL_H | |
20 | #define CPU_ALL_H | |
21 | ||
022c62cb | 22 | #include "exec/cpu-common.h" |
1ab4c8ce | 23 | #include "exec/memory.h" |
b2a8658e | 24 | #include "qemu/thread.h" |
2e5b09fd | 25 | #include "hw/core/cpu.h" |
43771539 | 26 | #include "qemu/rcu.h" |
0ac4bd56 | 27 | |
9e0dc48c PC |
28 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
29 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ | |
30 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ | |
31 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ | |
32 | #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ | |
fdbc2b57 | 33 | #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ |
9e0dc48c | 34 | |
5fafdf24 | 35 | /* some important defines: |
5fafdf24 | 36 | * |
e2542fe2 | 37 | * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
0ac4bd56 | 38 | * otherwise little endian. |
5fafdf24 | 39 | * |
0ac4bd56 FB |
40 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
41 | */ | |
42 | ||
e2542fe2 | 43 | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
f193c797 FB |
44 | #define BSWAP_NEEDED |
45 | #endif | |
46 | ||
47 | #ifdef BSWAP_NEEDED | |
48 | ||
49 | static inline uint16_t tswap16(uint16_t s) | |
50 | { | |
51 | return bswap16(s); | |
52 | } | |
53 | ||
54 | static inline uint32_t tswap32(uint32_t s) | |
55 | { | |
56 | return bswap32(s); | |
57 | } | |
58 | ||
59 | static inline uint64_t tswap64(uint64_t s) | |
60 | { | |
61 | return bswap64(s); | |
62 | } | |
63 | ||
64 | static inline void tswap16s(uint16_t *s) | |
65 | { | |
66 | *s = bswap16(*s); | |
67 | } | |
68 | ||
69 | static inline void tswap32s(uint32_t *s) | |
70 | { | |
71 | *s = bswap32(*s); | |
72 | } | |
73 | ||
74 | static inline void tswap64s(uint64_t *s) | |
75 | { | |
76 | *s = bswap64(*s); | |
77 | } | |
78 | ||
79 | #else | |
80 | ||
81 | static inline uint16_t tswap16(uint16_t s) | |
82 | { | |
83 | return s; | |
84 | } | |
85 | ||
86 | static inline uint32_t tswap32(uint32_t s) | |
87 | { | |
88 | return s; | |
89 | } | |
90 | ||
91 | static inline uint64_t tswap64(uint64_t s) | |
92 | { | |
93 | return s; | |
94 | } | |
95 | ||
96 | static inline void tswap16s(uint16_t *s) | |
97 | { | |
98 | } | |
99 | ||
100 | static inline void tswap32s(uint32_t *s) | |
101 | { | |
102 | } | |
103 | ||
104 | static inline void tswap64s(uint64_t *s) | |
105 | { | |
106 | } | |
107 | ||
108 | #endif | |
109 | ||
110 | #if TARGET_LONG_SIZE == 4 | |
111 | #define tswapl(s) tswap32(s) | |
112 | #define tswapls(s) tswap32s((uint32_t *)(s)) | |
0a962c02 | 113 | #define bswaptls(s) bswap32s(s) |
f193c797 FB |
114 | #else |
115 | #define tswapl(s) tswap64(s) | |
116 | #define tswapls(s) tswap64s((uint64_t *)(s)) | |
0a962c02 | 117 | #define bswaptls(s) bswap64s(s) |
f193c797 FB |
118 | #endif |
119 | ||
db5fd8d7 PM |
120 | /* Target-endianness CPU memory access functions. These fit into the |
121 | * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. | |
83d73968 | 122 | */ |
2df3b95d FB |
123 | #if defined(TARGET_WORDS_BIGENDIAN) |
124 | #define lduw_p(p) lduw_be_p(p) | |
125 | #define ldsw_p(p) ldsw_be_p(p) | |
126 | #define ldl_p(p) ldl_be_p(p) | |
127 | #define ldq_p(p) ldq_be_p(p) | |
128 | #define ldfl_p(p) ldfl_be_p(p) | |
129 | #define ldfq_p(p) ldfq_be_p(p) | |
130 | #define stw_p(p, v) stw_be_p(p, v) | |
131 | #define stl_p(p, v) stl_be_p(p, v) | |
132 | #define stq_p(p, v) stq_be_p(p, v) | |
133 | #define stfl_p(p, v) stfl_be_p(p, v) | |
134 | #define stfq_p(p, v) stfq_be_p(p, v) | |
afa4f665 PM |
135 | #define ldn_p(p, sz) ldn_be_p(p, sz) |
136 | #define stn_p(p, sz, v) stn_be_p(p, sz, v) | |
2df3b95d FB |
137 | #else |
138 | #define lduw_p(p) lduw_le_p(p) | |
139 | #define ldsw_p(p) ldsw_le_p(p) | |
140 | #define ldl_p(p) ldl_le_p(p) | |
141 | #define ldq_p(p) ldq_le_p(p) | |
142 | #define ldfl_p(p) ldfl_le_p(p) | |
143 | #define ldfq_p(p) ldfq_le_p(p) | |
144 | #define stw_p(p, v) stw_le_p(p, v) | |
145 | #define stl_p(p, v) stl_le_p(p, v) | |
146 | #define stq_p(p, v) stq_le_p(p, v) | |
147 | #define stfl_p(p, v) stfl_le_p(p, v) | |
148 | #define stfq_p(p, v) stfq_le_p(p, v) | |
afa4f665 PM |
149 | #define ldn_p(p, sz) ldn_le_p(p, sz) |
150 | #define stn_p(p, sz, v) stn_le_p(p, sz, v) | |
5a9fdfec FB |
151 | #endif |
152 | ||
61382a50 FB |
153 | /* MMU memory access macros */ |
154 | ||
53a5960a | 155 | #if defined(CONFIG_USER_ONLY) |
022c62cb | 156 | #include "exec/user/abitypes.h" |
0e62fd79 | 157 | |
53a5960a PB |
158 | /* On some host systems the guest address space is reserved on the host. |
159 | * This allows the guest address space to be offset to a convenient location. | |
160 | */ | |
379f6698 | 161 | extern unsigned long guest_base; |
e307c192 | 162 | extern bool have_guest_base; |
68a1c816 | 163 | extern unsigned long reserved_va; |
53a5960a | 164 | |
7d8cbbab RH |
165 | /* |
166 | * Limit the guest addresses as best we can. | |
167 | * | |
168 | * When not using -R reserved_va, we cannot really limit the guest | |
169 | * to less address space than the host. For 32-bit guests, this | |
170 | * acts as a sanity check that we're not giving the guest an address | |
171 | * that it cannot even represent. For 64-bit guests... the address | |
172 | * might not be what the real kernel would give, but it is at least | |
173 | * representable in the guest. | |
174 | * | |
175 | * TODO: Improve address allocation to avoid this problem, and to | |
176 | * avoid setting bits at the top of guest addresses that might need | |
177 | * to be used for tags. | |
178 | */ | |
f9919116 EB |
179 | #define GUEST_ADDR_MAX_ \ |
180 | ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ | |
181 | UINT32_MAX : ~0ul) | |
7d8cbbab RH |
182 | #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : GUEST_ADDR_MAX_) |
183 | ||
a7d6039c PB |
184 | #else |
185 | ||
186 | #include "exec/hwaddr.h" | |
4269c82b PB |
187 | |
188 | #define SUFFIX | |
189 | #define ARG1 as | |
190 | #define ARG1_DECL AddressSpace *as | |
191 | #define TARGET_ENDIANNESS | |
0979ed01 | 192 | #include "exec/memory_ldst.h.inc" |
4269c82b | 193 | |
48564041 | 194 | #define SUFFIX _cached_slow |
4269c82b PB |
195 | #define ARG1 cache |
196 | #define ARG1_DECL MemoryRegionCache *cache | |
197 | #define TARGET_ENDIANNESS | |
0979ed01 | 198 | #include "exec/memory_ldst.h.inc" |
4269c82b PB |
199 | |
200 | static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) | |
201 | { | |
202 | address_space_stl_notdirty(as, addr, val, | |
203 | MEMTXATTRS_UNSPECIFIED, NULL); | |
204 | } | |
205 | ||
206 | #define SUFFIX | |
207 | #define ARG1 as | |
208 | #define ARG1_DECL AddressSpace *as | |
209 | #define TARGET_ENDIANNESS | |
0979ed01 | 210 | #include "exec/memory_ldst_phys.h.inc" |
4269c82b | 211 | |
48564041 PB |
212 | /* Inline fast path for direct RAM access. */ |
213 | #define ENDIANNESS | |
0979ed01 | 214 | #include "exec/memory_ldst_cached.h.inc" |
48564041 | 215 | |
4269c82b PB |
216 | #define SUFFIX _cached |
217 | #define ARG1 cache | |
218 | #define ARG1_DECL MemoryRegionCache *cache | |
219 | #define TARGET_ENDIANNESS | |
0979ed01 | 220 | #include "exec/memory_ldst_phys.h.inc" |
53a5960a PB |
221 | #endif |
222 | ||
5a9fdfec FB |
223 | /* page related stuff */ |
224 | ||
20bccb82 | 225 | #ifdef TARGET_PAGE_BITS_VARY |
bbc17caf RH |
226 | typedef struct { |
227 | bool decided; | |
228 | int bits; | |
bb8e3ea6 | 229 | target_long mask; |
bbc17caf RH |
230 | } TargetPageBits; |
231 | #if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY) | |
232 | extern const TargetPageBits target_page; | |
233 | #else | |
234 | extern TargetPageBits target_page; | |
235 | #endif | |
639044b5 | 236 | #ifdef CONFIG_DEBUG_TCG |
bbc17caf | 237 | #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) |
bb8e3ea6 | 238 | #define TARGET_PAGE_MASK ({ assert(target_page.decided); target_page.mask; }) |
20bccb82 | 239 | #else |
639044b5 | 240 | #define TARGET_PAGE_BITS target_page.bits |
bb8e3ea6 | 241 | #define TARGET_PAGE_MASK target_page.mask |
639044b5 | 242 | #endif |
bb8e3ea6 | 243 | #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) |
639044b5 | 244 | #else |
20bccb82 | 245 | #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS |
bb8e3ea6 RH |
246 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
247 | #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) | |
20bccb82 PM |
248 | #endif |
249 | ||
50276a79 | 250 | #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) |
5a9fdfec | 251 | |
0c2d70c4 PB |
252 | /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even |
253 | * when intptr_t is 32-bit and we are aligning a long long. | |
254 | */ | |
c6d50674 | 255 | extern uintptr_t qemu_host_page_size; |
0c2d70c4 | 256 | extern intptr_t qemu_host_page_mask; |
5a9fdfec | 257 | |
50276a79 WY |
258 | #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) |
259 | #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size) | |
5a9fdfec FB |
260 | |
261 | /* same as PROT_xxx */ | |
262 | #define PAGE_READ 0x0001 | |
263 | #define PAGE_WRITE 0x0002 | |
264 | #define PAGE_EXEC 0x0004 | |
265 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) | |
266 | #define PAGE_VALID 0x0008 | |
267 | /* original state of the write flag (used when tracking self-modifying | |
268 | code */ | |
5fafdf24 | 269 | #define PAGE_WRITE_ORG 0x0010 |
f52bfb12 DH |
270 | /* Invalidate the TLB entry immediately, helpful for s390x |
271 | * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ | |
272 | #define PAGE_WRITE_INV 0x0040 | |
2e9a5713 PB |
273 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
274 | /* FIXME: Code that sets/uses this is broken and needs to go away. */ | |
50a9569b | 275 | #define PAGE_RESERVED 0x0020 |
2e9a5713 | 276 | #endif |
be5d6f48 RH |
277 | /* Target-specific bits that will be used via page_get_flags(). */ |
278 | #define PAGE_TARGET_1 0x0080 | |
5a9fdfec | 279 | |
b480d9b7 | 280 | #if defined(CONFIG_USER_ONLY) |
5a9fdfec | 281 | void page_dump(FILE *f); |
5cd2c5b6 | 282 | |
1a1c4db9 MI |
283 | typedef int (*walk_memory_regions_fn)(void *, target_ulong, |
284 | target_ulong, unsigned long); | |
5cd2c5b6 RH |
285 | int walk_memory_regions(void *, walk_memory_regions_fn); |
286 | ||
53a5960a PB |
287 | int page_get_flags(target_ulong address); |
288 | void page_set_flags(target_ulong start, target_ulong end, int flags); | |
3d97b40b | 289 | int page_check_range(target_ulong start, target_ulong len, int flags); |
b480d9b7 | 290 | #endif |
5a9fdfec | 291 | |
9349b4f9 | 292 | CPUArchState *cpu_copy(CPUArchState *env); |
c5be9f08 | 293 | |
9c76219e RH |
294 | /* Flags for use in ENV->INTERRUPT_PENDING. |
295 | ||
296 | The numbers assigned here are non-sequential in order to preserve | |
297 | binary compatibility with the vmstate dump. Bit 0 (0x0001) was | |
298 | previously used for CPU_INTERRUPT_EXIT, and is cleared when loading | |
299 | the vmstate dump. */ | |
300 | ||
301 | /* External hardware interrupt pending. This is typically used for | |
302 | interrupts from devices. */ | |
303 | #define CPU_INTERRUPT_HARD 0x0002 | |
304 | ||
305 | /* Exit the current TB. This is typically used when some system-level device | |
306 | makes some change to the memory mapping. E.g. the a20 line change. */ | |
307 | #define CPU_INTERRUPT_EXITTB 0x0004 | |
308 | ||
309 | /* Halt the CPU. */ | |
310 | #define CPU_INTERRUPT_HALT 0x0020 | |
311 | ||
312 | /* Debug event pending. */ | |
313 | #define CPU_INTERRUPT_DEBUG 0x0080 | |
314 | ||
4a92a558 PB |
315 | /* Reset signal. */ |
316 | #define CPU_INTERRUPT_RESET 0x0400 | |
317 | ||
9c76219e RH |
318 | /* Several target-specific external hardware interrupts. Each target/cpu.h |
319 | should define proper names based on these defines. */ | |
320 | #define CPU_INTERRUPT_TGT_EXT_0 0x0008 | |
321 | #define CPU_INTERRUPT_TGT_EXT_1 0x0010 | |
322 | #define CPU_INTERRUPT_TGT_EXT_2 0x0040 | |
323 | #define CPU_INTERRUPT_TGT_EXT_3 0x0200 | |
324 | #define CPU_INTERRUPT_TGT_EXT_4 0x1000 | |
325 | ||
326 | /* Several target-specific internal interrupts. These differ from the | |
07f35073 | 327 | preceding target-specific interrupts in that they are intended to |
9c76219e RH |
328 | originate from within the cpu itself, typically in response to some |
329 | instruction being executed. These, therefore, are not masked while | |
330 | single-stepping within the debugger. */ | |
331 | #define CPU_INTERRUPT_TGT_INT_0 0x0100 | |
4a92a558 PB |
332 | #define CPU_INTERRUPT_TGT_INT_1 0x0800 |
333 | #define CPU_INTERRUPT_TGT_INT_2 0x2000 | |
9c76219e | 334 | |
d362e757 | 335 | /* First unused bit: 0x4000. */ |
9c76219e | 336 | |
3125f763 RH |
337 | /* The set of all bits that should be masked when single-stepping. */ |
338 | #define CPU_INTERRUPT_SSTEP_MASK \ | |
339 | (CPU_INTERRUPT_HARD \ | |
340 | | CPU_INTERRUPT_TGT_EXT_0 \ | |
341 | | CPU_INTERRUPT_TGT_EXT_1 \ | |
342 | | CPU_INTERRUPT_TGT_EXT_2 \ | |
343 | | CPU_INTERRUPT_TGT_EXT_3 \ | |
344 | | CPU_INTERRUPT_TGT_EXT_4) | |
98699967 | 345 | |
069cfe77 RH |
346 | #ifdef CONFIG_USER_ONLY |
347 | ||
348 | /* | |
349 | * Allow some level of source compatibility with softmmu. We do not | |
350 | * support any of the more exotic features, so only invalid pages may | |
351 | * be signaled by probe_access_flags(). | |
352 | */ | |
353 | #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) | |
354 | #define TLB_MMIO 0 | |
355 | #define TLB_WATCHPOINT 0 | |
356 | ||
357 | #else | |
b3755a91 | 358 | |
1f6f2b34 RH |
359 | /* |
360 | * Flags stored in the low bits of the TLB virtual address. | |
361 | * These are defined so that fast path ram access is all zeros. | |
1f00b27f SS |
362 | * The flags all must be between TARGET_PAGE_BITS and |
363 | * maximum address alignment bit. | |
1f6f2b34 RH |
364 | * |
365 | * Use TARGET_PAGE_BITS_MIN so that these bits are constant | |
366 | * when TARGET_PAGE_BITS_VARY is in effect. | |
1f00b27f | 367 | */ |
0f459d16 | 368 | /* Zero if TLB entry is valid. */ |
1f6f2b34 | 369 | #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) |
0f459d16 PB |
370 | /* Set if TLB entry references a clean RAM page. The iotlb entry will |
371 | contain the page physical address. */ | |
1f6f2b34 | 372 | #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) |
0f459d16 | 373 | /* Set if TLB entry is an IO callback. */ |
1f6f2b34 | 374 | #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) |
50b107c5 | 375 | /* Set if TLB entry contains a watchpoint. */ |
1f6f2b34 | 376 | #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) |
5b87b3e6 RH |
377 | /* Set if TLB entry requires byte swap. */ |
378 | #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) | |
7b0d792c RH |
379 | /* Set if TLB entry writes ignored. */ |
380 | #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) | |
1f00b27f SS |
381 | |
382 | /* Use this mask to check interception with an alignment mask | |
383 | * in a TCG backend. | |
384 | */ | |
50b107c5 | 385 | #define TLB_FLAGS_MASK \ |
7b0d792c RH |
386 | (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ |
387 | | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) | |
0f459d16 | 388 | |
334692bc PM |
389 | /** |
390 | * tlb_hit_page: return true if page aligned @addr is a hit against the | |
391 | * TLB entry @tlb_addr | |
392 | * | |
393 | * @addr: virtual address to test (must be page aligned) | |
394 | * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) | |
395 | */ | |
396 | static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) | |
397 | { | |
398 | return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); | |
399 | } | |
400 | ||
401 | /** | |
402 | * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr | |
403 | * | |
404 | * @addr: virtual address to test (need not be page aligned) | |
405 | * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) | |
406 | */ | |
407 | static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) | |
408 | { | |
409 | return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); | |
410 | } | |
411 | ||
740b1759 CF |
412 | #ifdef CONFIG_TCG |
413 | void dump_drift_info(void); | |
3de2faa9 | 414 | void dump_exec_info(void); |
d4c51a0a | 415 | void dump_opcount_info(void); |
740b1759 CF |
416 | #endif /* CONFIG_TCG */ |
417 | ||
b3755a91 PB |
418 | #endif /* !CONFIG_USER_ONLY */ |
419 | ||
ddfc8b96 | 420 | /* Returns: 0 on success, -1 on error */ |
f17ec444 | 421 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
28c80bfe | 422 | void *ptr, target_ulong len, bool is_write); |
b3755a91 | 423 | |
8642c1b8 PC |
424 | int cpu_exec(CPUState *cpu); |
425 | ||
7506ed90 RH |
426 | /** |
427 | * cpu_set_cpustate_pointers(cpu) | |
428 | * @cpu: The cpu object | |
429 | * | |
430 | * Set the generic pointers in CPUState into the outer object. | |
431 | */ | |
432 | static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) | |
433 | { | |
434 | cpu->parent_obj.env_ptr = &cpu->env; | |
5e140196 | 435 | cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; |
7506ed90 RH |
436 | } |
437 | ||
083dc73d RH |
438 | /** |
439 | * env_archcpu(env) | |
440 | * @env: The architecture environment | |
441 | * | |
442 | * Return the ArchCPU associated with the environment. | |
443 | */ | |
444 | static inline ArchCPU *env_archcpu(CPUArchState *env) | |
445 | { | |
446 | return container_of(env, ArchCPU, env); | |
447 | } | |
448 | ||
29a0af61 RH |
449 | /** |
450 | * env_cpu(env) | |
451 | * @env: The architecture environment | |
452 | * | |
453 | * Return the CPUState associated with the environment. | |
454 | */ | |
455 | static inline CPUState *env_cpu(CPUArchState *env) | |
456 | { | |
083dc73d | 457 | return &env_archcpu(env)->parent_obj; |
29a0af61 RH |
458 | } |
459 | ||
5b146dc7 RH |
460 | /** |
461 | * env_neg(env) | |
462 | * @env: The architecture environment | |
463 | * | |
464 | * Return the CPUNegativeOffsetState associated with the environment. | |
465 | */ | |
466 | static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) | |
467 | { | |
468 | ArchCPU *arch_cpu = container_of(env, ArchCPU, env); | |
469 | return &arch_cpu->neg; | |
470 | } | |
471 | ||
472 | /** | |
473 | * cpu_neg(cpu) | |
474 | * @cpu: The generic CPUState | |
475 | * | |
476 | * Return the CPUNegativeOffsetState associated with the cpu. | |
477 | */ | |
478 | static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) | |
479 | { | |
480 | ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); | |
481 | return &arch_cpu->neg; | |
482 | } | |
483 | ||
269bd5d8 RH |
484 | /** |
485 | * env_tlb(env) | |
486 | * @env: The architecture environment | |
487 | * | |
488 | * Return the CPUTLB state associated with the environment. | |
489 | */ | |
490 | static inline CPUTLB *env_tlb(CPUArchState *env) | |
491 | { | |
492 | return &env_neg(env)->tlb; | |
493 | } | |
494 | ||
5a9fdfec | 495 | #endif /* CPU_ALL_H */ |