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Move page_size_init earlier
[mirror_qemu.git] / include / exec / cpu-common.h
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1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H 1
3
07f35073 4/* CPU interfaces that are target independent. */
1ad2134f 5
ce927ed9 6#ifndef CONFIG_USER_ONLY
022c62cb 7#include "exec/hwaddr.h"
ce927ed9 8#endif
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9
10#ifndef NEED_CPU_H
022c62cb 11#include "exec/poison.h"
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12#endif
13
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14#include "qemu/bswap.h"
15#include "qemu/queue.h"
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16#include "qemu/fprintf-fn.h"
17#include "qemu/typedefs.h"
1ad2134f 18
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19/**
20 * CPUListState:
21 * @cpu_fprintf: Print function.
22 * @file: File to print to using @cpu_fprint.
23 *
24 * State commonly used for iterating over CPU models.
25 */
26typedef struct CPUListState {
27 fprintf_function cpu_fprintf;
28 FILE *file;
29} CPUListState;
30
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31typedef enum MMUAccessType {
32 MMU_DATA_LOAD = 0,
33 MMU_DATA_STORE = 1,
34 MMU_INST_FETCH = 2
35} MMUAccessType;
36
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37#if !defined(CONFIG_USER_ONLY)
38
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39enum device_endian {
40 DEVICE_NATIVE_ENDIAN,
41 DEVICE_BIG_ENDIAN,
42 DEVICE_LITTLE_ENDIAN,
43};
44
1ad2134f 45/* address in the RAM (different from a physical address) */
4be403c8 46#if defined(CONFIG_XEN_BACKEND)
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47typedef uint64_t ram_addr_t;
48# define RAM_ADDR_MAX UINT64_MAX
49# define RAM_ADDR_FMT "%" PRIx64
50#else
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51typedef uintptr_t ram_addr_t;
52# define RAM_ADDR_MAX UINTPTR_MAX
53# define RAM_ADDR_FMT "%" PRIxPTR
f15fbc4b 54#endif
1ad2134f 55
96d0e26c 56extern ram_addr_t ram_size;
87a45cfe 57ram_addr_t get_current_ram_size(void);
96d0e26c 58
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59/* memory API */
60
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61typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
62typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
1ad2134f 63
cd19cfa2 64void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
1ad2134f 65/* This should not be used by devices. */
1b5ec234 66MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
c5705a77 67void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
20cfe881 68void qemu_ram_unset_idstr(ram_addr_t addr);
1ad2134f 69
a8170e5e 70void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
1ad2134f 71 int len, int is_write);
a8170e5e 72static inline void cpu_physical_memory_read(hwaddr addr,
3bad9814 73 void *buf, int len)
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74{
75 cpu_physical_memory_rw(addr, buf, len, 0);
76}
a8170e5e 77static inline void cpu_physical_memory_write(hwaddr addr,
3bad9814 78 const void *buf, int len)
1ad2134f 79{
3bad9814 80 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
1ad2134f 81}
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82void *cpu_physical_memory_map(hwaddr addr,
83 hwaddr *plen,
1ad2134f 84 int is_write);
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85void cpu_physical_memory_unmap(void *buffer, hwaddr len,
86 int is_write, hwaddr access_len);
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87void cpu_register_map_client(QEMUBH *bh);
88void cpu_unregister_map_client(QEMUBH *bh);
1ad2134f 89
a8170e5e 90bool cpu_physical_memory_is_io(hwaddr phys_addr);
76f35538 91
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92/* Coalesced MMIO regions are areas where write operations can be reordered.
93 * This usually implies that write operations are side-effect free. This allows
94 * batching which can make a major impact on performance when using
95 * virtualization.
96 */
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97void qemu_flush_coalesced_mmio_buffer(void);
98
2c17449b 99uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
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100uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
101uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
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102uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
103uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
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104uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
105uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
db3be60d 106void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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107void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
108void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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109void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
110void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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111void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
112void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
c227f099 113
21673cde 114#ifdef NEED_CPU_H
41701aa4 115uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
fdfba1a2 116uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
2c17449b 117uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
2198a121 118void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
5ce5944d 119void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
ab1da857 120void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
f606604f 121void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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122#endif
123
2a221651 124void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
1ad2134f 125 const uint8_t *buf, int len);
582b55a9 126void cpu_flush_icache_range(hwaddr start, int len);
1ad2134f 127
0e0df1e2 128extern struct MemoryRegion io_mem_rom;
0e0df1e2 129extern struct MemoryRegion io_mem_notdirty;
1ad2134f 130
e3807054 131typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
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132 ram_addr_t offset, ram_addr_t length, void *opaque);
133
e3807054 134int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
bd2fa51f 135
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136#endif
137
1ad2134f 138#endif /* !CPU_COMMON_H */