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Commit | Line | Data |
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1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
07f35073 | 4 | /* CPU interfaces that are target independent. */ |
1ad2134f | 5 | |
022c62cb | 6 | #include "exec/hwaddr.h" |
37b76cfd PB |
7 | |
8 | #ifndef NEED_CPU_H | |
022c62cb | 9 | #include "exec/poison.h" |
37b76cfd PB |
10 | #endif |
11 | ||
1de7afc9 PB |
12 | #include "qemu/bswap.h" |
13 | #include "qemu/queue.h" | |
1ad2134f | 14 | |
92a31361 AF |
15 | /** |
16 | * CPUListState: | |
17 | * @cpu_fprintf: Print function. | |
18 | * @file: File to print to using @cpu_fprint. | |
19 | * | |
20 | * State commonly used for iterating over CPU models. | |
21 | */ | |
22 | typedef struct CPUListState { | |
23 | fprintf_function cpu_fprintf; | |
24 | FILE *file; | |
25 | } CPUListState; | |
26 | ||
b3755a91 PB |
27 | #if !defined(CONFIG_USER_ONLY) |
28 | ||
dd310534 AG |
29 | enum device_endian { |
30 | DEVICE_NATIVE_ENDIAN, | |
31 | DEVICE_BIG_ENDIAN, | |
32 | DEVICE_LITTLE_ENDIAN, | |
33 | }; | |
34 | ||
1ad2134f | 35 | /* address in the RAM (different from a physical address) */ |
4be403c8 | 36 | #if defined(CONFIG_XEN_BACKEND) |
f15fbc4b AP |
37 | typedef uint64_t ram_addr_t; |
38 | # define RAM_ADDR_MAX UINT64_MAX | |
39 | # define RAM_ADDR_FMT "%" PRIx64 | |
40 | #else | |
53576999 SW |
41 | typedef uintptr_t ram_addr_t; |
42 | # define RAM_ADDR_MAX UINTPTR_MAX | |
43 | # define RAM_ADDR_FMT "%" PRIxPTR | |
f15fbc4b | 44 | #endif |
1ad2134f PB |
45 | |
46 | /* memory API */ | |
47 | ||
a8170e5e AK |
48 | typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); |
49 | typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); | |
1ad2134f | 50 | |
cd19cfa2 | 51 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); |
1ad2134f | 52 | /* This should not be used by devices. */ |
e890261f MT |
53 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); |
54 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); | |
c5705a77 | 55 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev); |
1ad2134f | 56 | |
a8170e5e | 57 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
1ad2134f | 58 | int len, int is_write); |
a8170e5e | 59 | static inline void cpu_physical_memory_read(hwaddr addr, |
3bad9814 | 60 | void *buf, int len) |
1ad2134f PB |
61 | { |
62 | cpu_physical_memory_rw(addr, buf, len, 0); | |
63 | } | |
a8170e5e | 64 | static inline void cpu_physical_memory_write(hwaddr addr, |
3bad9814 | 65 | const void *buf, int len) |
1ad2134f | 66 | { |
3bad9814 | 67 | cpu_physical_memory_rw(addr, (void *)buf, len, 1); |
1ad2134f | 68 | } |
a8170e5e AK |
69 | void *cpu_physical_memory_map(hwaddr addr, |
70 | hwaddr *plen, | |
1ad2134f | 71 | int is_write); |
a8170e5e AK |
72 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
73 | int is_write, hwaddr access_len); | |
1ad2134f | 74 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); |
1ad2134f | 75 | |
a8170e5e | 76 | bool cpu_physical_memory_is_io(hwaddr phys_addr); |
76f35538 | 77 | |
6842a08e BS |
78 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
79 | * This usually implies that write operations are side-effect free. This allows | |
80 | * batching which can make a major impact on performance when using | |
81 | * virtualization. | |
82 | */ | |
6842a08e BS |
83 | void qemu_flush_coalesced_mmio_buffer(void); |
84 | ||
a8170e5e AK |
85 | uint32_t ldub_phys(hwaddr addr); |
86 | uint32_t lduw_le_phys(hwaddr addr); | |
87 | uint32_t lduw_be_phys(hwaddr addr); | |
88 | uint32_t ldl_le_phys(hwaddr addr); | |
89 | uint32_t ldl_be_phys(hwaddr addr); | |
90 | uint64_t ldq_le_phys(hwaddr addr); | |
91 | uint64_t ldq_be_phys(hwaddr addr); | |
92 | void stb_phys(hwaddr addr, uint32_t val); | |
93 | void stw_le_phys(hwaddr addr, uint32_t val); | |
94 | void stw_be_phys(hwaddr addr, uint32_t val); | |
95 | void stl_le_phys(hwaddr addr, uint32_t val); | |
96 | void stl_be_phys(hwaddr addr, uint32_t val); | |
97 | void stq_le_phys(hwaddr addr, uint64_t val); | |
98 | void stq_be_phys(hwaddr addr, uint64_t val); | |
c227f099 | 99 | |
21673cde | 100 | #ifdef NEED_CPU_H |
a8170e5e AK |
101 | uint32_t lduw_phys(hwaddr addr); |
102 | uint32_t ldl_phys(hwaddr addr); | |
103 | uint64_t ldq_phys(hwaddr addr); | |
104 | void stl_phys_notdirty(hwaddr addr, uint32_t val); | |
a8170e5e AK |
105 | void stw_phys(hwaddr addr, uint32_t val); |
106 | void stl_phys(hwaddr addr, uint32_t val); | |
107 | void stq_phys(hwaddr addr, uint64_t val); | |
21673cde BS |
108 | #endif |
109 | ||
a8170e5e | 110 | void cpu_physical_memory_write_rom(hwaddr addr, |
1ad2134f PB |
111 | const uint8_t *buf, int len); |
112 | ||
0e0df1e2 AK |
113 | extern struct MemoryRegion io_mem_ram; |
114 | extern struct MemoryRegion io_mem_rom; | |
115 | extern struct MemoryRegion io_mem_unassigned; | |
116 | extern struct MemoryRegion io_mem_notdirty; | |
1ad2134f | 117 | |
b3755a91 PB |
118 | #endif |
119 | ||
1ad2134f | 120 | #endif /* !CPU_COMMON_H */ |