]> git.proxmox.com Git - mirror_qemu.git/blame - include/exec/cpu-common.h
Merge remote-tracking branch 'remotes/hdeller/tags/hppa-updates-pull-request' into...
[mirror_qemu.git] / include / exec / cpu-common.h
CommitLineData
1ad2134f 1#ifndef CPU_COMMON_H
175de524 2#define CPU_COMMON_H
1ad2134f 3
07f35073 4/* CPU interfaces that are target independent. */
1ad2134f 5
ce927ed9 6#ifndef CONFIG_USER_ONLY
022c62cb 7#include "exec/hwaddr.h"
ce927ed9 8#endif
37b76cfd 9
b269a708
PMD
10/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
11 * when intptr_t is 32-bit and we are aligning a long long.
12 */
13extern uintptr_t qemu_host_page_size;
14extern intptr_t qemu_host_page_mask;
15
16#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
17#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size)
18
0ac20318 19/* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
267f685b
PB
20void qemu_init_cpu_list(void);
21void cpu_list_lock(void);
22void cpu_list_unlock(void);
23
2cd53943
TH
24void tcg_flush_softmmu_tlb(CPUState *cs);
25
d9f24bf5
PB
26void tcg_iommu_init_notifier_list(CPUState *cpu);
27void tcg_iommu_free_notifier_list(CPUState *cpu);
28
b3755a91
PB
29#if !defined(CONFIG_USER_ONLY)
30
dd310534
AG
31enum device_endian {
32 DEVICE_NATIVE_ENDIAN,
33 DEVICE_BIG_ENDIAN,
34 DEVICE_LITTLE_ENDIAN,
35};
36
c99a29e7
YX
37#if defined(HOST_WORDS_BIGENDIAN)
38#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
39#else
40#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
41#endif
42
1ad2134f 43/* address in the RAM (different from a physical address) */
4be403c8 44#if defined(CONFIG_XEN_BACKEND)
f15fbc4b
AP
45typedef uint64_t ram_addr_t;
46# define RAM_ADDR_MAX UINT64_MAX
47# define RAM_ADDR_FMT "%" PRIx64
48#else
53576999
SW
49typedef uintptr_t ram_addr_t;
50# define RAM_ADDR_MAX UINTPTR_MAX
51# define RAM_ADDR_FMT "%" PRIxPTR
f15fbc4b 52#endif
1ad2134f
PB
53
54/* memory API */
55
cd19cfa2 56void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
1ad2134f 57/* This should not be used by devices. */
07bdaa41 58ram_addr_t qemu_ram_addr_from_host(void *ptr);
e3dd7493 59RAMBlock *qemu_ram_block_by_name(const char *name);
422148d3 60RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
f615f396 61 ram_addr_t *offset);
f90bb71b 62ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
fa53a0e5
GA
63void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
64void qemu_ram_unset_idstr(RAMBlock *block);
422148d3 65const char *qemu_ram_get_idstr(RAMBlock *rb);
754cb9c0
YK
66void *qemu_ram_get_host_addr(RAMBlock *rb);
67ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
68ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
082851a3 69ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
463a4ac2 70bool qemu_ram_is_shared(RAMBlock *rb);
8dbe22c6 71bool qemu_ram_is_noreserve(RAMBlock *rb);
2ce16640
DDAG
72bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
73void qemu_ram_set_uf_zeroable(RAMBlock *rb);
b895de50
CLG
74bool qemu_ram_is_migratable(RAMBlock *rb);
75void qemu_ram_set_migratable(RAMBlock *rb);
76void qemu_ram_unset_migratable(RAMBlock *rb);
2ce16640 77
863e9621 78size_t qemu_ram_pagesize(RAMBlock *block);
67f11b5c 79size_t qemu_ram_pagesize_largest(void);
1ad2134f 80
d7ef71ef 81void cpu_physical_memory_rw(hwaddr addr, void *buf,
28c80bfe 82 hwaddr len, bool is_write);
a8170e5e 83static inline void cpu_physical_memory_read(hwaddr addr,
0c249ff7 84 void *buf, hwaddr len)
1ad2134f 85{
85eb7c18 86 cpu_physical_memory_rw(addr, buf, len, false);
1ad2134f 87}
a8170e5e 88static inline void cpu_physical_memory_write(hwaddr addr,
0c249ff7 89 const void *buf, hwaddr len)
1ad2134f 90{
85eb7c18 91 cpu_physical_memory_rw(addr, (void *)buf, len, true);
1ad2134f 92}
a8170e5e
AK
93void *cpu_physical_memory_map(hwaddr addr,
94 hwaddr *plen,
28c80bfe 95 bool is_write);
a8170e5e 96void cpu_physical_memory_unmap(void *buffer, hwaddr len,
28c80bfe 97 bool is_write, hwaddr access_len);
e95205e1
FZ
98void cpu_register_map_client(QEMUBH *bh);
99void cpu_unregister_map_client(QEMUBH *bh);
1ad2134f 100
a8170e5e 101bool cpu_physical_memory_is_io(hwaddr phys_addr);
76f35538 102
6842a08e
BS
103/* Coalesced MMIO regions are areas where write operations can be reordered.
104 * This usually implies that write operations are side-effect free. This allows
105 * batching which can make a major impact on performance when using
106 * virtualization.
107 */
6842a08e
BS
108void qemu_flush_coalesced_mmio_buffer(void);
109
0c249ff7 110void cpu_flush_icache_range(hwaddr start, hwaddr len);
1ad2134f 111
754cb9c0 112typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
bd2fa51f 113
e3807054 114int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
d3a5038c 115int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
bd2fa51f 116
b3755a91
PB
117#endif
118
c5e3c918
PB
119/* vl.c */
120extern int singlestep;
121
175de524 122#endif /* CPU_COMMON_H */