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Commit | Line | Data |
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1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
07f35073 | 4 | /* CPU interfaces that are target independent. */ |
1ad2134f | 5 | |
ce927ed9 | 6 | #ifndef CONFIG_USER_ONLY |
022c62cb | 7 | #include "exec/hwaddr.h" |
ce927ed9 | 8 | #endif |
37b76cfd | 9 | |
1de7afc9 PB |
10 | #include "qemu/bswap.h" |
11 | #include "qemu/queue.h" | |
fba0a593 | 12 | #include "qemu/fprintf-fn.h" |
1ad2134f | 13 | |
92a31361 AF |
14 | /** |
15 | * CPUListState: | |
16 | * @cpu_fprintf: Print function. | |
17 | * @file: File to print to using @cpu_fprint. | |
18 | * | |
19 | * State commonly used for iterating over CPU models. | |
20 | */ | |
21 | typedef struct CPUListState { | |
22 | fprintf_function cpu_fprintf; | |
23 | FILE *file; | |
24 | } CPUListState; | |
25 | ||
b3755a91 PB |
26 | #if !defined(CONFIG_USER_ONLY) |
27 | ||
dd310534 AG |
28 | enum device_endian { |
29 | DEVICE_NATIVE_ENDIAN, | |
30 | DEVICE_BIG_ENDIAN, | |
31 | DEVICE_LITTLE_ENDIAN, | |
32 | }; | |
33 | ||
1ad2134f | 34 | /* address in the RAM (different from a physical address) */ |
4be403c8 | 35 | #if defined(CONFIG_XEN_BACKEND) |
f15fbc4b AP |
36 | typedef uint64_t ram_addr_t; |
37 | # define RAM_ADDR_MAX UINT64_MAX | |
38 | # define RAM_ADDR_FMT "%" PRIx64 | |
39 | #else | |
53576999 SW |
40 | typedef uintptr_t ram_addr_t; |
41 | # define RAM_ADDR_MAX UINTPTR_MAX | |
42 | # define RAM_ADDR_FMT "%" PRIxPTR | |
f15fbc4b | 43 | #endif |
1ad2134f | 44 | |
96d0e26c WG |
45 | extern ram_addr_t ram_size; |
46 | ||
1ad2134f PB |
47 | /* memory API */ |
48 | ||
a8170e5e AK |
49 | typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); |
50 | typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); | |
1ad2134f | 51 | |
cd19cfa2 | 52 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); |
1ad2134f | 53 | /* This should not be used by devices. */ |
07bdaa41 | 54 | ram_addr_t qemu_ram_addr_from_host(void *ptr); |
e3dd7493 | 55 | RAMBlock *qemu_ram_block_by_name(const char *name); |
422148d3 | 56 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
f615f396 | 57 | ram_addr_t *offset); |
fa53a0e5 GA |
58 | void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); |
59 | void qemu_ram_unset_idstr(RAMBlock *block); | |
422148d3 | 60 | const char *qemu_ram_get_idstr(RAMBlock *rb); |
1ad2134f | 61 | |
a8170e5e | 62 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
1ad2134f | 63 | int len, int is_write); |
a8170e5e | 64 | static inline void cpu_physical_memory_read(hwaddr addr, |
3bad9814 | 65 | void *buf, int len) |
1ad2134f PB |
66 | { |
67 | cpu_physical_memory_rw(addr, buf, len, 0); | |
68 | } | |
a8170e5e | 69 | static inline void cpu_physical_memory_write(hwaddr addr, |
3bad9814 | 70 | const void *buf, int len) |
1ad2134f | 71 | { |
3bad9814 | 72 | cpu_physical_memory_rw(addr, (void *)buf, len, 1); |
1ad2134f | 73 | } |
a8170e5e AK |
74 | void *cpu_physical_memory_map(hwaddr addr, |
75 | hwaddr *plen, | |
1ad2134f | 76 | int is_write); |
a8170e5e AK |
77 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
78 | int is_write, hwaddr access_len); | |
e95205e1 FZ |
79 | void cpu_register_map_client(QEMUBH *bh); |
80 | void cpu_unregister_map_client(QEMUBH *bh); | |
1ad2134f | 81 | |
a8170e5e | 82 | bool cpu_physical_memory_is_io(hwaddr phys_addr); |
76f35538 | 83 | |
6842a08e BS |
84 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
85 | * This usually implies that write operations are side-effect free. This allows | |
86 | * batching which can make a major impact on performance when using | |
87 | * virtualization. | |
88 | */ | |
6842a08e BS |
89 | void qemu_flush_coalesced_mmio_buffer(void); |
90 | ||
2c17449b | 91 | uint32_t ldub_phys(AddressSpace *as, hwaddr addr); |
41701aa4 EI |
92 | uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr); |
93 | uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr); | |
fdfba1a2 EI |
94 | uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr); |
95 | uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr); | |
2c17449b EI |
96 | uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr); |
97 | uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr); | |
db3be60d | 98 | void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
5ce5944d EI |
99 | void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
100 | void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
ab1da857 EI |
101 | void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
102 | void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
f606604f EI |
103 | void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val); |
104 | void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val); | |
c227f099 | 105 | |
2a221651 | 106 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
1ad2134f | 107 | const uint8_t *buf, int len); |
582b55a9 | 108 | void cpu_flush_icache_range(hwaddr start, int len); |
1ad2134f | 109 | |
0e0df1e2 | 110 | extern struct MemoryRegion io_mem_rom; |
0e0df1e2 | 111 | extern struct MemoryRegion io_mem_notdirty; |
1ad2134f | 112 | |
e3807054 | 113 | typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr, |
bd2fa51f MH |
114 | ram_addr_t offset, ram_addr_t length, void *opaque); |
115 | ||
e3807054 | 116 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); |
bd2fa51f | 117 | |
b3755a91 PB |
118 | #endif |
119 | ||
1ad2134f | 120 | #endif /* !CPU_COMMON_H */ |