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Commit | Line | Data |
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1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
07f35073 | 4 | /* CPU interfaces that are target independent. */ |
1ad2134f | 5 | |
ce927ed9 | 6 | #ifndef CONFIG_USER_ONLY |
022c62cb | 7 | #include "exec/hwaddr.h" |
ce927ed9 | 8 | #endif |
37b76cfd | 9 | |
1de7afc9 PB |
10 | #include "qemu/bswap.h" |
11 | #include "qemu/queue.h" | |
fba0a593 | 12 | #include "qemu/fprintf-fn.h" |
1ad2134f | 13 | |
92a31361 AF |
14 | /** |
15 | * CPUListState: | |
16 | * @cpu_fprintf: Print function. | |
17 | * @file: File to print to using @cpu_fprint. | |
18 | * | |
19 | * State commonly used for iterating over CPU models. | |
20 | */ | |
21 | typedef struct CPUListState { | |
22 | fprintf_function cpu_fprintf; | |
23 | FILE *file; | |
24 | } CPUListState; | |
25 | ||
55e94093 LA |
26 | typedef enum MMUAccessType { |
27 | MMU_DATA_LOAD = 0, | |
28 | MMU_DATA_STORE = 1, | |
29 | MMU_INST_FETCH = 2 | |
30 | } MMUAccessType; | |
31 | ||
b3755a91 PB |
32 | #if !defined(CONFIG_USER_ONLY) |
33 | ||
dd310534 AG |
34 | enum device_endian { |
35 | DEVICE_NATIVE_ENDIAN, | |
36 | DEVICE_BIG_ENDIAN, | |
37 | DEVICE_LITTLE_ENDIAN, | |
38 | }; | |
39 | ||
1ad2134f | 40 | /* address in the RAM (different from a physical address) */ |
4be403c8 | 41 | #if defined(CONFIG_XEN_BACKEND) |
f15fbc4b AP |
42 | typedef uint64_t ram_addr_t; |
43 | # define RAM_ADDR_MAX UINT64_MAX | |
44 | # define RAM_ADDR_FMT "%" PRIx64 | |
45 | #else | |
53576999 SW |
46 | typedef uintptr_t ram_addr_t; |
47 | # define RAM_ADDR_MAX UINTPTR_MAX | |
48 | # define RAM_ADDR_FMT "%" PRIxPTR | |
f15fbc4b | 49 | #endif |
1ad2134f | 50 | |
96d0e26c WG |
51 | extern ram_addr_t ram_size; |
52 | ||
1ad2134f PB |
53 | /* memory API */ |
54 | ||
a8170e5e AK |
55 | typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); |
56 | typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); | |
1ad2134f | 57 | |
cd19cfa2 | 58 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); |
1ad2134f | 59 | /* This should not be used by devices. */ |
1b5ec234 | 60 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); |
e3dd7493 | 61 | RAMBlock *qemu_ram_block_by_name(const char *name); |
422148d3 DDAG |
62 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
63 | ram_addr_t *ram_addr, ram_addr_t *offset); | |
fa53a0e5 GA |
64 | void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); |
65 | void qemu_ram_unset_idstr(RAMBlock *block); | |
422148d3 | 66 | const char *qemu_ram_get_idstr(RAMBlock *rb); |
1ad2134f | 67 | |
a8170e5e | 68 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
1ad2134f | 69 | int len, int is_write); |
a8170e5e | 70 | static inline void cpu_physical_memory_read(hwaddr addr, |
3bad9814 | 71 | void *buf, int len) |
1ad2134f PB |
72 | { |
73 | cpu_physical_memory_rw(addr, buf, len, 0); | |
74 | } | |
a8170e5e | 75 | static inline void cpu_physical_memory_write(hwaddr addr, |
3bad9814 | 76 | const void *buf, int len) |
1ad2134f | 77 | { |
3bad9814 | 78 | cpu_physical_memory_rw(addr, (void *)buf, len, 1); |
1ad2134f | 79 | } |
a8170e5e AK |
80 | void *cpu_physical_memory_map(hwaddr addr, |
81 | hwaddr *plen, | |
1ad2134f | 82 | int is_write); |
a8170e5e AK |
83 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
84 | int is_write, hwaddr access_len); | |
e95205e1 FZ |
85 | void cpu_register_map_client(QEMUBH *bh); |
86 | void cpu_unregister_map_client(QEMUBH *bh); | |
1ad2134f | 87 | |
a8170e5e | 88 | bool cpu_physical_memory_is_io(hwaddr phys_addr); |
76f35538 | 89 | |
6842a08e BS |
90 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
91 | * This usually implies that write operations are side-effect free. This allows | |
92 | * batching which can make a major impact on performance when using | |
93 | * virtualization. | |
94 | */ | |
6842a08e BS |
95 | void qemu_flush_coalesced_mmio_buffer(void); |
96 | ||
2c17449b | 97 | uint32_t ldub_phys(AddressSpace *as, hwaddr addr); |
41701aa4 EI |
98 | uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr); |
99 | uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr); | |
fdfba1a2 EI |
100 | uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr); |
101 | uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr); | |
2c17449b EI |
102 | uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr); |
103 | uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr); | |
db3be60d | 104 | void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
5ce5944d EI |
105 | void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
106 | void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
ab1da857 EI |
107 | void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
108 | void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
f606604f EI |
109 | void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val); |
110 | void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val); | |
c227f099 | 111 | |
2a221651 | 112 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
1ad2134f | 113 | const uint8_t *buf, int len); |
582b55a9 | 114 | void cpu_flush_icache_range(hwaddr start, int len); |
1ad2134f | 115 | |
0e0df1e2 | 116 | extern struct MemoryRegion io_mem_rom; |
0e0df1e2 | 117 | extern struct MemoryRegion io_mem_notdirty; |
1ad2134f | 118 | |
e3807054 | 119 | typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr, |
bd2fa51f MH |
120 | ram_addr_t offset, ram_addr_t length, void *opaque); |
121 | ||
e3807054 | 122 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); |
bd2fa51f | 123 | |
b3755a91 PB |
124 | #endif |
125 | ||
1ad2134f | 126 | #endif /* !CPU_COMMON_H */ |