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Commit | Line | Data |
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d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d4e8164f FB |
18 | */ |
19 | ||
875cdcf6 AL |
20 | #ifndef _EXEC_ALL_H_ |
21 | #define _EXEC_ALL_H_ | |
7d99a001 BS |
22 | |
23 | #include "qemu-common.h" | |
24 | ||
b346ff46 | 25 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
de9a95f0 | 26 | #define DEBUG_DISAS |
b346ff46 | 27 | |
41c1b1c9 PB |
28 | /* Page tracking code uses ram addresses in system mode, and virtual |
29 | addresses in userspace mode. Define tb_page_addr_t to be an appropriate | |
30 | type. */ | |
31 | #if defined(CONFIG_USER_ONLY) | |
b480d9b7 | 32 | typedef abi_ulong tb_page_addr_t; |
41c1b1c9 PB |
33 | #else |
34 | typedef ram_addr_t tb_page_addr_t; | |
35 | #endif | |
36 | ||
b346ff46 FB |
37 | /* is_jmp field values */ |
38 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
39 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
40 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
41 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
42 | ||
f081c76c | 43 | struct TranslationBlock; |
2e70f6ef | 44 | typedef struct TranslationBlock TranslationBlock; |
b346ff46 FB |
45 | |
46 | /* XXX: make safe guess about sizes */ | |
14dcdac8 | 47 | #define MAX_OP_PER_INSTR 266 |
4d0e4ac7 SB |
48 | |
49 | #if HOST_LONG_BITS == 32 | |
50 | #define MAX_OPC_PARAM_PER_ARG 2 | |
51 | #else | |
52 | #define MAX_OPC_PARAM_PER_ARG 1 | |
53 | #endif | |
3cebc3f1 | 54 | #define MAX_OPC_PARAM_IARGS 5 |
4d0e4ac7 SB |
55 | #define MAX_OPC_PARAM_OARGS 1 |
56 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
57 | ||
58 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
59 | * and up to 4 + N parameters on 64-bit archs | |
60 | * (N = number of input arguments + output arguments). */ | |
61 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
6db73509 | 62 | #define OPC_BUF_SIZE 640 |
b346ff46 FB |
63 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) |
64 | ||
a208e54a | 65 | /* Maximum size a TCG op can expand to. This is complicated because a |
0cbfcd2b AJ |
66 | single op may require several host instructions and register reloads. |
67 | For now take a wild guess at 192 bytes, which should allow at least | |
a208e54a | 68 | a couple of fixup instructions per argument. */ |
0cbfcd2b | 69 | #define TCG_MAX_OP_SIZE 192 |
a208e54a | 70 | |
0115be31 | 71 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
b346ff46 | 72 | |
1de7afc9 | 73 | #include "qemu/log.h" |
b346ff46 | 74 | |
9349b4f9 AF |
75 | void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); |
76 | void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb); | |
77 | void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, | |
e87b7cb0 | 78 | int pc_pos); |
d2856f1a | 79 | |
57fec1fe | 80 | void cpu_gen_init(void); |
9349b4f9 | 81 | int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, |
d07bde88 | 82 | int *gen_code_size_ptr); |
3f38f309 | 83 | bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); |
47c16ed5 | 84 | void page_size_init(void); |
a8a826a3 | 85 | |
0ea8cb88 | 86 | void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); |
90b40a69 | 87 | void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); |
648f034c | 88 | TranslationBlock *tb_gen_code(CPUState *cpu, |
2e70f6ef PB |
89 | target_ulong pc, target_ulong cs_base, int flags, |
90 | int cflags); | |
9349b4f9 | 91 | void cpu_exec_init(CPUArchState *env); |
5638d180 | 92 | void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); |
6375e09e | 93 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc); |
41c1b1c9 | 94 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
2e12669a | 95 | int is_cpu_write_access); |
77a8f1a5 AG |
96 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, |
97 | int is_cpu_write_access); | |
0cac1b66 | 98 | #if !defined(CONFIG_USER_ONLY) |
09daed84 | 99 | void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); |
0cac1b66 | 100 | /* cputlb.c */ |
31b030d4 | 101 | void tlb_flush_page(CPUState *cpu, target_ulong addr); |
00c8cb0a | 102 | void tlb_flush(CPUState *cpu, int flush_global); |
0c591eb0 | 103 | void tlb_set_page(CPUState *cpu, target_ulong vaddr, |
a8170e5e | 104 | hwaddr paddr, int prot, |
d4c430a8 | 105 | int mmu_idx, target_ulong size); |
29d8ec7b | 106 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); |
0cac1b66 | 107 | #else |
31b030d4 | 108 | static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) |
0cac1b66 BS |
109 | { |
110 | } | |
111 | ||
00c8cb0a | 112 | static inline void tlb_flush(CPUState *cpu, int flush_global) |
0cac1b66 BS |
113 | { |
114 | } | |
c527ee8f | 115 | #endif |
d4e8164f | 116 | |
d4e8164f FB |
117 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
118 | ||
4390df51 FB |
119 | #define CODE_GEN_PHYS_HASH_BITS 15 |
120 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
121 | ||
4390df51 FB |
122 | /* estimated block size for TB allocation */ |
123 | /* XXX: use a per code average code fragment size and modulate it | |
124 | according to the host CPU */ | |
125 | #if defined(CONFIG_SOFTMMU) | |
126 | #define CODE_GEN_AVG_BLOCK_SIZE 128 | |
127 | #else | |
128 | #define CODE_GEN_AVG_BLOCK_SIZE 64 | |
129 | #endif | |
130 | ||
5bbd2cae RH |
131 | #if defined(__arm__) || defined(_ARCH_PPC) \ |
132 | || defined(__x86_64__) || defined(__i386__) \ | |
4a136e0a | 133 | || defined(__sparc__) || defined(__aarch64__) \ |
b6bfeea9 | 134 | || defined(__s390x__) || defined(__mips__) \ |
5bbd2cae | 135 | || defined(CONFIG_TCG_INTERPRETER) |
7316329a | 136 | #define USE_DIRECT_JUMP |
d4e8164f FB |
137 | #endif |
138 | ||
2e70f6ef | 139 | struct TranslationBlock { |
2e12669a FB |
140 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
141 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 142 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
143 | uint16_t size; /* size of target code for this block (1 <= |
144 | size <= TARGET_PAGE_SIZE) */ | |
58fe2f10 | 145 | uint16_t cflags; /* compile flags */ |
2e70f6ef PB |
146 | #define CF_COUNT_MASK 0x7fff |
147 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ | |
58fe2f10 | 148 | |
1813e175 | 149 | void *tc_ptr; /* pointer to the translated code */ |
4390df51 | 150 | /* next matching tb for physical address. */ |
5fafdf24 | 151 | struct TranslationBlock *phys_hash_next; |
4390df51 FB |
152 | /* first and second physical page containing code. The lower bit |
153 | of the pointer tells the index in page_next[] */ | |
5fafdf24 | 154 | struct TranslationBlock *page_next[2]; |
41c1b1c9 | 155 | tb_page_addr_t page_addr[2]; |
4390df51 | 156 | |
d4e8164f FB |
157 | /* the following data are used to directly call another TB from |
158 | the code of this one. */ | |
159 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
160 | #ifdef USE_DIRECT_JUMP | |
efc0a514 | 161 | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
d4e8164f | 162 | #else |
6375e09e | 163 | uintptr_t tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
164 | #endif |
165 | /* list of TBs jumping to this one. This is a circular list using | |
166 | the two least significant bits of the pointers to tell what is | |
167 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
168 | jmp_first */ | |
5fafdf24 | 169 | struct TranslationBlock *jmp_next[2]; |
d4e8164f | 170 | struct TranslationBlock *jmp_first; |
2e70f6ef PB |
171 | uint32_t icount; |
172 | }; | |
d4e8164f | 173 | |
5e5f07e0 EV |
174 | #include "exec/spinlock.h" |
175 | ||
176 | typedef struct TBContext TBContext; | |
177 | ||
178 | struct TBContext { | |
179 | ||
180 | TranslationBlock *tbs; | |
181 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; | |
182 | int nb_tbs; | |
183 | /* any access to the tbs or the page table must use this lock */ | |
184 | spinlock_t tb_lock; | |
185 | ||
186 | /* statistics */ | |
187 | int tb_flush_count; | |
188 | int tb_phys_invalidate_count; | |
189 | ||
190 | int tb_invalidated_flag; | |
191 | }; | |
192 | ||
b362e5e0 PB |
193 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
194 | { | |
195 | target_ulong tmp; | |
196 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c | 197 | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; |
b362e5e0 PB |
198 | } |
199 | ||
8a40a180 | 200 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
d4e8164f | 201 | { |
b362e5e0 PB |
202 | target_ulong tmp; |
203 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c EI |
204 | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) |
205 | | (tmp & TB_JMP_ADDR_MASK)); | |
d4e8164f FB |
206 | } |
207 | ||
41c1b1c9 | 208 | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) |
4390df51 | 209 | { |
f96a3834 | 210 | return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); |
4390df51 FB |
211 | } |
212 | ||
2e70f6ef | 213 | void tb_free(TranslationBlock *tb); |
9349b4f9 | 214 | void tb_flush(CPUArchState *env); |
41c1b1c9 | 215 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); |
d4e8164f | 216 | |
4390df51 FB |
217 | #if defined(USE_DIRECT_JUMP) |
218 | ||
7316329a SW |
219 | #if defined(CONFIG_TCG_INTERPRETER) |
220 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
221 | { | |
222 | /* patch the branch destination */ | |
223 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
224 | /* no need to flush icache explicitly */ | |
225 | } | |
226 | #elif defined(_ARCH_PPC) | |
9171478c | 227 | void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); |
810260a8 | 228 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target |
57fec1fe | 229 | #elif defined(__i386__) || defined(__x86_64__) |
6375e09e | 230 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
4390df51 FB |
231 | { |
232 | /* patch the branch destination */ | |
cb3d83bc | 233 | stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4)); |
1235fc06 | 234 | /* no need to flush icache explicitly */ |
4390df51 | 235 | } |
a10c64e0 RH |
236 | #elif defined(__s390x__) |
237 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
238 | { | |
239 | /* patch the branch destination */ | |
240 | intptr_t disp = addr - (jmp_addr - 2); | |
241 | stl_be_p((void*)jmp_addr, disp / 2); | |
242 | /* no need to flush icache explicitly */ | |
243 | } | |
4a136e0a CF |
244 | #elif defined(__aarch64__) |
245 | void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); | |
246 | #define tb_set_jmp_target1 aarch64_tb_set_jmp_target | |
811d4cf4 | 247 | #elif defined(__arm__) |
6375e09e | 248 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
811d4cf4 | 249 | { |
4a1e19ae | 250 | #if !QEMU_GNUC_PREREQ(4, 1) |
811d4cf4 AZ |
251 | register unsigned long _beg __asm ("a1"); |
252 | register unsigned long _end __asm ("a2"); | |
253 | register unsigned long _flg __asm ("a3"); | |
3233f0d4 | 254 | #endif |
811d4cf4 AZ |
255 | |
256 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ | |
87b78ad1 LD |
257 | *(uint32_t *)jmp_addr = |
258 | (*(uint32_t *)jmp_addr & ~0xffffff) | |
259 | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); | |
811d4cf4 | 260 | |
3233f0d4 | 261 | #if QEMU_GNUC_PREREQ(4, 1) |
4a1e19ae | 262 | __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
3233f0d4 | 263 | #else |
811d4cf4 AZ |
264 | /* flush icache */ |
265 | _beg = jmp_addr; | |
266 | _end = jmp_addr + 4; | |
267 | _flg = 0; | |
268 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); | |
3233f0d4 | 269 | #endif |
811d4cf4 | 270 | } |
b6bfeea9 | 271 | #elif defined(__sparc__) || defined(__mips__) |
5bbd2cae | 272 | void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); |
7316329a SW |
273 | #else |
274 | #error tb_set_jmp_target1 is missing | |
4390df51 | 275 | #endif |
d4e8164f | 276 | |
5fafdf24 | 277 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
6375e09e | 278 | int n, uintptr_t addr) |
4cbb86e1 | 279 | { |
6375e09e SW |
280 | uint16_t offset = tb->tb_jmp_offset[n]; |
281 | tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); | |
4cbb86e1 FB |
282 | } |
283 | ||
d4e8164f FB |
284 | #else |
285 | ||
286 | /* set the jump target */ | |
5fafdf24 | 287 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
6375e09e | 288 | int n, uintptr_t addr) |
d4e8164f | 289 | { |
95f7652d | 290 | tb->tb_next[n] = addr; |
d4e8164f FB |
291 | } |
292 | ||
293 | #endif | |
294 | ||
5fafdf24 | 295 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
296 | TranslationBlock *tb_next) |
297 | { | |
cf25629d FB |
298 | /* NOTE: this test is only needed for thread safety */ |
299 | if (!tb->jmp_next[n]) { | |
300 | /* patch the native jump address */ | |
6375e09e | 301 | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); |
3b46e624 | 302 | |
cf25629d FB |
303 | /* add in TB jmp circular list */ |
304 | tb->jmp_next[n] = tb_next->jmp_first; | |
6375e09e | 305 | tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n)); |
cf25629d | 306 | } |
d4e8164f FB |
307 | } |
308 | ||
0f842f8a RH |
309 | /* GETRA is the true target of the return instruction that we'll execute, |
310 | defined here for simplicity of defining the follow-up macros. */ | |
7316329a | 311 | #if defined(CONFIG_TCG_INTERPRETER) |
c3ca0467 | 312 | extern uintptr_t tci_tb_ptr; |
0f842f8a RH |
313 | # define GETRA() tci_tb_ptr |
314 | #else | |
315 | # define GETRA() \ | |
316 | ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) | |
317 | #endif | |
318 | ||
319 | /* The true return address will often point to a host insn that is part of | |
320 | the next translated guest insn. Adjust the address backward to point to | |
321 | the middle of the call insn. Subtracting one would do the job except for | |
322 | several compressed mode architectures (arm, mips) which set the low bit | |
323 | to indicate the compressed mode; subtracting two works around that. It | |
324 | is also the case that there are no host isas that contain a call insn | |
325 | smaller than 4 bytes, so we don't worry about special-casing this. */ | |
326 | #if defined(CONFIG_TCG_INTERPRETER) | |
327 | # define GETPC_ADJ 0 | |
3917149d | 328 | #else |
0f842f8a | 329 | # define GETPC_ADJ 2 |
3917149d BS |
330 | #endif |
331 | ||
0f842f8a RH |
332 | #define GETPC() (GETRA() - GETPC_ADJ) |
333 | ||
e95c8d51 | 334 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 335 | |
575ddeb4 | 336 | void phys_mem_set_alloc(void *(*alloc)(size_t)); |
91138037 | 337 | |
77717094 | 338 | struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index); |
791af8c8 PB |
339 | bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, |
340 | uint64_t *pvalue, unsigned size); | |
341 | bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, | |
37ec01d4 | 342 | uint64_t value, unsigned size); |
b3755a91 | 343 | |
d5a11fef | 344 | void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 345 | uintptr_t retaddr); |
6e59c1db | 346 | |
6e59c1db | 347 | #endif |
4390df51 FB |
348 | |
349 | #if defined(CONFIG_USER_ONLY) | |
9349b4f9 | 350 | static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) |
4390df51 FB |
351 | { |
352 | return addr; | |
353 | } | |
354 | #else | |
0cac1b66 | 355 | /* cputlb.c */ |
9349b4f9 | 356 | tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); |
4390df51 | 357 | #endif |
9df217a3 | 358 | |
1b530a6d AJ |
359 | /* vl.c */ |
360 | extern int singlestep; | |
361 | ||
1a28cac3 MT |
362 | /* cpu-exec.c */ |
363 | extern volatile sig_atomic_t exit_request; | |
364 | ||
99df7dce AF |
365 | /** |
366 | * cpu_can_do_io: | |
367 | * @cpu: The CPU for which to check IO. | |
368 | * | |
369 | * Deterministic execution requires that IO only be performed on the last | |
370 | * instruction of a TB so that interrupts take effect immediately. | |
371 | * | |
372 | * Returns: %true if memory-mapped IO is safe, %false otherwise. | |
373 | */ | |
374 | static inline bool cpu_can_do_io(CPUState *cpu) | |
946fb27c PB |
375 | { |
376 | if (!use_icount) { | |
99df7dce | 377 | return true; |
946fb27c PB |
378 | } |
379 | /* If not executing code then assume we are ok. */ | |
d77953b9 | 380 | if (cpu->current_tb == NULL) { |
99df7dce | 381 | return true; |
946fb27c | 382 | } |
99df7dce | 383 | return cpu->can_do_io != 0; |
946fb27c PB |
384 | } |
385 | ||
875cdcf6 | 386 | #endif |