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d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d4e8164f FB |
18 | */ |
19 | ||
875cdcf6 AL |
20 | #ifndef _EXEC_ALL_H_ |
21 | #define _EXEC_ALL_H_ | |
7d99a001 BS |
22 | |
23 | #include "qemu-common.h" | |
24 | ||
b346ff46 | 25 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
de9a95f0 | 26 | #define DEBUG_DISAS |
b346ff46 | 27 | |
41c1b1c9 PB |
28 | /* Page tracking code uses ram addresses in system mode, and virtual |
29 | addresses in userspace mode. Define tb_page_addr_t to be an appropriate | |
30 | type. */ | |
31 | #if defined(CONFIG_USER_ONLY) | |
b480d9b7 | 32 | typedef abi_ulong tb_page_addr_t; |
41c1b1c9 PB |
33 | #else |
34 | typedef ram_addr_t tb_page_addr_t; | |
35 | #endif | |
36 | ||
b346ff46 FB |
37 | /* is_jmp field values */ |
38 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
39 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
40 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
41 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
42 | ||
f081c76c | 43 | struct TranslationBlock; |
2e70f6ef | 44 | typedef struct TranslationBlock TranslationBlock; |
b346ff46 FB |
45 | |
46 | /* XXX: make safe guess about sizes */ | |
14dcdac8 | 47 | #define MAX_OP_PER_INSTR 266 |
4d0e4ac7 SB |
48 | |
49 | #if HOST_LONG_BITS == 32 | |
50 | #define MAX_OPC_PARAM_PER_ARG 2 | |
51 | #else | |
52 | #define MAX_OPC_PARAM_PER_ARG 1 | |
53 | #endif | |
3cebc3f1 | 54 | #define MAX_OPC_PARAM_IARGS 5 |
4d0e4ac7 SB |
55 | #define MAX_OPC_PARAM_OARGS 1 |
56 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
57 | ||
58 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
59 | * and up to 4 + N parameters on 64-bit archs | |
60 | * (N = number of input arguments + output arguments). */ | |
61 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
6db73509 | 62 | #define OPC_BUF_SIZE 640 |
b346ff46 FB |
63 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) |
64 | ||
0115be31 | 65 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
b346ff46 | 66 | |
1de7afc9 | 67 | #include "qemu/log.h" |
b346ff46 | 68 | |
9349b4f9 | 69 | void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); |
9349b4f9 | 70 | void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, |
bad729e2 | 71 | target_ulong *data); |
d2856f1a | 72 | |
57fec1fe | 73 | void cpu_gen_init(void); |
3f38f309 | 74 | bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); |
a8a826a3 | 75 | |
0ea8cb88 | 76 | void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); |
90b40a69 | 77 | void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); |
648f034c | 78 | TranslationBlock *tb_gen_code(CPUState *cpu, |
2e70f6ef PB |
79 | target_ulong pc, target_ulong cs_base, int flags, |
80 | int cflags); | |
4bad9e39 | 81 | void cpu_exec_init(CPUState *cpu, Error **errp); |
5638d180 | 82 | void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); |
1c3c8af1 | 83 | void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); |
1652b974 | 84 | |
0cac1b66 | 85 | #if !defined(CONFIG_USER_ONLY) |
32857f4d | 86 | void cpu_reloading_memory_map(void); |
56943e8c PM |
87 | /** |
88 | * cpu_address_space_init: | |
89 | * @cpu: CPU to add this address space to | |
90 | * @as: address space to add | |
91 | * @asidx: integer index of this address space | |
92 | * | |
93 | * Add the specified address space to the CPU's cpu_ases list. | |
94 | * The address space added with @asidx 0 is the one used for the | |
95 | * convenience pointer cpu->as. | |
96 | * The target-specific code which registers ASes is responsible | |
97 | * for defining what semantics address space 0, 1, 2, etc have. | |
98 | * | |
12ebc9a7 PM |
99 | * Before the first call to this function, the caller must set |
100 | * cpu->num_ases to the total number of address spaces it needs | |
101 | * to support. | |
102 | * | |
56943e8c PM |
103 | * Note that with KVM only one address space is supported. |
104 | */ | |
105 | void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); | |
651a5bc0 PM |
106 | /** |
107 | * cpu_get_address_space: | |
108 | * @cpu: CPU to get address space from | |
109 | * @asidx: index identifying which address space to get | |
110 | * | |
111 | * Return the requested address space of this CPU. @asidx | |
112 | * specifies which address space to read. | |
113 | */ | |
114 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
0cac1b66 | 115 | /* cputlb.c */ |
d7a74a9d PM |
116 | /** |
117 | * tlb_flush_page: | |
118 | * @cpu: CPU whose TLB should be flushed | |
119 | * @addr: virtual address of page to be flushed | |
120 | * | |
121 | * Flush one page from the TLB of the specified CPU, for all | |
122 | * MMU indexes. | |
123 | */ | |
31b030d4 | 124 | void tlb_flush_page(CPUState *cpu, target_ulong addr); |
d7a74a9d PM |
125 | /** |
126 | * tlb_flush: | |
127 | * @cpu: CPU whose TLB should be flushed | |
128 | * @flush_global: ignored | |
129 | * | |
130 | * Flush the entire TLB for the specified CPU. | |
131 | * The flush_global flag is in theory an indicator of whether the whole | |
132 | * TLB should be flushed, or only those entries not marked global. | |
133 | * In practice QEMU does not implement any global/not global flag for | |
134 | * TLB entries, and the argument is ignored. | |
135 | */ | |
00c8cb0a | 136 | void tlb_flush(CPUState *cpu, int flush_global); |
d7a74a9d PM |
137 | /** |
138 | * tlb_flush_page_by_mmuidx: | |
139 | * @cpu: CPU whose TLB should be flushed | |
140 | * @addr: virtual address of page to be flushed | |
141 | * @...: list of MMU indexes to flush, terminated by a negative value | |
142 | * | |
143 | * Flush one page from the TLB of the specified CPU, for the specified | |
144 | * MMU indexes. | |
145 | */ | |
146 | void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...); | |
147 | /** | |
148 | * tlb_flush_by_mmuidx: | |
149 | * @cpu: CPU whose TLB should be flushed | |
150 | * @...: list of MMU indexes to flush, terminated by a negative value | |
151 | * | |
152 | * Flush all entries from the TLB of the specified CPU, for the specified | |
153 | * MMU indexes. | |
154 | */ | |
155 | void tlb_flush_by_mmuidx(CPUState *cpu, ...); | |
1787cc8e PM |
156 | /** |
157 | * tlb_set_page_with_attrs: | |
158 | * @cpu: CPU to add this TLB entry for | |
159 | * @vaddr: virtual address of page to add entry for | |
160 | * @paddr: physical address of the page | |
161 | * @attrs: memory transaction attributes | |
162 | * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) | |
163 | * @mmu_idx: MMU index to insert TLB entry for | |
164 | * @size: size of the page in bytes | |
165 | * | |
166 | * Add an entry to this CPU's TLB (a mapping from virtual address | |
167 | * @vaddr to physical address @paddr) with the specified memory | |
168 | * transaction attributes. This is generally called by the target CPU | |
169 | * specific code after it has been called through the tlb_fill() | |
170 | * entry point and performed a successful page table walk to find | |
171 | * the physical address and attributes for the virtual address | |
172 | * which provoked the TLB miss. | |
173 | * | |
174 | * At most one entry for a given virtual address is permitted. Only a | |
175 | * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only | |
176 | * used by tlb_flush_page. | |
177 | */ | |
fadc1cbe PM |
178 | void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, |
179 | hwaddr paddr, MemTxAttrs attrs, | |
180 | int prot, int mmu_idx, target_ulong size); | |
1787cc8e PM |
181 | /* tlb_set_page: |
182 | * | |
183 | * This function is equivalent to calling tlb_set_page_with_attrs() | |
184 | * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided | |
185 | * as a convenience for CPUs which don't use memory transaction attributes. | |
186 | */ | |
187 | void tlb_set_page(CPUState *cpu, target_ulong vaddr, | |
188 | hwaddr paddr, int prot, | |
189 | int mmu_idx, target_ulong size); | |
29d8ec7b | 190 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); |
3b4afc9e YK |
191 | void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, |
192 | uintptr_t retaddr); | |
0cac1b66 | 193 | #else |
31b030d4 | 194 | static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) |
0cac1b66 BS |
195 | { |
196 | } | |
197 | ||
00c8cb0a | 198 | static inline void tlb_flush(CPUState *cpu, int flush_global) |
0cac1b66 BS |
199 | { |
200 | } | |
d7a74a9d PM |
201 | |
202 | static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, | |
203 | target_ulong addr, ...) | |
204 | { | |
205 | } | |
206 | ||
207 | static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) | |
208 | { | |
209 | } | |
c527ee8f | 210 | #endif |
d4e8164f | 211 | |
d4e8164f FB |
212 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
213 | ||
4390df51 FB |
214 | #define CODE_GEN_PHYS_HASH_BITS 15 |
215 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
216 | ||
126d89e8 RH |
217 | /* Estimated block size for TB allocation. */ |
218 | /* ??? The following is based on a 2015 survey of x86_64 host output. | |
219 | Better would seem to be some sort of dynamically sized TB array, | |
220 | adapting to the block sizes actually being produced. */ | |
4390df51 | 221 | #if defined(CONFIG_SOFTMMU) |
126d89e8 | 222 | #define CODE_GEN_AVG_BLOCK_SIZE 400 |
4390df51 | 223 | #else |
126d89e8 | 224 | #define CODE_GEN_AVG_BLOCK_SIZE 150 |
4390df51 FB |
225 | #endif |
226 | ||
5bbd2cae RH |
227 | #if defined(__arm__) || defined(_ARCH_PPC) \ |
228 | || defined(__x86_64__) || defined(__i386__) \ | |
4a136e0a | 229 | || defined(__sparc__) || defined(__aarch64__) \ |
b6bfeea9 | 230 | || defined(__s390x__) || defined(__mips__) \ |
5bbd2cae | 231 | || defined(CONFIG_TCG_INTERPRETER) |
7316329a | 232 | #define USE_DIRECT_JUMP |
d4e8164f FB |
233 | #endif |
234 | ||
2e70f6ef | 235 | struct TranslationBlock { |
2e12669a FB |
236 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
237 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 238 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
239 | uint16_t size; /* size of target code for this block (1 <= |
240 | size <= TARGET_PAGE_SIZE) */ | |
0266359e PB |
241 | uint16_t icount; |
242 | uint32_t cflags; /* compile flags */ | |
2e70f6ef PB |
243 | #define CF_COUNT_MASK 0x7fff |
244 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ | |
d8a499f1 | 245 | #define CF_NOCACHE 0x10000 /* To be freed after execution */ |
0266359e | 246 | #define CF_USE_ICOUNT 0x20000 |
56c0269a | 247 | #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ |
58fe2f10 | 248 | |
1813e175 | 249 | void *tc_ptr; /* pointer to the translated code */ |
fca8a500 | 250 | uint8_t *tc_search; /* pointer to search data */ |
4390df51 | 251 | /* next matching tb for physical address. */ |
5fafdf24 | 252 | struct TranslationBlock *phys_hash_next; |
02d57ea1 SF |
253 | /* original tb when cflags has CF_NOCACHE */ |
254 | struct TranslationBlock *orig_tb; | |
4390df51 FB |
255 | /* first and second physical page containing code. The lower bit |
256 | of the pointer tells the index in page_next[] */ | |
5fafdf24 | 257 | struct TranslationBlock *page_next[2]; |
41c1b1c9 | 258 | tb_page_addr_t page_addr[2]; |
4390df51 | 259 | |
d4e8164f FB |
260 | /* the following data are used to directly call another TB from |
261 | the code of this one. */ | |
262 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
263 | #ifdef USE_DIRECT_JUMP | |
efc0a514 | 264 | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
d4e8164f | 265 | #else |
6375e09e | 266 | uintptr_t tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
267 | #endif |
268 | /* list of TBs jumping to this one. This is a circular list using | |
269 | the two least significant bits of the pointers to tell what is | |
270 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
271 | jmp_first */ | |
5fafdf24 | 272 | struct TranslationBlock *jmp_next[2]; |
d4e8164f | 273 | struct TranslationBlock *jmp_first; |
2e70f6ef | 274 | }; |
d4e8164f | 275 | |
677ef623 | 276 | #include "qemu/thread.h" |
5e5f07e0 EV |
277 | |
278 | typedef struct TBContext TBContext; | |
279 | ||
280 | struct TBContext { | |
281 | ||
282 | TranslationBlock *tbs; | |
283 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; | |
284 | int nb_tbs; | |
285 | /* any access to the tbs or the page table must use this lock */ | |
677ef623 | 286 | QemuMutex tb_lock; |
5e5f07e0 EV |
287 | |
288 | /* statistics */ | |
289 | int tb_flush_count; | |
290 | int tb_phys_invalidate_count; | |
291 | ||
292 | int tb_invalidated_flag; | |
293 | }; | |
294 | ||
2e70f6ef | 295 | void tb_free(TranslationBlock *tb); |
bbd77c18 | 296 | void tb_flush(CPUState *cpu); |
41c1b1c9 | 297 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); |
d4e8164f | 298 | |
4390df51 FB |
299 | #if defined(USE_DIRECT_JUMP) |
300 | ||
7316329a SW |
301 | #if defined(CONFIG_TCG_INTERPRETER) |
302 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
303 | { | |
304 | /* patch the branch destination */ | |
305 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
306 | /* no need to flush icache explicitly */ | |
307 | } | |
308 | #elif defined(_ARCH_PPC) | |
9171478c | 309 | void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); |
810260a8 | 310 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target |
57fec1fe | 311 | #elif defined(__i386__) || defined(__x86_64__) |
6375e09e | 312 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
4390df51 FB |
313 | { |
314 | /* patch the branch destination */ | |
cb3d83bc | 315 | stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4)); |
1235fc06 | 316 | /* no need to flush icache explicitly */ |
4390df51 | 317 | } |
a10c64e0 RH |
318 | #elif defined(__s390x__) |
319 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
320 | { | |
321 | /* patch the branch destination */ | |
322 | intptr_t disp = addr - (jmp_addr - 2); | |
323 | stl_be_p((void*)jmp_addr, disp / 2); | |
324 | /* no need to flush icache explicitly */ | |
325 | } | |
4a136e0a CF |
326 | #elif defined(__aarch64__) |
327 | void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); | |
328 | #define tb_set_jmp_target1 aarch64_tb_set_jmp_target | |
811d4cf4 | 329 | #elif defined(__arm__) |
6375e09e | 330 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
811d4cf4 | 331 | { |
4a1e19ae | 332 | #if !QEMU_GNUC_PREREQ(4, 1) |
811d4cf4 AZ |
333 | register unsigned long _beg __asm ("a1"); |
334 | register unsigned long _end __asm ("a2"); | |
335 | register unsigned long _flg __asm ("a3"); | |
3233f0d4 | 336 | #endif |
811d4cf4 AZ |
337 | |
338 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ | |
87b78ad1 LD |
339 | *(uint32_t *)jmp_addr = |
340 | (*(uint32_t *)jmp_addr & ~0xffffff) | |
341 | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); | |
811d4cf4 | 342 | |
3233f0d4 | 343 | #if QEMU_GNUC_PREREQ(4, 1) |
4a1e19ae | 344 | __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
3233f0d4 | 345 | #else |
811d4cf4 AZ |
346 | /* flush icache */ |
347 | _beg = jmp_addr; | |
348 | _end = jmp_addr + 4; | |
349 | _flg = 0; | |
350 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); | |
3233f0d4 | 351 | #endif |
811d4cf4 | 352 | } |
b6bfeea9 | 353 | #elif defined(__sparc__) || defined(__mips__) |
5bbd2cae | 354 | void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); |
7316329a SW |
355 | #else |
356 | #error tb_set_jmp_target1 is missing | |
4390df51 | 357 | #endif |
d4e8164f | 358 | |
5fafdf24 | 359 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
6375e09e | 360 | int n, uintptr_t addr) |
4cbb86e1 | 361 | { |
6375e09e SW |
362 | uint16_t offset = tb->tb_jmp_offset[n]; |
363 | tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); | |
4cbb86e1 FB |
364 | } |
365 | ||
d4e8164f FB |
366 | #else |
367 | ||
368 | /* set the jump target */ | |
5fafdf24 | 369 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
6375e09e | 370 | int n, uintptr_t addr) |
d4e8164f | 371 | { |
95f7652d | 372 | tb->tb_next[n] = addr; |
d4e8164f FB |
373 | } |
374 | ||
375 | #endif | |
376 | ||
5fafdf24 | 377 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
378 | TranslationBlock *tb_next) |
379 | { | |
cf25629d FB |
380 | /* NOTE: this test is only needed for thread safety */ |
381 | if (!tb->jmp_next[n]) { | |
382 | /* patch the native jump address */ | |
6375e09e | 383 | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); |
3b46e624 | 384 | |
cf25629d FB |
385 | /* add in TB jmp circular list */ |
386 | tb->jmp_next[n] = tb_next->jmp_first; | |
6375e09e | 387 | tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n)); |
cf25629d | 388 | } |
d4e8164f FB |
389 | } |
390 | ||
0f842f8a RH |
391 | /* GETRA is the true target of the return instruction that we'll execute, |
392 | defined here for simplicity of defining the follow-up macros. */ | |
7316329a | 393 | #if defined(CONFIG_TCG_INTERPRETER) |
c3ca0467 | 394 | extern uintptr_t tci_tb_ptr; |
0f842f8a RH |
395 | # define GETRA() tci_tb_ptr |
396 | #else | |
397 | # define GETRA() \ | |
398 | ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) | |
399 | #endif | |
400 | ||
401 | /* The true return address will often point to a host insn that is part of | |
402 | the next translated guest insn. Adjust the address backward to point to | |
403 | the middle of the call insn. Subtracting one would do the job except for | |
404 | several compressed mode architectures (arm, mips) which set the low bit | |
405 | to indicate the compressed mode; subtracting two works around that. It | |
406 | is also the case that there are no host isas that contain a call insn | |
407 | smaller than 4 bytes, so we don't worry about special-casing this. */ | |
a17d4482 | 408 | #define GETPC_ADJ 2 |
3917149d | 409 | |
0f842f8a RH |
410 | #define GETPC() (GETRA() - GETPC_ADJ) |
411 | ||
e95c8d51 | 412 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 413 | |
9d82b5a7 | 414 | struct MemoryRegion *iotlb_to_region(CPUState *cpu, |
a54c87b6 | 415 | hwaddr index, MemTxAttrs attrs); |
b3755a91 | 416 | |
d5a11fef | 417 | void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 418 | uintptr_t retaddr); |
6e59c1db | 419 | |
6e59c1db | 420 | #endif |
4390df51 FB |
421 | |
422 | #if defined(CONFIG_USER_ONLY) | |
8fd19e6c PB |
423 | void mmap_lock(void); |
424 | void mmap_unlock(void); | |
425 | ||
9349b4f9 | 426 | static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) |
4390df51 FB |
427 | { |
428 | return addr; | |
429 | } | |
430 | #else | |
8fd19e6c PB |
431 | static inline void mmap_lock(void) {} |
432 | static inline void mmap_unlock(void) {} | |
433 | ||
0cac1b66 | 434 | /* cputlb.c */ |
9349b4f9 | 435 | tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); |
dfccc760 PC |
436 | |
437 | void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); | |
438 | void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); | |
439 | ||
440 | /* exec.c */ | |
441 | void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); | |
442 | ||
443 | MemoryRegionSection * | |
d7898cda PM |
444 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
445 | hwaddr *xlat, hwaddr *plen); | |
dfccc760 PC |
446 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
447 | MemoryRegionSection *section, | |
448 | target_ulong vaddr, | |
449 | hwaddr paddr, hwaddr xlat, | |
450 | int prot, | |
451 | target_ulong *address); | |
452 | bool memory_region_is_unassigned(MemoryRegion *mr); | |
453 | ||
4390df51 | 454 | #endif |
9df217a3 | 455 | |
1b530a6d AJ |
456 | /* vl.c */ |
457 | extern int singlestep; | |
458 | ||
e0c38211 | 459 | /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */ |
9373e632 | 460 | extern CPUState *tcg_current_cpu; |
e0c38211 | 461 | extern bool exit_request; |
1a28cac3 | 462 | |
875cdcf6 | 463 | #endif |