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d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d4e8164f FB |
18 | */ |
19 | ||
2a6a4076 MA |
20 | #ifndef EXEC_ALL_H |
21 | #define EXEC_ALL_H | |
7d99a001 BS |
22 | |
23 | #include "qemu-common.h" | |
00f6da6a | 24 | #include "exec/tb-context.h" |
7d99a001 | 25 | |
b346ff46 | 26 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
de9a95f0 | 27 | #define DEBUG_DISAS |
b346ff46 | 28 | |
41c1b1c9 PB |
29 | /* Page tracking code uses ram addresses in system mode, and virtual |
30 | addresses in userspace mode. Define tb_page_addr_t to be an appropriate | |
31 | type. */ | |
32 | #if defined(CONFIG_USER_ONLY) | |
b480d9b7 | 33 | typedef abi_ulong tb_page_addr_t; |
41c1b1c9 PB |
34 | #else |
35 | typedef ram_addr_t tb_page_addr_t; | |
36 | #endif | |
37 | ||
b346ff46 FB |
38 | /* is_jmp field values */ |
39 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
40 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
41 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
42 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
43 | ||
1de7afc9 | 44 | #include "qemu/log.h" |
b346ff46 | 45 | |
9349b4f9 | 46 | void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); |
9349b4f9 | 47 | void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, |
bad729e2 | 48 | target_ulong *data); |
d2856f1a | 49 | |
57fec1fe | 50 | void cpu_gen_init(void); |
3f38f309 | 51 | bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); |
a8a826a3 | 52 | |
6886b980 | 53 | void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); |
90b40a69 | 54 | void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); |
648f034c | 55 | TranslationBlock *tb_gen_code(CPUState *cpu, |
89fee74a EC |
56 | target_ulong pc, target_ulong cs_base, |
57 | uint32_t flags, | |
2e70f6ef | 58 | int cflags); |
1bc7e522 | 59 | |
5638d180 | 60 | void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); |
1c3c8af1 | 61 | void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); |
fdbc2b57 | 62 | void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); |
1652b974 | 63 | |
0cac1b66 | 64 | #if !defined(CONFIG_USER_ONLY) |
32857f4d | 65 | void cpu_reloading_memory_map(void); |
56943e8c PM |
66 | /** |
67 | * cpu_address_space_init: | |
68 | * @cpu: CPU to add this address space to | |
69 | * @as: address space to add | |
70 | * @asidx: integer index of this address space | |
71 | * | |
72 | * Add the specified address space to the CPU's cpu_ases list. | |
73 | * The address space added with @asidx 0 is the one used for the | |
74 | * convenience pointer cpu->as. | |
75 | * The target-specific code which registers ASes is responsible | |
76 | * for defining what semantics address space 0, 1, 2, etc have. | |
77 | * | |
12ebc9a7 PM |
78 | * Before the first call to this function, the caller must set |
79 | * cpu->num_ases to the total number of address spaces it needs | |
80 | * to support. | |
81 | * | |
56943e8c PM |
82 | * Note that with KVM only one address space is supported. |
83 | */ | |
84 | void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); | |
0cac1b66 | 85 | /* cputlb.c */ |
d7a74a9d PM |
86 | /** |
87 | * tlb_flush_page: | |
88 | * @cpu: CPU whose TLB should be flushed | |
89 | * @addr: virtual address of page to be flushed | |
90 | * | |
91 | * Flush one page from the TLB of the specified CPU, for all | |
92 | * MMU indexes. | |
93 | */ | |
31b030d4 | 94 | void tlb_flush_page(CPUState *cpu, target_ulong addr); |
d7a74a9d PM |
95 | /** |
96 | * tlb_flush: | |
97 | * @cpu: CPU whose TLB should be flushed | |
d7a74a9d | 98 | * |
d10eb08f AB |
99 | * Flush the entire TLB for the specified CPU. Most CPU architectures |
100 | * allow the implementation to drop entries from the TLB at any time | |
101 | * so this is generally safe. If more selective flushing is required | |
102 | * use one of the other functions for efficiency. | |
d7a74a9d | 103 | */ |
d10eb08f | 104 | void tlb_flush(CPUState *cpu); |
d7a74a9d PM |
105 | /** |
106 | * tlb_flush_page_by_mmuidx: | |
107 | * @cpu: CPU whose TLB should be flushed | |
108 | * @addr: virtual address of page to be flushed | |
109 | * @...: list of MMU indexes to flush, terminated by a negative value | |
110 | * | |
111 | * Flush one page from the TLB of the specified CPU, for the specified | |
112 | * MMU indexes. | |
113 | */ | |
114 | void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...); | |
115 | /** | |
116 | * tlb_flush_by_mmuidx: | |
117 | * @cpu: CPU whose TLB should be flushed | |
118 | * @...: list of MMU indexes to flush, terminated by a negative value | |
119 | * | |
120 | * Flush all entries from the TLB of the specified CPU, for the specified | |
121 | * MMU indexes. | |
122 | */ | |
123 | void tlb_flush_by_mmuidx(CPUState *cpu, ...); | |
1787cc8e PM |
124 | /** |
125 | * tlb_set_page_with_attrs: | |
126 | * @cpu: CPU to add this TLB entry for | |
127 | * @vaddr: virtual address of page to add entry for | |
128 | * @paddr: physical address of the page | |
129 | * @attrs: memory transaction attributes | |
130 | * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) | |
131 | * @mmu_idx: MMU index to insert TLB entry for | |
132 | * @size: size of the page in bytes | |
133 | * | |
134 | * Add an entry to this CPU's TLB (a mapping from virtual address | |
135 | * @vaddr to physical address @paddr) with the specified memory | |
136 | * transaction attributes. This is generally called by the target CPU | |
137 | * specific code after it has been called through the tlb_fill() | |
138 | * entry point and performed a successful page table walk to find | |
139 | * the physical address and attributes for the virtual address | |
140 | * which provoked the TLB miss. | |
141 | * | |
142 | * At most one entry for a given virtual address is permitted. Only a | |
143 | * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only | |
144 | * used by tlb_flush_page. | |
145 | */ | |
fadc1cbe PM |
146 | void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, |
147 | hwaddr paddr, MemTxAttrs attrs, | |
148 | int prot, int mmu_idx, target_ulong size); | |
1787cc8e PM |
149 | /* tlb_set_page: |
150 | * | |
151 | * This function is equivalent to calling tlb_set_page_with_attrs() | |
152 | * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided | |
153 | * as a convenience for CPUs which don't use memory transaction attributes. | |
154 | */ | |
155 | void tlb_set_page(CPUState *cpu, target_ulong vaddr, | |
156 | hwaddr paddr, int prot, | |
157 | int mmu_idx, target_ulong size); | |
29d8ec7b | 158 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); |
3b4afc9e YK |
159 | void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, |
160 | uintptr_t retaddr); | |
0cac1b66 | 161 | #else |
31b030d4 | 162 | static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) |
0cac1b66 BS |
163 | { |
164 | } | |
165 | ||
d10eb08f | 166 | static inline void tlb_flush(CPUState *cpu) |
0cac1b66 BS |
167 | { |
168 | } | |
d7a74a9d PM |
169 | |
170 | static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, | |
171 | target_ulong addr, ...) | |
172 | { | |
173 | } | |
174 | ||
175 | static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) | |
176 | { | |
177 | } | |
c527ee8f | 178 | #endif |
d4e8164f | 179 | |
d4e8164f FB |
180 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
181 | ||
126d89e8 RH |
182 | /* Estimated block size for TB allocation. */ |
183 | /* ??? The following is based on a 2015 survey of x86_64 host output. | |
184 | Better would seem to be some sort of dynamically sized TB array, | |
185 | adapting to the block sizes actually being produced. */ | |
4390df51 | 186 | #if defined(CONFIG_SOFTMMU) |
126d89e8 | 187 | #define CODE_GEN_AVG_BLOCK_SIZE 400 |
4390df51 | 188 | #else |
126d89e8 | 189 | #define CODE_GEN_AVG_BLOCK_SIZE 150 |
4390df51 FB |
190 | #endif |
191 | ||
5bbd2cae RH |
192 | #if defined(__arm__) || defined(_ARCH_PPC) \ |
193 | || defined(__x86_64__) || defined(__i386__) \ | |
4a136e0a | 194 | || defined(__sparc__) || defined(__aarch64__) \ |
b6bfeea9 | 195 | || defined(__s390x__) || defined(__mips__) \ |
5bbd2cae | 196 | || defined(CONFIG_TCG_INTERPRETER) |
10b4f485 | 197 | /* NOTE: Direct jump patching must be atomic to be thread-safe. */ |
7316329a | 198 | #define USE_DIRECT_JUMP |
d4e8164f FB |
199 | #endif |
200 | ||
2e70f6ef | 201 | struct TranslationBlock { |
2e12669a FB |
202 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
203 | target_ulong cs_base; /* CS base for this block */ | |
89fee74a | 204 | uint32_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
205 | uint16_t size; /* size of target code for this block (1 <= |
206 | size <= TARGET_PAGE_SIZE) */ | |
0266359e PB |
207 | uint16_t icount; |
208 | uint32_t cflags; /* compile flags */ | |
2e70f6ef PB |
209 | #define CF_COUNT_MASK 0x7fff |
210 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ | |
d8a499f1 | 211 | #define CF_NOCACHE 0x10000 /* To be freed after execution */ |
0266359e | 212 | #define CF_USE_ICOUNT 0x20000 |
56c0269a | 213 | #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ |
58fe2f10 | 214 | |
6d21e420 PB |
215 | uint16_t invalid; |
216 | ||
1813e175 | 217 | void *tc_ptr; /* pointer to the translated code */ |
fca8a500 | 218 | uint8_t *tc_search; /* pointer to search data */ |
02d57ea1 SF |
219 | /* original tb when cflags has CF_NOCACHE */ |
220 | struct TranslationBlock *orig_tb; | |
4390df51 FB |
221 | /* first and second physical page containing code. The lower bit |
222 | of the pointer tells the index in page_next[] */ | |
5fafdf24 | 223 | struct TranslationBlock *page_next[2]; |
41c1b1c9 | 224 | tb_page_addr_t page_addr[2]; |
4390df51 | 225 | |
f309101c SF |
226 | /* The following data are used to directly call another TB from |
227 | * the code of this one. This can be done either by emitting direct or | |
228 | * indirect native jump instructions. These jumps are reset so that the TB | |
229 | * just continue its execution. The TB can be linked to another one by | |
230 | * setting one of the jump targets (or patching the jump instruction). Only | |
231 | * two of such jumps are supported. | |
232 | */ | |
233 | uint16_t jmp_reset_offset[2]; /* offset of original jump target */ | |
234 | #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ | |
d4e8164f | 235 | #ifdef USE_DIRECT_JUMP |
f309101c | 236 | uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */ |
d4e8164f | 237 | #else |
f309101c | 238 | uintptr_t jmp_target_addr[2]; /* target address for indirect jump */ |
d4e8164f | 239 | #endif |
f309101c SF |
240 | /* Each TB has an assosiated circular list of TBs jumping to this one. |
241 | * jmp_list_first points to the first TB jumping to this one. | |
242 | * jmp_list_next is used to point to the next TB in a list. | |
243 | * Since each TB can have two jumps, it can participate in two lists. | |
c37e6d7e SF |
244 | * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a |
245 | * TranslationBlock structure, but the two least significant bits of | |
246 | * them are used to encode which data field of the pointed TB should | |
247 | * be used to traverse the list further from that TB: | |
f309101c SF |
248 | * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first. |
249 | * In other words, 0/1 tells which jump is used in the pointed TB, | |
250 | * and 2 means that this is a pointer back to the target TB of this list. | |
251 | */ | |
c37e6d7e SF |
252 | uintptr_t jmp_list_next[2]; |
253 | uintptr_t jmp_list_first; | |
2e70f6ef | 254 | }; |
d4e8164f | 255 | |
2e70f6ef | 256 | void tb_free(TranslationBlock *tb); |
bbd77c18 | 257 | void tb_flush(CPUState *cpu); |
41c1b1c9 | 258 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); |
d4e8164f | 259 | |
4390df51 FB |
260 | #if defined(USE_DIRECT_JUMP) |
261 | ||
7316329a SW |
262 | #if defined(CONFIG_TCG_INTERPRETER) |
263 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
264 | { | |
265 | /* patch the branch destination */ | |
76442a93 | 266 | atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); |
7316329a SW |
267 | /* no need to flush icache explicitly */ |
268 | } | |
269 | #elif defined(_ARCH_PPC) | |
9171478c | 270 | void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); |
810260a8 | 271 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target |
57fec1fe | 272 | #elif defined(__i386__) || defined(__x86_64__) |
6375e09e | 273 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
4390df51 FB |
274 | { |
275 | /* patch the branch destination */ | |
0d07abf0 | 276 | atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); |
1235fc06 | 277 | /* no need to flush icache explicitly */ |
4390df51 | 278 | } |
a10c64e0 RH |
279 | #elif defined(__s390x__) |
280 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
281 | { | |
282 | /* patch the branch destination */ | |
283 | intptr_t disp = addr - (jmp_addr - 2); | |
ed3d51ec | 284 | atomic_set((int32_t *)jmp_addr, disp / 2); |
a10c64e0 RH |
285 | /* no need to flush icache explicitly */ |
286 | } | |
4a136e0a CF |
287 | #elif defined(__aarch64__) |
288 | void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); | |
289 | #define tb_set_jmp_target1 aarch64_tb_set_jmp_target | |
811d4cf4 | 290 | #elif defined(__arm__) |
7d14e0e2 SF |
291 | void arm_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); |
292 | #define tb_set_jmp_target1 arm_tb_set_jmp_target | |
b6bfeea9 | 293 | #elif defined(__sparc__) || defined(__mips__) |
5bbd2cae | 294 | void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); |
7316329a SW |
295 | #else |
296 | #error tb_set_jmp_target1 is missing | |
4390df51 | 297 | #endif |
d4e8164f | 298 | |
5fafdf24 | 299 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
6375e09e | 300 | int n, uintptr_t addr) |
4cbb86e1 | 301 | { |
f309101c | 302 | uint16_t offset = tb->jmp_insn_offset[n]; |
6375e09e | 303 | tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); |
4cbb86e1 FB |
304 | } |
305 | ||
d4e8164f FB |
306 | #else |
307 | ||
308 | /* set the jump target */ | |
5fafdf24 | 309 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
6375e09e | 310 | int n, uintptr_t addr) |
d4e8164f | 311 | { |
f309101c | 312 | tb->jmp_target_addr[n] = addr; |
d4e8164f FB |
313 | } |
314 | ||
315 | #endif | |
316 | ||
7d7500d9 | 317 | /* Called with tb_lock held. */ |
5fafdf24 | 318 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
319 | TranslationBlock *tb_next) |
320 | { | |
9962c478 SF |
321 | if (tb->jmp_list_next[n]) { |
322 | /* Another thread has already done this while we were | |
323 | * outside of the lock; nothing to do in this case */ | |
324 | return; | |
cf25629d | 325 | } |
9962c478 SF |
326 | qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, |
327 | "Linking TBs %p [" TARGET_FMT_lx | |
328 | "] index %d -> %p [" TARGET_FMT_lx "]\n", | |
329 | tb->tc_ptr, tb->pc, n, | |
330 | tb_next->tc_ptr, tb_next->pc); | |
331 | ||
332 | /* patch the native jump address */ | |
333 | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); | |
334 | ||
335 | /* add in TB jmp circular list */ | |
336 | tb->jmp_list_next[n] = tb_next->jmp_list_first; | |
337 | tb_next->jmp_list_first = (uintptr_t)tb | n; | |
d4e8164f FB |
338 | } |
339 | ||
01ecaf43 | 340 | /* GETPC is the true target of the return instruction that we'll execute. */ |
7316329a | 341 | #if defined(CONFIG_TCG_INTERPRETER) |
c3ca0467 | 342 | extern uintptr_t tci_tb_ptr; |
01ecaf43 | 343 | # define GETPC() tci_tb_ptr |
0f842f8a | 344 | #else |
01ecaf43 | 345 | # define GETPC() \ |
0f842f8a RH |
346 | ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) |
347 | #endif | |
348 | ||
349 | /* The true return address will often point to a host insn that is part of | |
350 | the next translated guest insn. Adjust the address backward to point to | |
351 | the middle of the call insn. Subtracting one would do the job except for | |
352 | several compressed mode architectures (arm, mips) which set the low bit | |
353 | to indicate the compressed mode; subtracting two works around that. It | |
354 | is also the case that there are no host isas that contain a call insn | |
355 | smaller than 4 bytes, so we don't worry about special-casing this. */ | |
a17d4482 | 356 | #define GETPC_ADJ 2 |
3917149d | 357 | |
e95c8d51 | 358 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 359 | |
9d82b5a7 | 360 | struct MemoryRegion *iotlb_to_region(CPUState *cpu, |
a54c87b6 | 361 | hwaddr index, MemTxAttrs attrs); |
b3755a91 | 362 | |
b35399bb SS |
363 | void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type, |
364 | int mmu_idx, uintptr_t retaddr); | |
6e59c1db | 365 | |
6e59c1db | 366 | #endif |
4390df51 FB |
367 | |
368 | #if defined(CONFIG_USER_ONLY) | |
8fd19e6c PB |
369 | void mmap_lock(void); |
370 | void mmap_unlock(void); | |
301e40ed | 371 | bool have_mmap_lock(void); |
8fd19e6c | 372 | |
9349b4f9 | 373 | static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) |
4390df51 FB |
374 | { |
375 | return addr; | |
376 | } | |
377 | #else | |
8fd19e6c PB |
378 | static inline void mmap_lock(void) {} |
379 | static inline void mmap_unlock(void) {} | |
380 | ||
0cac1b66 | 381 | /* cputlb.c */ |
9349b4f9 | 382 | tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); |
dfccc760 PC |
383 | |
384 | void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); | |
385 | void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); | |
386 | ||
387 | /* exec.c */ | |
388 | void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); | |
389 | ||
390 | MemoryRegionSection * | |
d7898cda PM |
391 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
392 | hwaddr *xlat, hwaddr *plen); | |
dfccc760 PC |
393 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
394 | MemoryRegionSection *section, | |
395 | target_ulong vaddr, | |
396 | hwaddr paddr, hwaddr xlat, | |
397 | int prot, | |
398 | target_ulong *address); | |
399 | bool memory_region_is_unassigned(MemoryRegion *mr); | |
400 | ||
4390df51 | 401 | #endif |
9df217a3 | 402 | |
1b530a6d AJ |
403 | /* vl.c */ |
404 | extern int singlestep; | |
405 | ||
e0c38211 | 406 | /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */ |
9373e632 | 407 | extern CPUState *tcg_current_cpu; |
e0c38211 | 408 | extern bool exit_request; |
1a28cac3 | 409 | |
875cdcf6 | 410 | #endif |