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cc05c43a PM |
1 | /* |
2 | * Memory transaction attributes | |
3 | * | |
4 | * Copyright (c) 2015 Linaro Limited. | |
5 | * | |
6 | * Authors: | |
7 | * Peter Maydell <peter.maydell@linaro.org> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | * | |
12 | */ | |
13 | ||
14 | #ifndef MEMATTRS_H | |
15 | #define MEMATTRS_H | |
16 | ||
17 | /* Every memory transaction has associated with it a set of | |
18 | * attributes. Some of these are generic (such as the ID of | |
19 | * the bus master); some are specific to a particular kind of | |
20 | * bus (such as the ARM Secure/NonSecure bit). We define them | |
21 | * all as non-overlapping bitfields in a single struct to avoid | |
22 | * confusion if different parts of QEMU used the same bit for | |
23 | * different semantics. | |
24 | */ | |
25 | typedef struct MemTxAttrs { | |
26 | /* Bus masters which don't specify any attributes will get this | |
27 | * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can | |
28 | * distinguish "all attributes deliberately clear" from | |
29 | * "didn't specify" if necessary. | |
30 | */ | |
31 | unsigned int unspecified:1; | |
4d6e1c64 RH |
32 | /* |
33 | * ARM/AMBA: TrustZone Secure access | |
f794aa4a PB |
34 | * x86: System Management Mode access |
35 | */ | |
8bf5b6a9 | 36 | unsigned int secure:1; |
4d6e1c64 RH |
37 | /* |
38 | * ARM: ArmSecuritySpace. This partially overlaps secure, but it is | |
39 | * easier to have both fields to assist code that does not understand | |
40 | * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). | |
41 | */ | |
42 | unsigned int space:2; | |
0995bf8c PM |
43 | /* Memory access is usermode (unprivileged) */ |
44 | unsigned int user:1; | |
3ab6fdc9 PMD |
45 | /* |
46 | * Bus interconnect and peripherals can access anything (memories, | |
47 | * devices) by default. By setting the 'memory' bit, bus transaction | |
48 | * are restricted to "normal" memories (per the AMBA documentation) | |
49 | * versus devices. Access to devices will be logged and rejected | |
50 | * (see MEMTX_ACCESS_ERROR). | |
51 | */ | |
52 | unsigned int memory:1; | |
a05f686f PF |
53 | /* Requester ID (for MSI for example) */ |
54 | unsigned int requester_id:16; | |
a26fc6f5 TN |
55 | /* Invert endianness for this page */ |
56 | unsigned int byte_swap:1; | |
d3765835 RH |
57 | /* |
58 | * The following are target-specific page-table bits. These are not | |
59 | * related to actual memory transactions at all. However, this structure | |
60 | * is part of the tlb_fill interface, cached in the cputlb structure, | |
61 | * and has unused bits. These fields will be read by target-specific | |
62 | * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. | |
63 | */ | |
64 | unsigned int target_tlb_bit0 : 1; | |
65 | unsigned int target_tlb_bit1 : 1; | |
66 | unsigned int target_tlb_bit2 : 1; | |
cc05c43a PM |
67 | } MemTxAttrs; |
68 | ||
69 | /* Bus masters which don't specify any attributes will get this, | |
70 | * which has all attribute bits clear except the topmost one | |
71 | * (so that we can distinguish "all attributes deliberately clear" | |
72 | * from "didn't specify" if necessary). | |
73 | */ | |
74 | #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) | |
75 | ||
3114d092 PM |
76 | /* New-style MMIO accessors can indicate that the transaction failed. |
77 | * A zero (MEMTX_OK) response means success; anything else is a failure | |
78 | * of some kind. The memory subsystem will bitwise-OR together results | |
79 | * if it is synthesizing an operation from multiple smaller accesses. | |
80 | */ | |
81 | #define MEMTX_OK 0 | |
82 | #define MEMTX_ERROR (1U << 0) /* device returned an error */ | |
83 | #define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ | |
3ab6fdc9 | 84 | #define MEMTX_ACCESS_ERROR (1U << 2) /* access denied */ |
3114d092 PM |
85 | typedef uint32_t MemTxResult; |
86 | ||
cc05c43a | 87 | #endif |