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1/*
2 * Memory transaction attributes
3 *
4 * Copyright (c) 2015 Linaro Limited.
5 *
6 * Authors:
7 * Peter Maydell <peter.maydell@linaro.org>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 */
13
14#ifndef MEMATTRS_H
15#define MEMATTRS_H
16
17/* Every memory transaction has associated with it a set of
18 * attributes. Some of these are generic (such as the ID of
19 * the bus master); some are specific to a particular kind of
20 * bus (such as the ARM Secure/NonSecure bit). We define them
21 * all as non-overlapping bitfields in a single struct to avoid
22 * confusion if different parts of QEMU used the same bit for
23 * different semantics.
24 */
25typedef struct MemTxAttrs {
26 /* Bus masters which don't specify any attributes will get this
27 * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
28 * distinguish "all attributes deliberately clear" from
29 * "didn't specify" if necessary.
30 */
31 unsigned int unspecified:1;
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32 /* ARM/AMBA: TrustZone Secure access
33 * x86: System Management Mode access
34 */
8bf5b6a9 35 unsigned int secure:1;
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36 /* Memory access is usermode (unprivileged) */
37 unsigned int user:1;
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38 /* Requester ID (for MSI for example) */
39 unsigned int requester_id:16;
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40} MemTxAttrs;
41
42/* Bus masters which don't specify any attributes will get this,
43 * which has all attribute bits clear except the topmost one
44 * (so that we can distinguish "all attributes deliberately clear"
45 * from "didn't specify" if necessary).
46 */
47#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
48
49#endif